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More H7 improvements. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13305 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-01-23 15:45:51 +00:00
parent 2748445dab
commit 9959f10872
8 changed files with 92 additions and 38 deletions
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11
demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h
View File

@ -32,6 +32,7 @@
*/ */
#define STM32H7xx_MCUCONF #define STM32H7xx_MCUCONF
#define STM32H742_MCUCONF
#define STM32H743_MCUCONF #define STM32H743_MCUCONF
#define STM32H753_MCUCONF #define STM32H753_MCUCONF
@ -52,6 +53,7 @@
* Reading STM32 Reference Manual is required. * Reading STM32 Reference Manual is required.
* Register constants are taken from the ST header. * Register constants are taken from the ST header.
*/ */
#define STM32_ODEN STM32_ODEN_DISABLED
#define STM32_VOS STM32_VOS_SCALE1 #define STM32_VOS STM32_VOS_SCALE1
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) #define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN) #define STM32_PWR_CR2 (PWR_CR2_BREN)
@ -225,12 +227,8 @@
/* /*
* CAN driver system settings. * CAN driver system settings.
*/ */
#define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE #define STM32_CAN_USE_FDCAN2 FALSE
#define STM32_CAN_USE_CAN3 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN3_IRQ_PRIORITY 11
/* /*
* DAC driver system settings. * DAC driver system settings.
@ -473,6 +471,5 @@
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure") #define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
#define STM32_USE_STM32_D1_WORKAROUND TRUE
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

3
os/hal/ports/STM32/STM32H7xx/hal_lld.c
View File

@ -102,6 +102,9 @@ static inline void init_pwr(void) {
PWR->CR3 = STM32_PWR_CR3; PWR->CR3 = STM32_PWR_CR3;
PWR->CPUCR = STM32_PWR_CPUCR; PWR->CPUCR = STM32_PWR_CPUCR;
PWR->D3CR = STM32_VOS; PWR->D3CR = STM32_VOS;
#if !defined(STM32_ENFORCE_H7_REV_V)
SYSCFG->PWRCR = STM32_ODEN;
#endif
while ((PWR->D3CR & PWR_D3CR_VOSRDY) == 0) while ((PWR->D3CR & PWR_D3CR_VOSRDY) == 0)
; ;
#if STM32_PWR_CR2 & PWR_CR2_BREN #if STM32_PWR_CR2 & PWR_CR2_BREN

14
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -645,13 +645,6 @@
#define STM32_PWR_CPUCR 0 #define STM32_PWR_CPUCR 0
#endif #endif
/**
* @brief VOS setting.
*/
#if !defined(STM32_VOS) || defined(__DOXYGEN__)
#define STM32_VOS STM32_VOS_SCALE1
#endif
/** /**
* @brief ODEN setting. * @brief ODEN setting.
*/ */
@ -659,6 +652,13 @@
#define STM32_ODEN STM32_ODEN_DISABLED #define STM32_ODEN STM32_ODEN_DISABLED
#endif #endif
/**
* @brief VOS setting.
*/
#if !defined(STM32_VOS) || defined(__DOXYGEN__)
#define STM32_VOS STM32_VOS_SCALE1
#endif
/** /**
* @brief Enables or disables the HSI clock source. * @brief Enables or disables the HSI clock source.
*/ */

23
testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -32,6 +32,7 @@
*/ */
#define STM32H7xx_MCUCONF #define STM32H7xx_MCUCONF
#define STM32H742_MCUCONF
#define STM32H743_MCUCONF #define STM32H743_MCUCONF
#define STM32H753_MCUCONF #define STM32H753_MCUCONF
@ -52,6 +53,7 @@
* Reading STM32 Reference Manual is required. * Reading STM32 Reference Manual is required.
* Register constants are taken from the ST header. * Register constants are taken from the ST header.
*/ */
#define STM32_ODEN STM32_ODEN_DISABLED
#define STM32_VOS STM32_VOS_SCALE1 #define STM32_VOS STM32_VOS_SCALE1
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) #define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN) #define STM32_PWR_CR2 (PWR_CR2_BREN)
@ -177,6 +179,10 @@
#define STM32_IRQ_EXTI19_PRIORITY 6 #define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_21_PRIORITY 6 #define STM32_IRQ_EXTI20_21_PRIORITY 6
#define STM32_IRQ_MDMA_PRIORITY 9
#define STM32_IRQ_QUADSPI1_PRIORITY 10
#define STM32_IRQ_TIM1_UP_PRIORITY 7 #define STM32_IRQ_TIM1_UP_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7
@ -221,12 +227,8 @@
/* /*
* CAN driver system settings. * CAN driver system settings.
*/ */
#define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE #define STM32_CAN_USE_FDCAN2 FALSE
#define STM32_CAN_USE_CAN3 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN3_IRQ_PRIORITY 11
/* /*
* DAC driver system settings. * DAC driver system settings.
@ -461,4 +463,13 @@
*/ */
#define STM32_WDG_USE_IWDG FALSE #define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

23
testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -32,6 +32,7 @@
*/ */
#define STM32H7xx_MCUCONF #define STM32H7xx_MCUCONF
#define STM32H742_MCUCONF
#define STM32H743_MCUCONF #define STM32H743_MCUCONF
#define STM32H753_MCUCONF #define STM32H753_MCUCONF
@ -52,6 +53,7 @@
* Reading STM32 Reference Manual is required. * Reading STM32 Reference Manual is required.
* Register constants are taken from the ST header. * Register constants are taken from the ST header.
*/ */
#define STM32_ODEN STM32_ODEN_DISABLED
#define STM32_VOS STM32_VOS_SCALE1 #define STM32_VOS STM32_VOS_SCALE1
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) #define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN) #define STM32_PWR_CR2 (PWR_CR2_BREN)
@ -177,6 +179,10 @@
#define STM32_IRQ_EXTI19_PRIORITY 6 #define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_21_PRIORITY 6 #define STM32_IRQ_EXTI20_21_PRIORITY 6
#define STM32_IRQ_MDMA_PRIORITY 9
#define STM32_IRQ_QUADSPI1_PRIORITY 10
#define STM32_IRQ_TIM1_UP_PRIORITY 7 #define STM32_IRQ_TIM1_UP_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7
@ -221,12 +227,8 @@
/* /*
* CAN driver system settings. * CAN driver system settings.
*/ */
#define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE #define STM32_CAN_USE_FDCAN2 FALSE
#define STM32_CAN_USE_CAN3 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN3_IRQ_PRIORITY 11
/* /*
* DAC driver system settings. * DAC driver system settings.
@ -461,4 +463,13 @@
*/ */
#define STM32_WDG_USE_IWDG FALSE #define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

23
testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -32,6 +32,7 @@
*/ */
#define STM32H7xx_MCUCONF #define STM32H7xx_MCUCONF
#define STM32H742_MCUCONF
#define STM32H743_MCUCONF #define STM32H743_MCUCONF
#define STM32H753_MCUCONF #define STM32H753_MCUCONF
@ -52,6 +53,7 @@
* Reading STM32 Reference Manual is required. * Reading STM32 Reference Manual is required.
* Register constants are taken from the ST header. * Register constants are taken from the ST header.
*/ */
#define STM32_ODEN STM32_ODEN_DISABLED
#define STM32_VOS STM32_VOS_SCALE1 #define STM32_VOS STM32_VOS_SCALE1
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) #define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN) #define STM32_PWR_CR2 (PWR_CR2_BREN)
@ -177,6 +179,10 @@
#define STM32_IRQ_EXTI19_PRIORITY 6 #define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_21_PRIORITY 6 #define STM32_IRQ_EXTI20_21_PRIORITY 6
#define STM32_IRQ_MDMA_PRIORITY 9
#define STM32_IRQ_QUADSPI1_PRIORITY 10
#define STM32_IRQ_TIM1_UP_PRIORITY 7 #define STM32_IRQ_TIM1_UP_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7
@ -221,12 +227,8 @@
/* /*
* CAN driver system settings. * CAN driver system settings.
*/ */
#define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE #define STM32_CAN_USE_FDCAN2 FALSE
#define STM32_CAN_USE_CAN3 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN3_IRQ_PRIORITY 11
/* /*
* DAC driver system settings. * DAC driver system settings.
@ -461,4 +463,13 @@
*/ */
#define STM32_WDG_USE_IWDG FALSE #define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

23
testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -32,6 +32,7 @@
*/ */
#define STM32H7xx_MCUCONF #define STM32H7xx_MCUCONF
#define STM32H742_MCUCONF
#define STM32H743_MCUCONF #define STM32H743_MCUCONF
#define STM32H753_MCUCONF #define STM32H753_MCUCONF
@ -52,6 +53,7 @@
* Reading STM32 Reference Manual is required. * Reading STM32 Reference Manual is required.
* Register constants are taken from the ST header. * Register constants are taken from the ST header.
*/ */
#define STM32_ODEN STM32_ODEN_DISABLED
#define STM32_VOS STM32_VOS_SCALE1 #define STM32_VOS STM32_VOS_SCALE1
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) #define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN) #define STM32_PWR_CR2 (PWR_CR2_BREN)
@ -177,6 +179,10 @@
#define STM32_IRQ_EXTI19_PRIORITY 6 #define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_21_PRIORITY 6 #define STM32_IRQ_EXTI20_21_PRIORITY 6
#define STM32_IRQ_MDMA_PRIORITY 9
#define STM32_IRQ_QUADSPI1_PRIORITY 10
#define STM32_IRQ_TIM1_UP_PRIORITY 7 #define STM32_IRQ_TIM1_UP_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7 #define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7 #define STM32_IRQ_TIM2_PRIORITY 7
@ -221,12 +227,8 @@
/* /*
* CAN driver system settings. * CAN driver system settings.
*/ */
#define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE #define STM32_CAN_USE_FDCAN2 FALSE
#define STM32_CAN_USE_CAN3 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#define STM32_CAN_CAN3_IRQ_PRIORITY 11
/* /*
* DAC driver system settings. * DAC driver system settings.
@ -461,4 +463,13 @@
*/ */
#define STM32_WDG_USE_IWDG FALSE #define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

10
tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl
View File

@ -64,6 +64,7 @@
* Reading STM32 Reference Manual is required. * Reading STM32 Reference Manual is required.
* Register constants are taken from the ST header. * Register constants are taken from the ST header.
*/ */
#define STM32_ODEN ${doc.STM32_ODEN!"STM32_ODEN_DISABLED"}
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_SCALE1"} #define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_SCALE1"}
#define STM32_PWR_CR1 ${doc.STM32_PWR_CR1!"(PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)"} #define STM32_PWR_CR1 ${doc.STM32_PWR_CR1!"(PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_BREN)"} #define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_BREN)"}
@ -473,4 +474,13 @@
*/ */
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"} #define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL ${doc.STM32_WSPI_QUADSPI1_MDMA_CHANNEL!"STM32_MDMA_CHANNEL_ID_ANY"}
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY ${doc.STM32_WSPI_QUADSPI1_MDMA_PRIORITY!"1"}
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) ${doc.STM32_WSPI_MDMA_ERROR_HOOK!"osalSysHalt(\"MDMA failure\")"}
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */