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L0 shared IRQ rework, mcuconfs to be updated. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12894 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-07-10 09:35:03 +00:00
parent 8c335fdcf7
commit 9d05564539
6 changed files with 227 additions and 154 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/halconf.h
View File

@ -177,7 +177,7 @@
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART TRUE
#define HAL_USE_UART FALSE
#endif
/**

6
demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/mcuconf.h
View File

@ -181,10 +181,10 @@
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 TRUE
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 TRUE
#define STM32_UART_USE_UART4 TRUE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY

19
demos/STM32/RT-STM32L073RZ-NUCLEO64/cfg/mcuconf.h
View File

@ -32,6 +32,8 @@
*/
#define STM32L0xx_MCUCONF
#define STM32L072_MCUCONF
#define STM32L073_MCUCONF
/*
* HAL driver system settings.
@ -76,6 +78,10 @@
#define STM32_IRQ_EXTI16_PRIORITY 3
#define STM32_IRQ_EXTI17_20_PRIORITY 3
#define STM32_IRQ_EXTI21_22_PRIORITY 3
#define STM32_IRQ_USART1_PRIORITY 3
#define STM32_IRQ_USART2_PRIORITY 3
#define STM32_IRQ_UART4_5_PRIORITY 3
#define STM32_IRQ_LPUART1_PRIORITY 3
/*
* ADC driver system settings.
@ -163,6 +169,7 @@
#define STM32_PWM_TIM21_IRQ_PRIORITY 3
#define STM32_PWM_USE_TIM22 FALSE
#define STM32_PWM_TIM22_IRQ_PRIORITY 3
/*
* SERIAL driver system settings.
*/
@ -171,10 +178,6 @@
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
#define STM32_SERIAL_USART1_PRIORITY 3
#define STM32_SERIAL_USART2_PRIORITY 3
#define STM32_SERIAL_USART3_8_PRIORITY 3
#define STM32_SERIAL_LPUART1_PRIORITY 3
/*
* SPI driver system settings.
@ -203,17 +206,19 @@
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USART1_IRQ_PRIORITY 3
#define STM32_UART_USART2_IRQ_PRIORITY 3
#define STM32_UART_USART3_8_IRQ_PRIORITY 3
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*

123
os/hal/ports/STM32/STM32L0xx/stm32_isr.c
View File

@ -129,9 +129,116 @@ OSAL_IRQ_HANDLER(Vector5C) {
OSAL_IRQ_EPILOGUE();
}
#endif
#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
#if HAL_USE_SERIAL || HAL_USE_UART || defined(__DOXYGEN__)
#if !defined(STM32_DISABLE_USART1_HANDLER)
#if STM32_SERIAL_USE_USART1 || STM32_UART_USE_USART1
/**
* @brief USART1 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_SERIAL
#if STM32_SERIAL_USE_USART1
sd_lld_serve_interrupt(&SD1);
#endif
#endif
#if HAL_USE_UART
#if STM32_UART_USE_USART1
uart_lld_serve_interrupt(&UARTD1);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if !defined(STM32_DISABLE_USART2_HANDLER)
#if STM32_SERIAL_USE_USART2 || STM32_UART_USE_USART2
/**
* @brief USART2 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_SERIAL
#if STM32_SERIAL_USE_USART2
sd_lld_serve_interrupt(&SD2);
#endif
#endif
#if HAL_USE_UART
#if STM32_UART_USE_USART2
uart_lld_serve_interrupt(&UARTD2);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if !defined(STM32_DISABLE_UART4_5_HANDLER)
#if STM32_SERIAL_USE_UART4 || STM32_SERIAL_USE_UART5 || \
STM32_UART_USE_UART4 || STM32_UART_USE_UART5
/**
* @brief UART4 and 5 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_UART4_5_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_SERIAL
#if STM32_SERIAL_USE_UART4
sd_lld_serve_interrupt(&SD4);
#endif
#if STM32_SERIAL_USE_UART5
sd_lld_serve_interrupt(&SD5);
#endif
#endif
#if HAL_USE_UART
#if STM32_UART_USE_UART4
uart_lld_serve_interrupt(&UARTD4);
#endif
#if STM32_UART_USE_UART5
uart_lld_serve_interrupt(&UARTD5);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if !defined(STM32_DISABLE_LPUART1_HANDLER)
#if STM32_SERIAL_USE_LPUART1
/**
* @brief LPUART1 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_LPUART1_HANDLER) {
OSAL_IRQ_PROLOGUE();
sd_lld_serve_interrupt(&LPSD1);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#endif /* HAL_USE_SERIAL || HAL_USE_UART */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@ -149,6 +256,13 @@ void irqInit(void) {
nvicEnableVector(STM32_EXTI_LINE4_15_NUMBER, STM32_IRQ_EXTI4_15_PRIORITY);
nvicEnableVector(STM32_EXTI_LINE16_NUMBER, STM32_IRQ_EXTI16_PRIORITY);
#endif
#if HAL_USE_SERIAL || HAL_USE_UART
nvicEnableVector(STM32_USART1_NUMBER, STM32_IRQ_USART1_PRIORITY);
nvicEnableVector(STM32_USART2_NUMBER, STM32_IRQ_USART2_PRIORITY);
nvicEnableVector(STM32_UART4_5_NUMBER, STM32_IRQ_UART4_5_PRIORITY);
nvicEnableVector(STM32_LPUART1_NUMBER, STM32_IRQ_LPUART1_PRIORITY);
#endif
}
/**
@ -165,6 +279,13 @@ void irqDeinit(void) {
nvicDisableVector(STM32_EXTI_LINE16_NUMBER);
nvicDisableVector(STM32_EXTI_LINE2122_NUMBER);
#endif
#if HAL_USE_SERIAL || HAL_USE_UART
nvicDisableVector(STM32_USART1_NUMBER);
nvicDisableVector(STM32_USART2_NUMBER);
nvicDisableVector(STM32_UART4_5_NUMBER);
nvicDisableVector(STM32_LPUART1_NUMBER);
#endif
}
/** @} */

89
os/hal/ports/STM32/STM32L0xx/stm32_isr.h
View File

@ -29,6 +29,51 @@
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISRs suppressed in standard drivers
* @{
*/
#define STM32_USART1_SUPPRESS_ISR
#define STM32_USART2_SUPPRESS_ISR
#define STM32_UART4_SUPPRESS_ISR
#define STM32_UART5_SUPPRESS_ISR
#define STM32_LPUART1_SUPPRESS_ISR
/** @} */
/**
* @name ISR names and numbers remapping
* @{
*/
/*
* EXTI unit.
*/
#define STM32_EXTI_LINE01_HANDLER Vector54
#define STM32_EXTI_LINE23_HANDLER Vector58
#define STM32_EXTI_LINE4_15_HANDLER Vector5C
#define STM32_EXTI_LINE16_HANDLER Vector44
#define STM32_EXTI_LINE171920_HANDLER Vector48
#define STM32_EXTI_LINE2122_HANDLER Vector70
#define STM32_EXTI_LINE01_NUMBER 5
#define STM32_EXTI_LINE23_NUMBER 6
#define STM32_EXTI_LINE4_15_NUMBER 7
#define STM32_EXTI_LINE16_NUMBER 1
#define STM32_EXTI_LINE171920_NUMBER 2
#define STM32_EXTI_LINE2122_NUMBER 12
/*
* USART/UART units.
*/
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART2_HANDLER VectorB0
#define STM32_UART4_5_HANDLER Vector78
#define STM32_LPUART1_HANDLER VectorB4
#define STM32_USART1_NUMBER 27
#define STM32_USART2_NUMBER 28
#define STM32_UART4_5_NUMBER 14
#define STM32_LPUART1_NUMBER 29
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -78,6 +123,34 @@
#if !defined(STM32_IRQ_EXTI21_22_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI21_22_PRIORITY 3
#endif
/**
* @brief USART1 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_USART1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_USART1_PRIORITY 3
#endif
/**
* @brief USART2 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_USART2_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_USART2_PRIORITY 3
#endif
/**
* @brief UART4 and 5 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_UART4_5_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_UART4_5_PRIORITY 3
#endif
/**
* @brief LPUART1 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_LPUART1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_LPUART1_PRIORITY 3
#endif
/** @} */
/*===========================================================================*/
@ -109,6 +182,22 @@
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_22_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART1_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_USART1_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART2_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_USART2_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_UART4_5_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_UART4_5_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_LPUART1_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_LPUART1_PRIORITY"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/

142
os/hal/ports/STM32/STM32L0xx/stm32_registry.h
View File

@ -120,20 +120,6 @@
#define STM32_EXTI_NUM_LINES 23
#define STM32_EXTI_IMR1_MASK 0xFF840000U
#define STM32_EXTI_LINE01_HANDLER Vector54
#define STM32_EXTI_LINE23_HANDLER Vector58
#define STM32_EXTI_LINE4_15_HANDLER Vector5C
#define STM32_EXTI_LINE16_HANDLER Vector44
#define STM32_EXTI_LINE171920_HANDLER Vector48
#define STM32_EXTI_LINE2122_HANDLER Vector70
#define STM32_EXTI_LINE01_NUMBER 5
#define STM32_EXTI_LINE23_NUMBER 6
#define STM32_EXTI_LINE4_15_NUMBER 7
#define STM32_EXTI_LINE16_NUMBER 1
#define STM32_EXTI_LINE171920_NUMBER 2
#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -223,8 +209,6 @@
/* USART attributes.*/
#define STM32_HAS_USART2 TRUE
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART2_NUMBER 28
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_USART2_RX_DMA_CHN 0x00440000
@ -233,8 +217,6 @@
#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_LPUART1 TRUE
#define STM32_LPUART1_HANDLER VectorB4
#define STM32_LPUART1_NUMBER 29
#define STM32_HAS_USART1 FALSE
#define STM32_HAS_USART3 FALSE
@ -331,20 +313,6 @@
#define STM32_EXTI_NUM_LINES 23
#define STM32_EXTI_IMR1_MASK 0xFF840000U
#define STM32_EXTI_LINE01_HANDLER Vector54
#define STM32_EXTI_LINE23_HANDLER Vector58
#define STM32_EXTI_LINE4_15_HANDLER Vector5C
#define STM32_EXTI_LINE16_HANDLER Vector44
#define STM32_EXTI_LINE171920_HANDLER Vector48
#define STM32_EXTI_LINE2122_HANDLER Vector70
#define STM32_EXTI_LINE01_NUMBER 5
#define STM32_EXTI_LINE23_NUMBER 6
#define STM32_EXTI_LINE4_15_NUMBER 7
#define STM32_EXTI_LINE16_NUMBER 1
#define STM32_EXTI_LINE171920_NUMBER 2
#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -437,8 +405,6 @@
/* USART attributes.*/
#define STM32_HAS_USART2 TRUE
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART2_NUMBER 28
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_USART2_RX_DMA_CHN 0x00440000
@ -447,8 +413,6 @@
#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_LPUART1 TRUE
#define STM32_LPUART1_HANDLER VectorB4
#define STM32_LPUART1_NUMBER 29
#define STM32_HAS_USART1 FALSE
#define STM32_HAS_USART3 FALSE
@ -545,20 +509,6 @@
#define STM32_EXTI_NUM_LINES 23
#define STM32_EXTI_IMR1_MASK 0xFF840000U
#define STM32_EXTI_LINE01_HANDLER Vector54
#define STM32_EXTI_LINE23_HANDLER Vector58
#define STM32_EXTI_LINE4_15_HANDLER Vector5C
#define STM32_EXTI_LINE16_HANDLER Vector44
#define STM32_EXTI_LINE171920_HANDLER Vector48
#define STM32_EXTI_LINE2122_HANDLER Vector70
#define STM32_EXTI_LINE01_NUMBER 5
#define STM32_EXTI_LINE23_NUMBER 6
#define STM32_EXTI_LINE4_15_NUMBER 7
#define STM32_EXTI_LINE16_NUMBER 1
#define STM32_EXTI_LINE171920_NUMBER 2
#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -673,8 +623,6 @@
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART1_NUMBER 27
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART1_RX_DMA_CHN 0x00030300
@ -683,8 +631,6 @@
#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART2_NUMBER 28
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_USART2_RX_DMA_CHN 0x00440000
@ -693,8 +639,6 @@
#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_LPUART1 TRUE
#define STM32_LPUART1_HANDLER VectorB4
#define STM32_LPUART1_NUMBER 29
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
@ -793,20 +737,6 @@
#define STM32_EXTI_NUM_LINES 23
#define STM32_EXTI_IMR1_MASK 0xFF840000U
#define STM32_EXTI_LINE01_HANDLER Vector54
#define STM32_EXTI_LINE23_HANDLER Vector58
#define STM32_EXTI_LINE4_15_HANDLER Vector5C
#define STM32_EXTI_LINE16_HANDLER Vector44
#define STM32_EXTI_LINE171920_HANDLER Vector48
#define STM32_EXTI_LINE2122_HANDLER Vector70
#define STM32_EXTI_LINE01_NUMBER 5
#define STM32_EXTI_LINE23_NUMBER 6
#define STM32_EXTI_LINE4_15_NUMBER 7
#define STM32_EXTI_LINE16_NUMBER 1
#define STM32_EXTI_LINE171920_NUMBER 2
#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -917,8 +847,6 @@
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART1_NUMBER 27
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART1_RX_DMA_CHN 0x00030300
@ -927,8 +855,6 @@
#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART2_NUMBER 28
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_USART2_RX_DMA_CHN 0x00440000
@ -937,8 +863,6 @@
#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_LPUART1 TRUE
#define STM32_LPUART1_HANDLER VectorB4
#define STM32_LPUART1_NUMBER 29
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
@ -1045,20 +969,6 @@
#define STM32_EXTI_NUM_LINES 23
#define STM32_EXTI_IMR1_MASK 0xFF840000U
#define STM32_EXTI_LINE01_HANDLER Vector54
#define STM32_EXTI_LINE23_HANDLER Vector58
#define STM32_EXTI_LINE4_15_HANDLER Vector5C
#define STM32_EXTI_LINE16_HANDLER Vector44
#define STM32_EXTI_LINE171920_HANDLER Vector48
#define STM32_EXTI_LINE2122_HANDLER Vector70
#define STM32_EXTI_LINE01_NUMBER 5
#define STM32_EXTI_LINE23_NUMBER 6
#define STM32_EXTI_LINE4_15_NUMBER 7
#define STM32_EXTI_LINE16_NUMBER 1
#define STM32_EXTI_LINE171920_NUMBER 2
#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -1169,8 +1079,6 @@
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART1_NUMBER 27
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART1_RX_DMA_CHN 0x00030300
@ -1179,8 +1087,6 @@
#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART2_NUMBER 28
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_USART2_RX_DMA_CHN 0x00440000
@ -1189,8 +1095,6 @@
#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_LPUART1 TRUE
#define STM32_LPUART1_HANDLER VectorB4
#define STM32_LPUART1_NUMBER 29
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
@ -1299,20 +1203,6 @@
#define STM32_EXTI_NUM_LINES 23
#define STM32_EXTI_IMR1_MASK 0xFF840000U
#define STM32_EXTI_LINE01_HANDLER Vector54
#define STM32_EXTI_LINE23_HANDLER Vector58
#define STM32_EXTI_LINE4_15_HANDLER Vector5C
#define STM32_EXTI_LINE16_HANDLER Vector44
#define STM32_EXTI_LINE171920_HANDLER Vector48
#define STM32_EXTI_LINE2122_HANDLER Vector70
#define STM32_EXTI_LINE01_NUMBER 5
#define STM32_EXTI_LINE23_NUMBER 6
#define STM32_EXTI_LINE4_15_NUMBER 7
#define STM32_EXTI_LINE16_NUMBER 1
#define STM32_EXTI_LINE171920_NUMBER 2
#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -1442,8 +1332,6 @@
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART1_NUMBER 27
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART1_RX_DMA_CHN 0x00030300
@ -1452,8 +1340,6 @@
#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART2_NUMBER 28
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_USART2_RX_DMA_CHN 0x00440000
@ -1461,9 +1347,6 @@
STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_USART3_8_HANDLER Vector78
#define STM32_USART3_8_NUMBER 14
#define STM32_HAS_UART4 TRUE
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
@ -1481,8 +1364,6 @@
#define STM32_UART5_TX_DMA_CHN 0x0D000D00
#define STM32_HAS_LPUART1 TRUE
#define STM32_LPUART1_HANDLER VectorB4
#define STM32_LPUART1_NUMBER 29
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_USART6 FALSE
@ -1589,20 +1470,6 @@
#define STM32_EXTI_NUM_LINES 23
#define STM32_EXTI_IMR1_MASK 0xFF840000U
#define STM32_EXTI_LINE01_HANDLER Vector54
#define STM32_EXTI_LINE23_HANDLER Vector58
#define STM32_EXTI_LINE4_15_HANDLER Vector5C
#define STM32_EXTI_LINE16_HANDLER Vector44
#define STM32_EXTI_LINE171920_HANDLER Vector48
#define STM32_EXTI_LINE2122_HANDLER Vector70
#define STM32_EXTI_LINE01_NUMBER 5
#define STM32_EXTI_LINE23_NUMBER 6
#define STM32_EXTI_LINE4_15_NUMBER 7
#define STM32_EXTI_LINE16_NUMBER 1
#define STM32_EXTI_LINE171920_NUMBER 2
#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -1732,8 +1599,6 @@
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART1_NUMBER 27
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART1_RX_DMA_CHN 0x00030300
@ -1742,8 +1607,6 @@
#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART2_NUMBER 28
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_USART2_RX_DMA_CHN 0x00440000
@ -1751,9 +1614,6 @@
STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_USART3_8_HANDLER Vector78
#define STM32_USART3_8_NUMBER 14
#define STM32_HAS_UART4 TRUE
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
@ -1771,8 +1631,6 @@
#define STM32_UART5_TX_DMA_CHN 0x0D000D00
#define STM32_HAS_LPUART1 TRUE
#define STM32_LPUART1_HANDLER VectorB4
#define STM32_LPUART1_NUMBER 29
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_USART6 FALSE