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Mass update of G4 mcuconf.h files. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14374 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-05-15 12:03:30 +00:00
parent 50aac6e69f
commit 9f705c9d30
12 changed files with 11 additions and 4 deletions
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1
demos/STM32/NIL-STM32G474RE-NUCLEO64/cfg/mcuconf.h
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@ -41,6 +41,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)

1
demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h
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@ -39,6 +39,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)

1
demos/STM32/RT-STM32G474RE-DISCOVERY-DPOW1/cfg/mcuconf.h
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@ -41,6 +41,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)

1
demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
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@ -41,6 +41,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)

1
demos/various/RT-TEST-Latency/cfg/stm32g474re_nucleo64/mcuconf.h
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@ -41,6 +41,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)

4
os/hal/include/hal.h
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@ -42,10 +42,6 @@
#define HAL_USE_CAN FALSE
#endif
#if !defined(HAL_USE_CLK)
#define HAL_USE_CLK FALSE
#endif
#if !defined(HAL_USE_CRY)
#define HAL_USE_CRY FALSE
#endif

1
testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/mcuconf.h
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@ -41,6 +41,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)

1
testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h
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@ -41,6 +41,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)

1
testrt/IRQ_STORM/cfg/stm32g474re_nucleo64/mcuconf.h
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@ -41,6 +41,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)

1
testrt/VT_STORM/cfg/stm32g474re_nucleo64/mcuconf.h
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@ -41,6 +41,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)

1
tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl
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@ -50,6 +50,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
#define STM32_CLOCK_DYNAMIC ${doc.STM32_CLOCK_DYNAMIC!"FALSE"}
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"}
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}

1
tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl
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@ -52,6 +52,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
#define STM32_CLOCK_DYNAMIC ${doc.STM32_CLOCK_DYNAMIC!"FALSE"}
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"}
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}