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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13548 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2020-04-21 09:05:22 +00:00
parent 002cbe6e55
commit a3bc53d6a7
5 changed files with 30 additions and 198 deletions
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45
demos/STM32/RT-STM32L552ZE-NUCLEO144-TZ_GUEST/cfg/mcuconf.h
View File

@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -22,8 +22,7 @@
* driver is enabled in halconf.h. * driver is enabled in halconf.h.
* *
* IRQ priorities: * IRQ priorities:
* 7...0 Lowest...Highest (non-secure mode). * 7...0 Lowest...Highest.
* 3...0 Lowest...Highest (secure mode).
* *
* DMA priorities: * DMA priorities:
* 0...3 Lowest...Highest. * 0...3 Lowest...Highest.
@ -66,6 +65,7 @@
/* /*
* Clock settings. * Clock settings.
*/ */
#define STM32_RCC_SECCFGR (RCC_SECCFGR_MSISEC | RCC_SECCFGR_PLLSEC | RCC_SECCFGR_SYSCLKSEC | RCC_SECCFGR_PRESCSEC)
#define STM32_HSI16_ENABLED TRUE #define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE
@ -262,22 +262,6 @@
/* /*
* SPI driver system settings. * SPI driver system settings.
*/ */
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 5
#define STM32_SPI_SPI2_IRQ_PRIORITY 5
#define STM32_SPI_SPI3_IRQ_PRIORITY 5
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/* /*
* ST driver system settings. * ST driver system settings.
@ -288,32 +272,10 @@
/* /*
* TRNG driver system settings. * TRNG driver system settings.
*/ */
#define STM32_TRNG_USE_RNG1 FALSE
/* /*
* UART driver system settings. * UART driver system settings.
*/ */
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/* /*
* USB driver system settings. * USB driver system settings.
@ -329,3 +291,4 @@
*/ */
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

42
demos/STM32/RT-STM32L552ZE-NUCLEO144-TZ_HOST/cfg/mcuconf.h
View File

@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -23,7 +23,6 @@
* *
* IRQ priorities: * IRQ priorities:
* 7...0 Lowest...Highest. * 7...0 Lowest...Highest.
* 3...0 Lowest...Highest (trusted mode).
* *
* DMA priorities: * DMA priorities:
* 0...3 Lowest...Highest. * 0...3 Lowest...Highest.
@ -263,22 +262,6 @@
/* /*
* SPI driver system settings. * SPI driver system settings.
*/ */
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 5
#define STM32_SPI_SPI2_IRQ_PRIORITY 5
#define STM32_SPI_SPI3_IRQ_PRIORITY 5
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/* /*
* ST driver system settings. * ST driver system settings.
@ -289,32 +272,10 @@
/* /*
* TRNG driver system settings. * TRNG driver system settings.
*/ */
#define STM32_TRNG_USE_RNG1 FALSE
/* /*
* UART driver system settings. * UART driver system settings.
*/ */
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/* /*
* USB driver system settings. * USB driver system settings.
@ -330,3 +291,4 @@
*/ */
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

47
demos/STM32/RT-STM32L552ZE-NUCLEO144/cfg/mcuconf.h
View File

@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -35,6 +35,11 @@
#define STM32L552_MCUCONF #define STM32L552_MCUCONF
#define STM32L562_MCUCONF #define STM32L562_MCUCONF
/*
* Secure mode HAL settings.
*/
#define STM32_SECURE_MODE TRUE
/* /*
* HAL driver global settings. * HAL driver global settings.
*/ */
@ -60,6 +65,7 @@
/* /*
* Clock settings. * Clock settings.
*/ */
#define STM32_RCC_SECCFGR (RCC_SECCFGR_MSISEC | RCC_SECCFGR_PLLSEC | RCC_SECCFGR_SYSCLKSEC | RCC_SECCFGR_PRESCSEC)
#define STM32_HSI16_ENABLED TRUE #define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE
@ -256,22 +262,6 @@
/* /*
* SPI driver system settings. * SPI driver system settings.
*/ */
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 5
#define STM32_SPI_SPI2_IRQ_PRIORITY 5
#define STM32_SPI_SPI3_IRQ_PRIORITY 5
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/* /*
* ST driver system settings. * ST driver system settings.
@ -282,32 +272,10 @@
/* /*
* TRNG driver system settings. * TRNG driver system settings.
*/ */
#define STM32_TRNG_USE_RNG1 FALSE
/* /*
* UART driver system settings. * UART driver system settings.
*/ */
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/* /*
* USB driver system settings. * USB driver system settings.
@ -323,3 +291,4 @@
*/ */
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

47
demos/various/RT-TEST-Latency/cfg/stm32l552ze_nucleo144/mcuconf.h
View File

@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -35,6 +35,11 @@
#define STM32L552_MCUCONF #define STM32L552_MCUCONF
#define STM32L562_MCUCONF #define STM32L562_MCUCONF
/*
* Secure mode HAL settings.
*/
#define STM32_SECURE_MODE TRUE
/* /*
* HAL driver global settings. * HAL driver global settings.
*/ */
@ -60,6 +65,7 @@
/* /*
* Clock settings. * Clock settings.
*/ */
#define STM32_RCC_SECCFGR (RCC_SECCFGR_MSISEC | RCC_SECCFGR_PLLSEC | RCC_SECCFGR_SYSCLKSEC | RCC_SECCFGR_PRESCSEC)
#define STM32_HSI16_ENABLED TRUE #define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE
@ -256,22 +262,6 @@
/* /*
* SPI driver system settings. * SPI driver system settings.
*/ */
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 5
#define STM32_SPI_SPI2_IRQ_PRIORITY 5
#define STM32_SPI_SPI3_IRQ_PRIORITY 5
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/* /*
* ST driver system settings. * ST driver system settings.
@ -282,32 +272,10 @@
/* /*
* TRNG driver system settings. * TRNG driver system settings.
*/ */
#define STM32_TRNG_USE_RNG1 FALSE
/* /*
* UART driver system settings. * UART driver system settings.
*/ */
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/* /*
* USB driver system settings. * USB driver system settings.
@ -323,3 +291,4 @@
*/ */
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

47
demos/various/RT-TEST-Latency/cfg/stm32l552ze_nucleo144_alt/mcuconf.h
View File

@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -35,6 +35,11 @@
#define STM32L552_MCUCONF #define STM32L552_MCUCONF
#define STM32L562_MCUCONF #define STM32L562_MCUCONF
/*
* Secure mode HAL settings.
*/
#define STM32_SECURE_MODE TRUE
/* /*
* HAL driver global settings. * HAL driver global settings.
*/ */
@ -60,6 +65,7 @@
/* /*
* Clock settings. * Clock settings.
*/ */
#define STM32_RCC_SECCFGR (RCC_SECCFGR_MSISEC | RCC_SECCFGR_PLLSEC | RCC_SECCFGR_SYSCLKSEC | RCC_SECCFGR_PRESCSEC)
#define STM32_HSI16_ENABLED TRUE #define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE
@ -256,22 +262,6 @@
/* /*
* SPI driver system settings. * SPI driver system settings.
*/ */
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 5
#define STM32_SPI_SPI2_IRQ_PRIORITY 5
#define STM32_SPI_SPI3_IRQ_PRIORITY 5
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/* /*
* ST driver system settings. * ST driver system settings.
@ -282,32 +272,10 @@
/* /*
* TRNG driver system settings. * TRNG driver system settings.
*/ */
#define STM32_TRNG_USE_RNG1 FALSE
/* /*
* UART driver system settings. * UART driver system settings.
*/ */
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/* /*
* USB driver system settings. * USB driver system settings.
@ -323,3 +291,4 @@
*/ */
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */