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More clock tree definitions. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14815 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-09-21 14:22:22 +00:00
parent 8f6f9086cd
commit ade12538d6
2 changed files with 38 additions and 4 deletions
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4
os/hal/boards/ST_STM32MP157A_DK1/board.h
View File

@ -33,7 +33,7 @@
/* /*
* Board identifier. * Board identifier.
*/ */
#define BOARD_ST_STM32L476_DISCOVERY #define BOARD_ST_STM32MP157A_DK1
#define BOARD_NAME "STMicroelectronics STM32MP157A-DK1" #define BOARD_NAME "STMicroelectronics STM32MP157A-DK1"
/* /*
@ -44,6 +44,8 @@
#define STM32_LSECLK 32768U #define STM32_LSECLK 32768U
#endif #endif
#define STM32_LSEDRV (3U << 3U)
#if !defined(STM32_HSECLK) #if !defined(STM32_HSECLK)
#define STM32_HSECLK 24000000U #define STM32_HSECLK 24000000U
#endif #endif

38
os/hal/ports/STM32/STM32MP1xx/hal_lld.h
View File

@ -111,6 +111,16 @@
#define STM32_PLL4SRC_I2S_CKIN (3 << 0) /**< PLL4 clock source is I2SCK.*/ #define STM32_PLL4SRC_I2S_CKIN (3 << 0) /**< PLL4 clock source is I2SCK.*/
/** @} */ /** @} */
/**
* @name RCC_MSSCKSELR register bits definitions
* @{
*/
#define STM32_MCUSSRC_HSI (0 << 0) /**< MCU clock source is HSI. */
#define STM32_MCUSSRC_HSE (1 << 0) /**< MCU clock source is HSE. */
#define STM32_MCUSSRC_CSI (2 << 0) /**< MCU clock source is CSI. */
#define STM32_MCUSSRC_PLL3P (3 << 0) /**< MCU clock source is PLL3P.*/
/** @} */
/** /**
* @name RCC_CPERCKSELR register bits definitions * @name RCC_CPERCKSELR register bits definitions
* @{ * @{
@ -190,7 +200,7 @@
/** /**
* @brief Enables or disables the HSI64 clock source. * @brief Enables or disables the HSI64 clock source.
* @note This initialization is performed only if TZEN=0 * @note This initialization is performed only if TZEN=0 or MCKPROT=0
* otherwise the setting must match the initialization performed * otherwise the setting must match the initialization performed
* on the Cortex-A side. * on the Cortex-A side.
*/ */
@ -210,7 +220,7 @@
/** /**
* @brief Enables or disables the HSE clock source. * @brief Enables or disables the HSE clock source.
* @note This initialization is performed only if TZEN=0 * @note This initialization is performed only if TZEN=0 or MCKPROT=0
* otherwise the setting must match the initialization performed * otherwise the setting must match the initialization performed
* on the Cortex-A side. * on the Cortex-A side.
*/ */
@ -347,7 +357,7 @@
* on the Cortex-A side. * on the Cortex-A side.
*/ */
#if !defined(STM32_MCUSSRC) || defined(__DOXYGEN__) #if !defined(STM32_MCUSSRC) || defined(__DOXYGEN__)
#define STM32_MCUSSRC 2222222222 #define STM32_MCUSSRC STM32_MCUSSRC_PLL3P
#endif #endif
/** /**
@ -652,6 +662,28 @@
/* Inclusion of PLL-related checks and calculations.*/ /* Inclusion of PLL-related checks and calculations.*/
#include <stm32_pll3.inc> #include <stm32_pll3.inc>
/**
* @brief MCU system clock source.
*/
#if STM32_NO_INIT || defined(__DOXYGEN__)
#define STM32_MCUSS_CK STM32_CSICLK
#elif (STM32_MCUSSRC == STM32_MCUSSRC_HSI)
#define STM32_MCUSS_CK STM32_HSI64CLK
#elif (STM32_MCUSSRC == STM32_MCUSSRC_HSE)
#define STM32_MCUSS_CK STM32_HSECLK
#elif (STM32_MCUSSRC == STM32_MCUSSRC_CSI)
#define STM32_MCUSS_CK STM32_CSICLK
#elif (STM32_MCUSSRC == STM32_MCUSSRC_PLL3P)
#define STM32_MCUSS_CK STM32_PLL3_P_CLKOUT
#else
#error "invalid STM32_MCUSSRC value specified"
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver data structures and types. */ /* Driver data structures and types. */
/*===========================================================================*/ /*===========================================================================*/