andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Implemented TIMPRE setting for STM32F7xx HAL. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12881 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-07-07 13:40:51 +00:00
parent 22267b3fa2
commit b80e79d47f
27 changed files with 55 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
demos/STM32/NASA-OSAL-STM32F746G-DISCOVERY/cfg/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/NIL-STM32F746G-DISCOVERY/cfg/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/RT-STM32-LWIP-FATFS-USB-HTTPS/cfg/stm32f746_discovery/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f746_discovery/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f769_discovery/mcuconf.h
View File

@ -65,6 +65,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/RT-STM32F722ZE-NUCLEO144/cfg/mcuconf.h
View File

@ -64,6 +64,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/RT-STM32F746G-DISCOVERY/cfg/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/RT-STM32F746ZG-NUCLEO144/cfg/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/RT-STM32F756ZG-NUCLEO144/cfg/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/RT-STM32F767ZI-NUCLEO144/cfg/mcuconf.h
View File

@ -65,6 +65,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
demos/STM32/RT-STM32F769I-DISCOVERY/cfg/mcuconf.h
View File

@ -65,6 +65,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

3
os/hal/ports/STM32/STM32F7xx/hal_lld.c
View File

@ -274,6 +274,9 @@ void stm32_clock_init(void) {
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr1 |= STM32_SAI1SEL;
#endif
#if STM32_TIMPRE_ENABLE == TRUE
dckcfgr1 |= RCC_DCKCFGR1_TIMPRE;
#endif
RCC->DCKCFGR1 = dckcfgr1;
}

27
os/hal/ports/STM32/STM32F7xx/hal_lld.h
View File

@ -650,6 +650,13 @@
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#endif
/**
* @brief TIM clock prescaler selection.
*/
#if !defined(STM32_TIMPRE_ENABLE) || defined(__DOXYGEN__)
#define STM32_TIMPRE_ENABLE FALSE
#endif
/**
* @brief I2S clock source.
*/
@ -2061,20 +2068,40 @@
/**
* @brief Clock of timers connected to APB1
*/
#if (STM32_TIMPRE_ENABLE == FALSE) || defined(__DOXYGEN__)
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
#endif
#else
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
(STM32_PPRE1 == STM32_PPRE1_DIV2) || \
(STM32_PPRE1 == STM32_PPRE1_DIV4)
#define STM32_TIMCLK1 (STM32_HCLK * 1)
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
#endif
#endif
/**
* @brief Clock of timers connected to APB2.
*/
#if (STM32_TIMPRE_ENABLE == FALSE) || defined(__DOXYGEN__)
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
#endif
#else
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || \
(STM32_PPRE2 == STM32_PPRE2_DIV2) || \
(STM32_PPRE2 == STM32_PPRE2_DIV4)
#define STM32_TIMCLK2 (STM32_HCLK * 1)
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
#endif
#endif
/**
* @brief Flash settings.

1
readme.txt
View File

@ -74,6 +74,7 @@
*****************************************************************************
*** Next ***
- NEW: Implemented TIMPRE setting for STM32F7xx HAL.
- NEW: Merged FatFS 0.13c.
- NEW: Added a "library generator" project for RT, it allows to
generate a library with a pre-configured RT. It also includes

1
testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
testhal/STM32/STM32F7xx/SPI/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
testhal/STM32/STM32F7xx/USB_RAW/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
testhal/STM32/multi/CRYPTO/cfg/stm32f756zg_nucleo144/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
testhal/STM32/multi/PAL/cfg/stm32f746_discovery/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
testhal/STM32/multi/RTC/cfg/stm32f746_discovery/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
testhal/STM32/multi/UART/cfg/stm32f746_discovery/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
testhal/STM32/multi/USB_CDC/cfg/stm32f746_discovery/mcuconf.h
View File

@ -62,6 +62,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_TIMPRE_ENABLE FALSE
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4

1
tools/ftl/processors/conf/mcuconf_stm32f72xxx/mcuconf.h.ftl
View File

@ -75,6 +75,7 @@
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV4"}
#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"FALSE"}
#define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_OFF"}
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
#define STM32_PLLI2SP_VALUE ${doc.STM32_PLLI2SP_VALUE!"4"}

1
tools/ftl/processors/conf/mcuconf_stm32f746xx/mcuconf.h.ftl
View File

@ -73,6 +73,7 @@
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV4"}
#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"FALSE"}
#define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_OFF"}
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
#define STM32_PLLI2SP_VALUE ${doc.STM32_PLLI2SP_VALUE!"4"}

1
tools/ftl/processors/conf/mcuconf_stm32f76xxx/mcuconf.h.ftl
View File

@ -76,6 +76,7 @@
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV4"}
#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"FALSE"}
#define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_OFF"}
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
#define STM32_PLLI2SP_VALUE ${doc.STM32_PLLI2SP_VALUE!"4"}