Few fixes, split registry for H7A3.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15602 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
9a7e267936
commit
bd73ed1cef
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@ -283,6 +283,8 @@
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#define RCC_CDCCIP1R_SPDIFSEL_VALUE(n) ((n) << RCC_CDCCIP1R_SPDIFSEL_Pos)
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#define RCC_CDCCIP1R_SPI45SEL_VALUE(n) ((n) << RCC_CDCCIP1R_SPI45SEL_Pos)
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#define RCC_CDCCIP1R_SPI123SEL_VALUE(n) ((n) << RCC_CDCCIP1R_SPI123SEL_Pos)
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#define RCC_CDCCIP1R_SAI2BSEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI2BSEL_Pos)
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#define RCC_CDCCIP1R_SAI2ASEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI2ASEL_Pos)
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#define RCC_CDCCIP1R_SAI1SEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI1SEL_Pos)
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#define RCC_CDCCIP2R_LPTIM1SEL_VALUE(n) ((n) << RCC_CDCCIP2R_LPTIM1SEL_Pos)
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@ -294,8 +296,6 @@
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#define RCC_CDCCIP2R_USART234578SEL_VALUE(n) ((n) << RCC_CDCCIP2R_USART234578SEL_Pos)
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#define RCC_SRDCCIPR_SPI6SEL_VALUE(n) ((n) << RCC_SRDCCIPR_SPI6SEL_Pos)
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#define RCC_CDCCIP1R_SAI2BSEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI2BSEL_Pos)
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#define RCC_CDCCIP1R_SAI2ASEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI2ASEL_Pos)
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#define RCC_SRDCCIPR_ADCSEL_VALUE(n) ((n) << RCC_SRDCCIPR_ADCSEL_Pos)
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#define RCC_SRDCCIPR_LPTIM3SEL_VALUE(n) ((n) << RCC_SRDCCIPR_LPTIM3SEL_Pos)
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#define RCC_SRDCCIPR_LPTIM2SEL_VALUE(n) ((n) << RCC_SRDCCIPR_LPTIM2SEL_Pos)
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@ -1051,13 +1051,6 @@
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#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
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#endif
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/**
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* @brief DFSDM2 clock source.
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*/
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#if !defined(STM32_DFSDM2SEL) || defined(__DOXYGEN__)
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#define STM32_DFSDM2SEL STM32_DFSDM2SEL_PCLK4
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#endif
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/**
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* @brief SPDIF clock source.
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*/
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@ -1080,10 +1073,17 @@
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#endif
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/**
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* @brief SAI2 clock source.
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* @brief SAI2BSEL clock source.
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*/
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#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
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#define STM32_SAI2SEL 0U /* Not present.*/
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#if !defined(STM32_SAI2BSEL) || defined(__DOXYGEN__)
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#define STM32_SAI2BSEL STM32_SAI2BSEL_PLL1_Q_CK
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#endif
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/**
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* @brief SAI2ASEL clock source.
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*/
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#if !defined(STM32_SAI2ASEL) || defined(__DOXYGEN__)
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#define STM32_SAI2ASEL STM32_SAI2ASEL_PLL1_Q_CK
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#endif
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/**
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@ -1150,17 +1150,10 @@
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#endif
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/**
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* @brief SAI2BSEL clock source.
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* @brief DFSDM2 clock source.
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*/
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#if !defined(STM32_SAI2BSEL) || defined(__DOXYGEN__)
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#define STM32_SAI2BSEL STM32_SAI2BSEL_PLL1_Q_CK
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#endif
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/**
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* @brief SAI2ASEL clock source.
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*/
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#if !defined(STM32_SAI2ASEL) || defined(__DOXYGEN__)
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#define STM32_SAI2ASEL STM32_SAI2ASEL_PLL1_Q_CK
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#if !defined(STM32_DFSDM2SEL) || defined(__DOXYGEN__)
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#define STM32_DFSDM2SEL STM32_DFSDM2SEL_PCLK4
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#endif
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/**
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@ -46,11 +46,6 @@
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#define STM32_HAS_M4 TRUE
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#endif
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/**
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* @name STM32H7xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* Common. */
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/*===========================================================================*/
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@ -346,15 +341,12 @@
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#define STM32_HAS_DCMI TRUE
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#endif /* defined(STM32H743xx) || defined(STM32H753xx) */
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/** @} */
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/*===========================================================================*/
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/* STM32H723xx, STM32H733xx, STM32H725xx, STM32H735xx. */
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/* STM32H723xx, STM32H733xx, STM32H725xx, STM32H735xx. */
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/*===========================================================================*/
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#if defined(STM32H723xx) || defined(STM32H733xx) || \
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defined(STM32H725xx) || defined(STM32H735xx) || \
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defined(STM32H7A3xx) || defined(STM32H7B3xx) || \
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defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || \
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defined(__DOXYGEN__)
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/* ADC attributes.*/
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@ -371,7 +363,7 @@
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/* CAN attributes.*/
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#define STM32_HAS_FDCAN1 TRUE
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#define STM32_HAS_FDCAN2 TRUE
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#define STM32_HAS_FDCAN3 TRUE
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#define STM32_HAS_FDCAN3 FALSE
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#define STM32_FDCAN_FLS_NBR 128U
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#define STM32_FDCAN_FLE_NBR 128U
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#define STM32_FDCAN_RF0_NBR 64U
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@ -585,7 +577,243 @@
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#endif /* defined(STM32H723xx) || defined(STM32H733xx) ||
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defined(STM32H725xx) || defined(STM32H735xx) */
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/** @} */
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/*===========================================================================*/
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/* STM32H7A3xx, STM32H7B3xx, STM32H7A3xxQ, STM32H7B3xxQ. */
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/*===========================================================================*/
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#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || \
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defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || \
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defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_ADC_RENAMED_REGS TRUE
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 FALSE /* NOT an error, it is a different ADC type.*/
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_HAS_SDADC3 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_FDCAN1 TRUE
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#define STM32_HAS_FDCAN2 TRUE
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#define STM32_HAS_FDCAN3 FALSE
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#define STM32_FDCAN_FLS_NBR 128U
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#define STM32_FDCAN_FLE_NBR 128U
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#define STM32_FDCAN_RF0_NBR 64U
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#define STM32_FDCAN_RF1_NBR 64U
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#define STM32_FDCAN_RB_NBR 64U
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#define STM32_FDCAN_TEF_NBR 32U
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#define STM32_FDCAN_TB_NBR 32U
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#define STM32_FDCAN_TM_NBR 64U
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* BDMA attributes.*/
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#define STM32_HAS_BDMA1 TRUE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX TRUE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 TRUE
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/* MDMA attributes.*/
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#define STM32_HAS_MDMA1 TRUE
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_ENHANCED
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#define STM32_EXTI_NUM_LINES 34
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#define STM32_EXTI_IMR1_MASK 0x1F800000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOI TRUE
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#define STM32_HAS_GPIOJ TRUE
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#define STM32_HAS_GPIOK TRUE
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#define STM32_GPIO_EN_MASK (RCC_AHB4ENR_GPIOAEN | \
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RCC_AHB4ENR_GPIOBEN | \
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RCC_AHB4ENR_GPIOCEN | \
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RCC_AHB4ENR_GPIODEN | \
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RCC_AHB4ENR_GPIOEEN | \
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RCC_AHB4ENR_GPIOFEN | \
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RCC_AHB4ENR_GPIOGEN | \
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RCC_AHB4ENR_GPIOHEN | \
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RCC_AHB4ENR_GPIOIEN | \
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RCC_AHB4ENR_GPIOJEN | \
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RCC_AHB4ENR_GPIOKEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_I2C3 TRUE
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#define STM32_HAS_I2C4 TRUE
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/* OCTOSPI attributes.*/
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#define STM32_HAS_OCTOSPI1 TRUE
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#define STM32_HAS_OCTOSPI2 TRUE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 FALSE
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#define STM32_HAS_QUADSPI2 FALSE
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 TRUE
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#define STM32_HAS_SDMMC2 TRUE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S TRUE
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#define STM32_SPI1_I2S_FULLDUPLEX TRUE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_SPI2_I2S_FULLDUPLEX TRUE
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S TRUE
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#define STM32_SPI3_I2S_FULLDUPLEX TRUE
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI5 TRUE
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#define STM32_SPI5_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI6 TRUE
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#define STM32_SPI6_SUPPORTS_I2S FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_HAS_TIM12 TRUE
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#define STM32_TIM12_IS_32BITS FALSE
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#define STM32_TIM12_CHANNELS 2
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#define STM32_HAS_TIM13 TRUE
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#define STM32_TIM13_IS_32BITS FALSE
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#define STM32_TIM13_CHANNELS 1
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 1
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 1
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART4 TRUE
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#define STM32_HAS_UART5 TRUE
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#define STM32_HAS_USART6 TRUE
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#define STM32_HAS_UART7 TRUE
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#define STM32_HAS_UART8 TRUE
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#define STM32_HAS_UART9 TRUE
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#define STM32_HAS_USART10 TRUE
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#define STM32_HAS_LPUART1 TRUE
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/* USB attributes.*/
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#define STM32_OTG_STEPPING 2
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 TRUE
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#define STM32_OTG2_ENDPOINTS 8
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#define STM32_HAS_USB FALSE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED TRUE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC TRUE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D TRUE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC TRUE
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#define STM32_FSMC_IS_FMC TRUE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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/* DCMI attributes.*/
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#define STM32_HAS_DCMI TRUE
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#endif /* defined(STM32H723xx) || defined(STM32H733xx) ||
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defined(STM32H725xx) || defined(STM32H735xx) */
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/*===========================================================================*/
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/* STM32H750xx. */
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