Starting EX improvements: improved L3GD20 driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9638 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi
parent
fd47b671f8
commit
beabb0d0ae
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@ -33,58 +33,7 @@
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/* Driver local definitions. */
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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#define L3GD20_SENS_250DPS ((float)0.00875f)
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#define PI 3.14159f
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#define L3GD20_SENS_500DPS ((float)0.01750f)
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#define L3GD20_SENS_2000DPS ((float)0.07000f)
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#define L3GD20_DI ((uint8_t)0xFF)
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#define L3GD20_DI_0 ((uint8_t)0x01)
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#define L3GD20_DI_1 ((uint8_t)0x02)
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#define L3GD20_DI_2 ((uint8_t)0x04)
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#define L3GD20_DI_3 ((uint8_t)0x08)
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#define L3GD20_DI_4 ((uint8_t)0x10)
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#define L3GD20_DI_5 ((uint8_t)0x20)
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#define L3GD20_DI_6 ((uint8_t)0x40)
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#define L3GD20_DI_7 ((uint8_t)0x80)
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#define L3GD20_AD ((uint8_t)0x3F)
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#define L3GD20_AD_0 ((uint8_t)0x01)
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#define L3GD20_AD_1 ((uint8_t)0x02)
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#define L3GD20_AD_2 ((uint8_t)0x04)
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#define L3GD20_AD_3 ((uint8_t)0x08)
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#define L3GD20_AD_4 ((uint8_t)0x10)
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#define L3GD20_AD_5 ((uint8_t)0x20)
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#define L3GD20_MS ((uint8_t)0x40)
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#define L3GD20_RW ((uint8_t)0x80)
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#define L3GD20_AD_WHO_AM_I ((uint8_t)0x0F)
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#define L3GD20_AD_CTRL_REG1 ((uint8_t)0x20)
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#define L3GD20_AD_CTRL_REG2 ((uint8_t)0x21)
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#define L3GD20_AD_CTRL_REG3 ((uint8_t)0x22)
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#define L3GD20_AD_CTRL_REG4 ((uint8_t)0x23)
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#define L3GD20_AD_CTRL_REG5 ((uint8_t)0x24)
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#define L3GD20_AD_REFERENCE ((uint8_t)0x25)
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#define L3GD20_AD_OUT_TEMP ((uint8_t)0x26)
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#define L3GD20_AD_STATUS_REG ((uint8_t)0x27)
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#define L3GD20_AD_OUT_X_L ((uint8_t)0x28)
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#define L3GD20_AD_OUT_X_H ((uint8_t)0x29)
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#define L3GD20_AD_OUT_Y_L ((uint8_t)0x2A)
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#define L3GD20_AD_OUT_Y_H ((uint8_t)0x2B)
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#define L3GD20_AD_OUT_Z_L ((uint8_t)0x2C)
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#define L3GD20_AD_OUT_Z_H ((uint8_t)0x2D)
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#define L3GD20_AD_FIFO_CTRL_REG ((uint8_t)0x2E)
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#define L3GD20_AD_FIFO_SRC_REG ((uint8_t)0x2F)
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#define L3GD20_AD_INT1_CFG ((uint8_t)0x30)
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#define L3GD20_AD_INT1_SRC ((uint8_t)0x31)
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#define L3GD20_AD_INT1_TSH_XH ((uint8_t)0x32)
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#define L3GD20_AD_INT1_TSH_XL ((uint8_t)0x33)
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#define L3GD20_AD_INT1_TSH_YH ((uint8_t)0x34)
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#define L3GD20_AD_INT1_TSH_YL ((uint8_t)0x35)
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#define L3GD20_AD_INT1_TSH_ZH ((uint8_t)0x36)
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#define L3GD20_AD_INT1_TSH_ZL ((uint8_t)0x37)
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#define L3GD20_AD_INT1_DURATION ((uint8_t)0x38)
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#define L3GD20_CTRL_REG4_FS_MASK ((uint8_t)0x30)
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/* Driver exported variables. */
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@ -94,14 +43,6 @@
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/* Driver local variables and types. */
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief L3GD20 Power Mode
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*/
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typedef enum {
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L3GD20_PM_POWER_DOWN = 0x00, /**< Power down enabled. */
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L3GD20_PM_SLEEP_NORMAL = 0x08 /**< Normal operation mode. */
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}l3gd20_pm_t;
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -112,16 +53,18 @@ typedef enum {
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* @pre The SPI interface must be initialized and the driver started.
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* @pre The SPI interface must be initialized and the driver started.
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*
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*
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* @param[in] spip pointer to the SPI interface
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* @param[in] spip pointer to the SPI interface
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* @param[in] reg register number
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* @param[in] reg starting register address
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* @return register value.
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* @param[in] n number of adjacent registers to write
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* @param[in] b pointer to a buffer.
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*/
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*/
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static uint8_t l3gd20SPIReadRegister(SPIDriver *spip, uint8_t reg) {
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static void l3gd20SPIReadRegister(SPIDriver *spip, uint8_t reg, size_t n,
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uint8_t txbuf[2] = {L3GD20_RW | reg, 0xFF};
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uint8_t* b) {
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uint8_t rxbuf[2] = {0x00, 0x00};
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uint8_t cmd;
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(n == 1) ? (cmd = reg) : (cmd = reg | L3GD20_RW | L3GD20_MS);
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spiSelect(spip);
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spiSelect(spip);
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spiExchange(spip, 2, txbuf, rxbuf);
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spiSend(spip, 1, &cmd);
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spiReceive(spip, n, b);
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spiUnselect(spip);
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spiUnselect(spip);
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return rxbuf[1];
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}
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}
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/**
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/**
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@ -129,51 +72,18 @@ static uint8_t l3gd20SPIReadRegister(SPIDriver *spip, uint8_t reg) {
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* @pre The SPI interface must be initialized and the driver started.
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* @pre The SPI interface must be initialized and the driver started.
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*
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*
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* @param[in] spip pointer to the SPI interface
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* @param[in] spip pointer to the SPI interface
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* @param[in] reg register number
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* @param[in] reg starting register address
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* @param[in] value register value.
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* @param[in] n number of adjacent registers to write
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* @param[in] value pointer to a buffer of values.
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*/
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*/
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static void l3gd20SPIWriteRegister(SPIDriver *spip, uint8_t reg,
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static void l3gd20SPIWriteRegister(SPIDriver *spip, uint8_t reg, size_t n,
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uint8_t value) {
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uint8_t* b) {
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uint8_t cmd;
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switch (reg) {
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(n == 1) ? (cmd = reg) : (cmd = reg | L3GD20_MS);
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default:
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spiSelect(spip);
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/* Reserved register must not be written, according to the datasheet
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spiSend(spip, 1, &cmd);
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* this could permanently damage the device.
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spiSend(spip, n, b);
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*/
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spiUnselect(spip);
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osalDbgAssert(FALSE, "l3gd20SPIWriteRegister(), reserved register");
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case L3GD20_AD_WHO_AM_I:
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case L3GD20_AD_OUT_TEMP :
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case L3GD20_AD_STATUS_REG:
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case L3GD20_AD_OUT_X_L:
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case L3GD20_AD_OUT_X_H:
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case L3GD20_AD_OUT_Y_L:
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case L3GD20_AD_OUT_Y_H:
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case L3GD20_AD_OUT_Z_L:
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case L3GD20_AD_OUT_Z_H:
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case L3GD20_AD_FIFO_SRC_REG:
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case L3GD20_AD_INT1_SRC:
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/* Read only registers cannot be written, the command is ignored.*/
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return;
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case L3GD20_AD_CTRL_REG1:
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case L3GD20_AD_CTRL_REG2:
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case L3GD20_AD_CTRL_REG3:
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case L3GD20_AD_CTRL_REG4:
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case L3GD20_AD_CTRL_REG5:
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case L3GD20_AD_REFERENCE:
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case L3GD20_AD_FIFO_CTRL_REG:
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case L3GD20_AD_INT1_CFG:
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case L3GD20_AD_INT1_TSH_XH:
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case L3GD20_AD_INT1_TSH_XL:
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case L3GD20_AD_INT1_TSH_YH:
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case L3GD20_AD_INT1_TSH_YL:
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case L3GD20_AD_INT1_TSH_ZH:
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case L3GD20_AD_INT1_TSH_ZL:
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case L3GD20_AD_INT1_DURATION:
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spiSelect(spip);
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uint8_t txbuf[2] = {reg, value};
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spiSend(spip, 2, txbuf);
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spiUnselect(spip);
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}
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}
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}
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#endif /* L3GD20_USE_SPI */
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#endif /* L3GD20_USE_SPI */
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@ -187,6 +97,7 @@ static size_t get_axes_number(void *ip) {
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}
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}
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static msg_t read_raw(void *ip, int32_t axes[L3GD20_NUMBER_OF_AXES]) {
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static msg_t read_raw(void *ip, int32_t axes[L3GD20_NUMBER_OF_AXES]) {
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uint8_t buff [L3GD20_NUMBER_OF_AXES * 2], i;
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int16_t tmp;
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int16_t tmp;
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osalDbgCheck((ip != NULL) && (axes != NULL));
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osalDbgCheck((ip != NULL) && (axes != NULL));
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@ -201,27 +112,12 @@ static msg_t read_raw(void *ip, int32_t axes[L3GD20_NUMBER_OF_AXES]) {
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spiStart(((L3GD20Driver *)ip)->config->spip,
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spiStart(((L3GD20Driver *)ip)->config->spip,
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((L3GD20Driver *)ip)->config->spicfg);
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((L3GD20Driver *)ip)->config->spicfg);
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#endif /* L3GD20_SHARED_SPI */
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#endif /* L3GD20_SHARED_SPI */
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if(((L3GD20Driver *)ip)->config->axesenabling & L3GD20_AE_X){
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l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip, L3GD20_AD_OUT_X_L,
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tmp = l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip,
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L3GD20_NUMBER_OF_AXES * 2, buff);
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L3GD20_AD_OUT_X_L);
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for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
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tmp += l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip,
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tmp = buff[2*i] + (buff[2*i+1] << 8);
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L3GD20_AD_OUT_X_H) << 8;
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axes[i] = (int32_t)tmp;
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axes[0] = (int32_t)tmp + ((L3GD20Driver *)ip)->bias[0];
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}
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}
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if(((L3GD20Driver *)ip)->config->axesenabling & L3GD20_AE_Y){
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tmp = l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip,
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L3GD20_AD_OUT_Y_L);
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tmp += l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip,
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L3GD20_AD_OUT_Y_H) << 8;
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axes[1] = (int32_t)tmp + ((L3GD20Driver *)ip)->bias[1];
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}
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if(((L3GD20Driver *)ip)->config->axesenabling & L3GD20_AE_Z){
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tmp = l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip,
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L3GD20_AD_OUT_Z_L);
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tmp += l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip,
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L3GD20_AD_OUT_Z_H) << 8;
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axes[2] = (int32_t)tmp + ((L3GD20Driver *)ip)->bias[2];
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}
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#if L3GD20_SHARED_SPI
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#if L3GD20_SHARED_SPI
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spiReleaseBus(((L3GD20Driver *)ip)->config->spip);
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spiReleaseBus(((L3GD20Driver *)ip)->config->spip);
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#endif /* L3GD20_SHARED_SPI */
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#endif /* L3GD20_SHARED_SPI */
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@ -241,7 +137,8 @@ static msg_t read_cooked(void *ip, float axes[]) {
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msg = read_raw(ip, raw);
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msg = read_raw(ip, raw);
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for(i = 0; i < L3GD20_NUMBER_OF_AXES ; i++){
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for(i = 0; i < L3GD20_NUMBER_OF_AXES ; i++){
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axes[i] = raw[i] * ((L3GD20Driver *)ip)->sensitivity[i];
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axes[i] = (raw[i] * ((L3GD20Driver *)ip)->sensitivity[i]);
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axes[i] -= ((L3GD20Driver *)ip)->bias[i];
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}
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}
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return msg;
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return msg;
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}
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}
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@ -265,7 +162,8 @@ static msg_t sample_bias(void *ip) {
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}
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}
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for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++){
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for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++){
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((L3GD20Driver *)ip)->bias[i] = buff[i] / L3GD20_BIAS_ACQ_TIMES;
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((L3GD20Driver *)ip)->bias[i] = (buff[i] / L3GD20_BIAS_ACQ_TIMES);
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((L3GD20Driver *)ip)->bias[i] *= ((L3GD20Driver *)ip)->sensitivity[i];
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}
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}
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return MSG_OK;
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return MSG_OK;
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}
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}
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@ -337,25 +235,70 @@ static msg_t reset_sensivity(void *ip) {
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return MSG_OK;
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return MSG_OK;
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}
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}
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static msg_t get_temperature(void *ip, float* tempp) {
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static msg_t set_full_scale(void *ip, l3gd20_fs_t fs) {
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float newfs, scale;
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unsigned i;
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#if L3GD20_USE_SPI
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if(fs == L3GD20_FS_250DPS) {
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osalDbgAssert((((L3GD20Driver *)ip)->config->spip->state == SPI_READY),
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newfs = L3GD20_250DPS;
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"read_raw(), channel not ready");
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}
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#if L3GD20_SHARED_SPI
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else if(fs == L3GD20_FS_500DPS) {
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spiAcquireBus(((L3GD20Driver *)ip)->config->spip);
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newfs = L3GD20_500DPS;
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spiStart(((L3GD20Driver *)ip)->config->spip,
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}
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((L3GD20Driver *)ip)->config->spicfg);
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else if(fs == L3GD20_FS_2000DPS) {
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#endif /* L3GD20_SHARED_SPI */
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newfs = L3GD20_2000DPS;
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*tempp = (int8_t)l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip,
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}
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L3GD20_AD_OUT_TEMP);
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else {
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#if L3GD20_SHARED_SPI
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return MSG_RESET;
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spiReleaseBus(((L3GD20Driver *)ip)->config->spip);
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}
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#endif /* L3GD20_SHARED_SPI */
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#endif /* L3GD20_USE_SPI */
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if(newfs != ((L3GD20Driver *)ip)->fullscale) {
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scale = newfs / ((L3GD20Driver *)ip)->fullscale;
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((L3GD20Driver *)ip)->fullscale = newfs;
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/* Scaling sensitivity and bias. Re-calibration is suggested anyway. */
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for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
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((L3GD20Driver *)ip)->sensitivity[i] *= scale;
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((L3GD20Driver *)ip)->bias[i] *= scale;
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}
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}
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return MSG_OK;
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return MSG_OK;
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}
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}
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static l3gd20_fs_t get_full_scale(void *ip) {
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if(((L3GD20Driver *)ip)->fullscale == L3GD20_250DPS) {
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return L3GD20_FS_250DPS;
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}
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else if(((L3GD20Driver *)ip)->fullscale == L3GD20_500DPS) {
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return L3GD20_FS_500DPS;
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}
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else {
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return L3GD20_FS_2000DPS;
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}
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}
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static msg_t set_meas_unit(void *ip, l3gd20_unit_t unit) {
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unsigned i;
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if(unit != ((L3GD20Driver *)ip)->meas_unit) {
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((L3GD20Driver *)ip)->meas_unit = unit;
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/* From RPS to DPS */
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if(unit == L3GD20_UNIT_DPS)
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for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
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((L3GD20Driver *)ip)->sensitivity[i] *= (2 * PI);
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/* From DPS to RPS */
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else if(unit == L3GD20_UNIT_RPS)
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for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
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((L3GD20Driver *)ip)->sensitivity[i] /= (2 * PI);
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else
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return MSG_RESET;
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}
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return MSG_OK;
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}
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||||||
|
static l3gd20_unit_t get_meas_unit(void *ip) {
|
||||||
|
|
||||||
|
return ((L3GD20Driver *)ip)->meas_unit;
|
||||||
|
}
|
||||||
|
|
||||||
static const struct BaseSensorVMT vmt_basesensor = {
|
static const struct BaseSensorVMT vmt_basesensor = {
|
||||||
get_axes_number, read_raw, read_cooked
|
get_axes_number, read_raw, read_cooked
|
||||||
};
|
};
|
||||||
|
|
@ -369,7 +312,9 @@ static const struct BaseGyroscopeVMT vmt_basegyroscope = {
|
||||||
static const struct L3GD20VMT vmt_l3gd20 = {
|
static const struct L3GD20VMT vmt_l3gd20 = {
|
||||||
get_axes_number, read_raw, read_cooked,
|
get_axes_number, read_raw, read_cooked,
|
||||||
sample_bias, set_bias, reset_bias,
|
sample_bias, set_bias, reset_bias,
|
||||||
set_sensivity, reset_sensivity, get_temperature
|
set_sensivity, reset_sensivity,
|
||||||
|
set_full_scale, get_full_scale,
|
||||||
|
set_meas_unit, get_meas_unit
|
||||||
};
|
};
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
@ -404,6 +349,7 @@ void l3gd20ObjectInit(L3GD20Driver *devp) {
|
||||||
*/
|
*/
|
||||||
void l3gd20Start(L3GD20Driver *devp, const L3GD20Config *config) {
|
void l3gd20Start(L3GD20Driver *devp, const L3GD20Config *config) {
|
||||||
uint32_t i;
|
uint32_t i;
|
||||||
|
uint8_t cr[5] = {0, 0, 0, 0, 0};
|
||||||
osalDbgCheck((devp != NULL) && (config != NULL));
|
osalDbgCheck((devp != NULL) && (config != NULL));
|
||||||
|
|
||||||
osalDbgAssert((devp->state == L3GD20_STOP) || (devp->state == L3GD20_READY),
|
osalDbgAssert((devp->state == L3GD20_STOP) || (devp->state == L3GD20_READY),
|
||||||
|
|
@ -417,29 +363,105 @@ void l3gd20Start(L3GD20Driver *devp, const L3GD20Config *config) {
|
||||||
#endif /* L3GD20_SHARED_SPI */
|
#endif /* L3GD20_SHARED_SPI */
|
||||||
spiStart((devp)->config->spip,
|
spiStart((devp)->config->spip,
|
||||||
(devp)->config->spicfg);
|
(devp)->config->spicfg);
|
||||||
|
|
||||||
|
/* Control register 1 configuration block */
|
||||||
|
{
|
||||||
|
cr[0] = L3GD20_CTRL_REG1_XEN | L3GD20_CTRL_REG1_YEN |
|
||||||
|
L3GD20_CTRL_REG1_ZEN | L3GD20_CTRL_REG1_PD |
|
||||||
|
devp->config->outputdatarate;
|
||||||
|
#if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
|
||||||
|
cr[0] |= devp->config->bandwidth;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Control register 2 configuration block */
|
||||||
|
{
|
||||||
|
#if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
|
||||||
|
if(devp->config->hpmode != L3GD20_HPM_BYPASSED)
|
||||||
|
cr[1] = devp->config->hpmode | devp->config->hpconfiguration;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Control register 3 configuration block */
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Control register 4 configuration block */
|
||||||
|
{
|
||||||
|
cr[3] = devp->config->fullscale;
|
||||||
|
#if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
|
||||||
|
cr[3] |= devp->config->blockdataupdate |
|
||||||
|
devp->config->endianness;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Control register 5 configuration block */
|
||||||
|
{
|
||||||
|
|
||||||
|
#if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
|
||||||
|
if((devp->config->hpmode != L3GD20_HPM_BYPASSED)) {
|
||||||
|
cr[4] = L3GD20_CTRL_REG5_HPEN;
|
||||||
|
if(devp->config->lp2mode != L3GD20_LP2M_BYPASSED) {
|
||||||
|
cr[4] |= L3GD20_CTRL_REG5_INT1_SEL1 |
|
||||||
|
L3GD20_CTRL_REG5_OUT_SEL1;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
cr[4] |= L3GD20_CTRL_REG5_INT1_SEL0 |
|
||||||
|
L3GD20_CTRL_REG5_OUT_SEL0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG1,
|
l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG1,
|
||||||
devp->config->axesenabling |
|
5, cr);
|
||||||
L3GD20_PM_SLEEP_NORMAL |
|
|
||||||
devp->config->outputdatarate);
|
|
||||||
l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG4,
|
|
||||||
devp->config->fullscale |
|
|
||||||
devp->config->blockdataupdate |
|
|
||||||
devp->config->endianness);
|
|
||||||
#if L3GD20_SHARED_SPI
|
#if L3GD20_SHARED_SPI
|
||||||
spiReleaseBus((devp)->config->spip);
|
spiReleaseBus((devp)->config->spip);
|
||||||
#endif /* L3GD20_SHARED_SPI */
|
#endif /* L3GD20_SHARED_SPI */
|
||||||
#endif /* L3GD20_USE_SPI */
|
#endif /* L3GD20_USE_SPI */
|
||||||
|
|
||||||
/* Storing sensitivity information according to full scale value */
|
/* Storing sensitivity information according to full scale and unit value */
|
||||||
if(devp->config->fullscale == L3GD20_FS_250DPS)
|
if(devp->config->fullscale == L3GD20_FS_250DPS) {
|
||||||
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
|
devp->fullscale = L3GD20_250DPS;
|
||||||
devp->sensitivity[i] = L3GD20_SENS_250DPS;
|
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
|
||||||
else if(devp->config->fullscale == L3GD20_FS_500DPS)
|
if(devp->meas_unit == L3GD20_UNIT_DPS) {
|
||||||
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
|
devp->sensitivity[i] = L3GD20_SENS_250DPS;
|
||||||
devp->sensitivity[i] = L3GD20_SENS_500DPS;
|
}
|
||||||
else if(devp->config->fullscale == L3GD20_FS_2000DPS)
|
else if (devp->meas_unit == L3GD20_UNIT_RPS) {
|
||||||
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
|
devp->sensitivity[i] = L3GD20_SENS_250DPS / (2 * PI);
|
||||||
devp->sensitivity[i] = L3GD20_SENS_2000DPS;
|
}
|
||||||
|
else {
|
||||||
|
devp->sensitivity[i] = 1.0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if(devp->config->fullscale == L3GD20_FS_500DPS) {
|
||||||
|
devp->fullscale = L3GD20_500DPS;
|
||||||
|
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
|
||||||
|
if(devp->meas_unit == L3GD20_UNIT_DPS) {
|
||||||
|
devp->sensitivity[i] = L3GD20_SENS_500DPS;
|
||||||
|
}
|
||||||
|
else if (devp->meas_unit == L3GD20_UNIT_RPS) {
|
||||||
|
devp->sensitivity[i] = L3GD20_SENS_500DPS / (2 * PI);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
devp->sensitivity[i] = 1.0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if(devp->config->fullscale == L3GD20_FS_2000DPS) {
|
||||||
|
devp->fullscale = L3GD20_2000DPS;
|
||||||
|
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
|
||||||
|
if(devp->meas_unit == L3GD20_UNIT_DPS) {
|
||||||
|
devp->sensitivity[i] = L3GD20_SENS_500DPS;
|
||||||
|
}
|
||||||
|
else if (devp->meas_unit == L3GD20_UNIT_RPS) {
|
||||||
|
devp->sensitivity[i] = L3GD20_SENS_500DPS / (2 * PI);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
devp->sensitivity[i] = 1.0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
else
|
else
|
||||||
osalDbgAssert(FALSE, "l3gd20Start(), full scale issue");
|
osalDbgAssert(FALSE, "l3gd20Start(), full scale issue");
|
||||||
/* This is the Gyroscope transient recovery time */
|
/* This is the Gyroscope transient recovery time */
|
||||||
|
|
@ -456,7 +478,7 @@ void l3gd20Start(L3GD20Driver *devp, const L3GD20Config *config) {
|
||||||
* @api
|
* @api
|
||||||
*/
|
*/
|
||||||
void l3gd20Stop(L3GD20Driver *devp) {
|
void l3gd20Stop(L3GD20Driver *devp) {
|
||||||
|
uint8_t cr1;
|
||||||
osalDbgCheck(devp != NULL);
|
osalDbgCheck(devp != NULL);
|
||||||
|
|
||||||
osalDbgAssert((devp->state == L3GD20_STOP) || (devp->state == L3GD20_READY),
|
osalDbgAssert((devp->state == L3GD20_STOP) || (devp->state == L3GD20_READY),
|
||||||
|
|
@ -469,8 +491,10 @@ void l3gd20Stop(L3GD20Driver *devp) {
|
||||||
spiStart((devp)->config->spip,
|
spiStart((devp)->config->spip,
|
||||||
(devp)->config->spicfg);
|
(devp)->config->spicfg);
|
||||||
#endif /* L3GD20_SHARED_SPI */
|
#endif /* L3GD20_SHARED_SPI */
|
||||||
|
/* Disabling all axes and enabling power down mode */
|
||||||
|
cr1 = 0;
|
||||||
l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG1,
|
l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG1,
|
||||||
L3GD20_PM_POWER_DOWN | L3GD20_AE_DISABLED);
|
1, &cr1);
|
||||||
spiStop((devp)->config->spip);
|
spiStop((devp)->config->spip);
|
||||||
#if L3GD20_SHARED_SPI
|
#if L3GD20_SHARED_SPI
|
||||||
spiReleaseBus((devp)->config->spip);
|
spiReleaseBus((devp)->config->spip);
|
||||||
|
|
|
||||||
|
|
@ -35,9 +35,132 @@
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 number of axes.
|
* @brief L3GD20 characteristics
|
||||||
*/
|
*/
|
||||||
#define L3GD20_NUMBER_OF_AXES ((size_t) 3U)
|
#define L3GD20_NUMBER_OF_AXES 3U
|
||||||
|
|
||||||
|
#define L3GD20_250DPS 250.0f
|
||||||
|
#define L3GD20_500DPS 500.0f
|
||||||
|
#define L3GD20_2000DPS 2000.0f
|
||||||
|
|
||||||
|
#define L3GD20_SENS_250DPS 0.00875f
|
||||||
|
#define L3GD20_SENS_500DPS 0.01750f
|
||||||
|
#define L3GD20_SENS_2000DPS 0.07000f
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name L3GD20 communication interfaces related bit masks
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define L3GD20_DI_MASK 0xFF /**< Data In mask */
|
||||||
|
#define L3GD20_DI(n) (1 << n) /**< Data In bit n */
|
||||||
|
#define L3GD20_AD_MASK 0x3F /**< Address Data mask */
|
||||||
|
#define L3GD20_AD(n) (1 << n) /**< Address Data bit n */
|
||||||
|
#define L3GD20_MS (1 << 6) /**< Multiple read write */
|
||||||
|
#define L3GD20_RW (1 << 7) /**< Read Write selector */
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name L3GD20 register addresses
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define L3GD20_AD_WHO_AM_I 0x0F
|
||||||
|
#define L3GD20_AD_CTRL_REG1 0x20
|
||||||
|
#define L3GD20_AD_CTRL_REG2 0x21
|
||||||
|
#define L3GD20_AD_CTRL_REG3 0x22
|
||||||
|
#define L3GD20_AD_CTRL_REG4 0x23
|
||||||
|
#define L3GD20_AD_CTRL_REG5 0x24
|
||||||
|
#define L3GD20_AD_REFERENCE 0x25
|
||||||
|
#define L3GD20_AD_OUT_TEMP 0x26
|
||||||
|
#define L3GD20_AD_STATUS_REG 0x27
|
||||||
|
#define L3GD20_AD_OUT_X_L 0x28
|
||||||
|
#define L3GD20_AD_OUT_X_H 0x29
|
||||||
|
#define L3GD20_AD_OUT_Y_L 0x2A
|
||||||
|
#define L3GD20_AD_OUT_Y_H 0x2B
|
||||||
|
#define L3GD20_AD_OUT_Z_L 0x2C
|
||||||
|
#define L3GD20_AD_OUT_Z_H 0x2D
|
||||||
|
#define L3GD20_AD_FIFO_CTRL_REG 0x2E
|
||||||
|
#define L3GD20_AD_FIFO_SRC_REG 0x2F
|
||||||
|
#define L3GD20_AD_INT1_CFG 0x30
|
||||||
|
#define L3GD20_AD_INT1_SRC 0x31
|
||||||
|
#define L3GD20_AD_INT1_TSH_XH 0x32
|
||||||
|
#define L3GD20_AD_INT1_TSH_XL 0x33
|
||||||
|
#define L3GD20_AD_INT1_TSH_YH 0x34
|
||||||
|
#define L3GD20_AD_INT1_TSH_YL 0x35
|
||||||
|
#define L3GD20_AD_INT1_TSH_ZH 0x36
|
||||||
|
#define L3GD20_AD_INT1_TSH_ZL 0x37
|
||||||
|
#define L3GD20_AD_INT1_DURATION 0x38
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name L3GD20_CTRL_REG1 register bits definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define L3GD20_CTRL_REG1_MASK 0xFF /**< L3GD20_CTRL_REG1 mask */
|
||||||
|
#define L3GD20_CTRL_REG1_XEN (1 << 0) /**< X axis enable */
|
||||||
|
#define L3GD20_CTRL_REG1_YEN (1 << 1) /**< Y axis enable */
|
||||||
|
#define L3GD20_CTRL_REG1_ZEN (1 << 2) /**< Z axis enable */
|
||||||
|
#define L3GD20_CTRL_REG1_PD (1 << 3) /**< Power-down mode enable */
|
||||||
|
#define L3GD20_CTRL_REG1_BW0 (1 << 4) /**< Bandwidth bit 0 */
|
||||||
|
#define L3GD20_CTRL_REG1_BW1 (1 << 5) /**< Bandwidth bit 1 */
|
||||||
|
#define L3GD20_CTRL_REG1_DR0 (1 << 6) /**< Output data rate bit 0 */
|
||||||
|
#define L3GD20_CTRL_REG1_DR1 (1 << 7) /**< Output data rate bit 1 */
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name L3GD20_CTRL_REG2 register bits definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define L3GD20_CTRL_REG2_MASK 0x3F /**< L3GD20_CTRL_REG2 mask */
|
||||||
|
#define L3GD20_CTRL_REG2_HPCF0 (1 << 0) /**< HP filter cutoff bit 0 */
|
||||||
|
#define L3GD20_CTRL_REG2_HPCF1 (1 << 1) /**< HP filter cutoff bit 1 */
|
||||||
|
#define L3GD20_CTRL_REG2_HPCF2 (1 << 2) /**< HP filter cutoff bit 2 */
|
||||||
|
#define L3GD20_CTRL_REG2_HPCF3 (1 << 3) /**< HP filter cutoff bit 3 */
|
||||||
|
#define L3GD20_CTRL_REG2_HPM0 (1 << 4) /**< HP filter mode bit 0 */
|
||||||
|
#define L3GD20_CTRL_REG2_HPM1 (1 << 5) /**< HP filter mode bit 1 */
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name L3GD20_CTRL_REG3 register bits definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define L3GD20_CTRL_REG3_MASK 0xFF /**< L3GD20_CTRL_REG3 mask */
|
||||||
|
#define L3GD20_CTRL_REG3_I2_EMPTY (1 << 0) /**< FIFO empty IRQ */
|
||||||
|
#define L3GD20_CTRL_REG3_I2_ORUN (1 << 1) /**< FIFO overrun IRQ */
|
||||||
|
#define L3GD20_CTRL_REG3_I2_WTM (1 << 2) /**< FIFO watermark IRQ */
|
||||||
|
#define L3GD20_CTRL_REG3_I2_DRDY (1 << 3) /**< Data ready */
|
||||||
|
#define L3GD20_CTRL_REG3_PP_OD (1 << 4) /**< Push-pull / Open Drain */
|
||||||
|
#define L3GD20_CTRL_REG3_H_LACTIVE (1 << 5) /**< IRQ active */
|
||||||
|
#define L3GD20_CTRL_REG3_I1_BOOT (1 << 6) /**< Boot status available */
|
||||||
|
#define L3GD20_CTRL_REG3_I1_INT1 (1 << 7) /**< IRQ enable */
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name L3GD20_CTRL_REG4 register bits definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define L3GD20_CTRL_REG4_MASK 0xF1 /**< L3GD20_CTRL_REG4 mask */
|
||||||
|
#define L3GD20_CTRL_REG4_SIM (1 << 0) /**< SPI mode */
|
||||||
|
#define L3GD20_CTRL_REG4_FS_MASK (3 << 4) /**< Full scale mask */
|
||||||
|
#define L3GD20_CTRL_REG4_FS0 (1 << 4) /**< Full scale bit 0 */
|
||||||
|
#define L3GD20_CTRL_REG4_FS1 (1 << 5) /**< Full scale bit 1 */
|
||||||
|
#define L3GD20_CTRL_REG4_BLE (1 << 6) /**< Big/little endian data */
|
||||||
|
#define L3GD20_CTRL_REG4_BDU (1 << 7) /**< Block data update */
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name L3GD20_CTRL_REG5 register bits definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define L3GD20_CTRL_REG5_MASK 0xDF /**< L3GD20_CTRL_REG5 mask */
|
||||||
|
#define L3GD20_CTRL_REG5_OUT_SEL0 (1 << 0) /**< Out selection bit 0 */
|
||||||
|
#define L3GD20_CTRL_REG5_OUT_SEL1 (1 << 1) /**< Out selection bit 1 */
|
||||||
|
#define L3GD20_CTRL_REG5_INT1_SEL0 (1 << 2) /**< INT1 selection bit 0 */
|
||||||
|
#define L3GD20_CTRL_REG5_INT1_SEL1 (1 << 3) /**< INT1 selection bit 1 */
|
||||||
|
#define L3GD20_CTRL_REG5_HPEN (1 << 4) /**< HP filter enable */
|
||||||
|
#define L3GD20_CTRL_REG5_FIFO_EN (1 << 6) /**< FIFO enable */
|
||||||
|
#define L3GD20_CTRL_REG5_BOOT (1 << 7) /**< Reboot memory content */
|
||||||
|
/** @} */
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver pre-compile time settings. */
|
/* Driver pre-compile time settings. */
|
||||||
|
|
@ -65,6 +188,15 @@
|
||||||
#define L3GD20_USE_I2C FALSE
|
#define L3GD20_USE_I2C FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 advanced configurations switch.
|
||||||
|
* @details If set to @p TRUE more configurations are available.
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#if !defined(L3GD20_USE_ADVANCED) || defined(__DOXYGEN__)
|
||||||
|
#define L3GD20_USE_ADVANCED FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 shared SPI switch.
|
* @brief L3GD20 shared SPI switch.
|
||||||
* @details If set to @p TRUE the device acquires SPI bus ownership
|
* @details If set to @p TRUE the device acquires SPI bus ownership
|
||||||
|
|
@ -118,11 +250,11 @@
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @name L3GD20 data structures and types
|
* @name L3GD20 data structures and types.
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 full scale
|
* @brief L3GD20 full scale.
|
||||||
*/
|
*/
|
||||||
typedef enum {
|
typedef enum {
|
||||||
L3GD20_FS_250DPS = 0x00, /**< Full scale 250 degree per second. */
|
L3GD20_FS_250DPS = 0x00, /**< Full scale 250 degree per second. */
|
||||||
|
|
@ -131,41 +263,26 @@ typedef enum {
|
||||||
}l3gd20_fs_t;
|
}l3gd20_fs_t;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 output data rate and bandwidth
|
* @brief L3GD20 output data rate and bandwidth.
|
||||||
*/
|
*/
|
||||||
typedef enum {
|
typedef enum {
|
||||||
L3GD20_ODR_95HZ_FC_12_5 = 0x00, /**< ODR 95 Hz, BW 12.5 Hz. */
|
L3GD20_ODR_95HZ = 0x00, /**< Output data rate 95 Hz. */
|
||||||
L3GD20_ODR_95HZ_FC_25 = 0x10, /**< ODR 95 Hz, BW 25Hz. */
|
L3GD20_ODR_190HZ = 0x40, /**< Output data rate 190 Hz. */
|
||||||
L3GD20_ODR_190HZ_FC_12_5 = 0x40, /**< ODR 190 Hz, BW 12.5 Hz. */
|
L3GD20_ODR_380HZ = 0x80, /**< Output data rate 380 Hz. */
|
||||||
L3GD20_ODR_190HZ_FC_25 = 0x50, /**< ODR 190 Hz, BW 25 Hz. */
|
L3GD20_ODR_760HZ = 0xC0 /**< Output data rate 760 Hz. */
|
||||||
L3GD20_ODR_190HZ_FC_50 = 0x60, /**< ODR 190 Hz, BW 50 Hz. */
|
|
||||||
L3GD20_ODR_190HZ_FC_70 = 0x70, /**< ODR 190 Hz, BW 70 Hz. */
|
|
||||||
L3GD20_ODR_380HZ_FC_20 = 0x80, /**< ODR 380 Hz, BW 20 Hz. */
|
|
||||||
L3GD20_ODR_380HZ_FC_25 = 0x90, /**< ODR 380 Hz, BW 25 Hz. */
|
|
||||||
L3GD20_ODR_380HZ_FC_50 = 0xA0, /**< ODR 380 Hz, BW 50 Hz. */
|
|
||||||
L3GD20_ODR_380HZ_FC_100 = 0xB0, /**< ODR 380 Hz, BW 100 Hz. */
|
|
||||||
L3GD20_ODR_760HZ_FC_30 = 0xC0, /**< ODR 760 Hz, BW 30 Hz. */
|
|
||||||
L3GD20_ODR_760HZ_FC_35 = 0xD0, /**< ODR 760 Hz, BW 35 Hz. */
|
|
||||||
L3GD20_ODR_760HZ_FC_50 = 0xE0, /**< ODR 760 Hz, BW 50 Hz. */
|
|
||||||
L3GD20_ODR_760HZ_FC_100 = 0xF0 /**< ODR 760 Hz, BW 100 Hz. */
|
|
||||||
}l3gd20_odr_t;
|
}l3gd20_odr_t;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 axes enabling
|
* @brief L3GD20 low pass filter 1 bandwidth.
|
||||||
*/
|
*/
|
||||||
typedef enum {
|
typedef enum {
|
||||||
L3GD20_AE_DISABLED = 0x00, /**< All axes disabled. */
|
L3GD20_BW0 = 0x00, /**< LPF1 bandwidth. Depends on ODR. */
|
||||||
L3GD20_AE_X = 0x01, /**< Only X-axis enabled. */
|
L3GD20_BW1 = 0x40, /**< LPF1 bandwidth. Depends on ODR. */
|
||||||
L3GD20_AE_Y = 0x02, /**< Only Y-axis enabled. */
|
L3GD20_BW2 = 0x80, /**< LPF1 bandwidth. Depends on ODR. */
|
||||||
L3GD20_AE_XY = 0x03, /**< X and Y axes enabled. */
|
L3GD20_BW3 = 0xC0 /**< LPF1 bandwidth. Depends on ODR. */
|
||||||
L3GD20_AE_Z = 0x04, /**< Only Z-axis enabled. */
|
}l3gd20_bw_t;
|
||||||
L3GD20_AE_XZ = 0x05, /**< X and Z axes enabled. */
|
|
||||||
L3GD20_AE_YZ = 0x06, /**< Y and Z axes enabled. */
|
|
||||||
L3GD20_AE_XYZ = 0x07 /**< All axes enabled. */
|
|
||||||
}l3gd20_ae_t;
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 block data update
|
* @brief L3GD20 block data update.
|
||||||
*/
|
*/
|
||||||
typedef enum {
|
typedef enum {
|
||||||
L3GD20_BDU_CONTINUOUS = 0x00, /**< Block data continuously updated. */
|
L3GD20_BDU_CONTINUOUS = 0x00, /**< Block data continuously updated. */
|
||||||
|
|
@ -173,13 +290,56 @@ typedef enum {
|
||||||
}l3gd20_bdu_t;
|
}l3gd20_bdu_t;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 endianness
|
* @brief L3GD20 HP filter mode.
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
L3GD20_HPM_NORMAL = 0x00, /**< Normal mode. */
|
||||||
|
L3GD20_HPM_REFERENCE = 0x10, /**< Reference signal for filtering. */
|
||||||
|
L3GD20_HPM_AUTORESET = 0x30, /**< Autoreset on interrupt event. */
|
||||||
|
L3GD20_HPM_BYPASSED = 0xFF /**< HP filter bypassed */
|
||||||
|
}l3gd20_hpm_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 HP configuration.
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
L3GD20_HPCF_0 = 0x00, /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
L3GD20_HPCF_1 = 0x01, /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
L3GD20_HPCF_2 = 0x02, /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
L3GD20_HPCF_3 = 0x03, /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
L3GD20_HPCF_4 = 0x04, /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
L3GD20_HPCF_5 = 0x05, /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
L3GD20_HPCF_6 = 0x06, /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
L3GD20_HPCF_7 = 0x07, /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
L3GD20_HPCF_8 = 0x08, /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
L3GD20_HPCF_9 = 0x09 /**< Depends on ODR (Table 26 for more).*/
|
||||||
|
}l3gd20_hpcf_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 LP2 filter mode.
|
||||||
|
* @detail To activate LP2 HP should be active
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
L3GD20_LP2M_ON = 0x00, /**< LP2 filter activated. */
|
||||||
|
L3GD20_LP2M_BYPASSED = 0xFF, /**< LP2 filter bypassed. */
|
||||||
|
}l3gd20_lp2m_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 endianness.
|
||||||
*/
|
*/
|
||||||
typedef enum {
|
typedef enum {
|
||||||
L3GD20_END_LITTLE = 0x00, /**< Little endian. */
|
L3GD20_END_LITTLE = 0x00, /**< Little endian. */
|
||||||
L3GD20_END_BIG = 0x40 /**< Big endian. */
|
L3GD20_END_BIG = 0x40 /**< Big endian. */
|
||||||
}l3gd20_end_t;
|
}l3gd20_end_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 measurement unit.
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
L3GD20_UNIT_DPS = 0x00, /**< Cooked data in degrees per seconds.*/
|
||||||
|
L3GD20_UNIT_RPS = 0x01, /**< Cooked data in radians per seconds.*/
|
||||||
|
} l3gd20_unit_t;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Driver state machine possible states.
|
* @brief Driver state machine possible states.
|
||||||
*/
|
*/
|
||||||
|
|
@ -194,7 +354,7 @@ typedef enum {
|
||||||
*/
|
*/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
|
|
||||||
#if (L3GD20_USE_SPI) || defined(__DOXYGEN__)
|
#if L3GD20_USE_SPI || defined(__DOXYGEN__)
|
||||||
/**
|
/**
|
||||||
* @brief SPI driver associated to this L3GD20.
|
* @brief SPI driver associated to this L3GD20.
|
||||||
*/
|
*/
|
||||||
|
|
@ -204,7 +364,7 @@ typedef struct {
|
||||||
*/
|
*/
|
||||||
const SPIConfig *spicfg;
|
const SPIConfig *spicfg;
|
||||||
#endif /* L3GD20_USE_SPI */
|
#endif /* L3GD20_USE_SPI */
|
||||||
#if (L3GD20_USE_I2C) || defined(__DOXYGEN__)
|
#if L3GD20_USE_I2C || defined(__DOXYGEN__)
|
||||||
/**
|
/**
|
||||||
* @brief I2C driver associated to this L3GD20.
|
* @brief I2C driver associated to this L3GD20.
|
||||||
*/
|
*/
|
||||||
|
|
@ -215,17 +375,22 @@ typedef struct {
|
||||||
const I2CConfig *i2ccfg;
|
const I2CConfig *i2ccfg;
|
||||||
#endif /* L3GD20_USE_I2C */
|
#endif /* L3GD20_USE_I2C */
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 full scale value.
|
* @brief L3GD20 initial sensitivity.
|
||||||
|
*/
|
||||||
|
float sensitivity[L3GD20_NUMBER_OF_AXES];
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 initial bias.
|
||||||
|
*/
|
||||||
|
float bias[L3GD20_NUMBER_OF_AXES];
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 initial full scale value.
|
||||||
*/
|
*/
|
||||||
l3gd20_fs_t fullscale;
|
l3gd20_fs_t fullscale;
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 output data rate selection.
|
* @brief L3GD20 output data rate selection.
|
||||||
*/
|
*/
|
||||||
l3gd20_odr_t outputdatarate;
|
l3gd20_odr_t outputdatarate;
|
||||||
/**
|
#if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
|
||||||
* @brief L3GD20 axes enabling.
|
|
||||||
*/
|
|
||||||
l3gd20_ae_t axesenabling;
|
|
||||||
/**
|
/**
|
||||||
* @brief L3GD20 block data update.
|
* @brief L3GD20 block data update.
|
||||||
*/
|
*/
|
||||||
|
|
@ -234,6 +399,28 @@ typedef struct {
|
||||||
* @brief L3GD20 endianness.
|
* @brief L3GD20 endianness.
|
||||||
*/
|
*/
|
||||||
l3gd20_end_t endianness;
|
l3gd20_end_t endianness;
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 LP1 filter bandwidth.
|
||||||
|
*/
|
||||||
|
l3gd20_bw_t bandwidth;
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 HP filter mode.
|
||||||
|
*/
|
||||||
|
l3gd20_hpm_t hpmode;
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 HP configuration.
|
||||||
|
*/
|
||||||
|
l3gd20_hpcf_t hpconfiguration;
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 LP2 filter mode.
|
||||||
|
* @detail To activate LP2 HP should be active
|
||||||
|
*/
|
||||||
|
l3gd20_lp2m_t lp2mode;
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @brief L3GD20 initial measurement unit.
|
||||||
|
*/
|
||||||
|
l3gd20_unit_t unit;
|
||||||
} L3GD20Config;
|
} L3GD20Config;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -246,9 +433,14 @@ typedef struct L3GD20Driver L3GD20Driver;
|
||||||
*/
|
*/
|
||||||
#define _l3gd20_methods \
|
#define _l3gd20_methods \
|
||||||
_base_gyroscope_methods \
|
_base_gyroscope_methods \
|
||||||
/* Retrieve the temperature of L3GD20 chip.*/ \
|
/* Change full scale value of L3GD20 .*/ \
|
||||||
msg_t (*get_temperature)(void *instance, float* temperature);
|
msg_t (*set_full_scale)(void *instance, l3gd20_fs_t fs); \
|
||||||
|
/* Get full scale value of L3GD20 .*/ \
|
||||||
|
l3gd20_fs_t (*get_full_scale)(void *instance); \
|
||||||
|
/* Change measurement unit of L3GD20 .*/ \
|
||||||
|
msg_t (*set_meas_unit)(void *instance, l3gd20_unit_t unit); \
|
||||||
|
/* Get measurement unit of L3GD20 .*/ \
|
||||||
|
l3gd20_unit_t (*get_meas_unit)(void *instance);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @extends BaseGyroscopeVMT
|
* @extends BaseGyroscopeVMT
|
||||||
|
|
@ -268,10 +460,14 @@ struct L3GD20VMT {
|
||||||
l3gd20_state_t state; \
|
l3gd20_state_t state; \
|
||||||
/* Current configuration data.*/ \
|
/* Current configuration data.*/ \
|
||||||
const L3GD20Config *config; \
|
const L3GD20Config *config; \
|
||||||
/* Current sensitivity.*/ \
|
/* Current sensitivity data.*/ \
|
||||||
float sensitivity[L3GD20_NUMBER_OF_AXES]; \
|
float sensitivity[L3GD20_NUMBER_OF_AXES]; \
|
||||||
/* Bias data.*/ \
|
/* Current Bias data.*/ \
|
||||||
int32_t bias[L3GD20_NUMBER_OF_AXES];
|
float bias[L3GD20_NUMBER_OF_AXES]; \
|
||||||
|
/* Current full scale value.*/ \
|
||||||
|
float fullscale; \
|
||||||
|
/* Measurement unit.*/ \
|
||||||
|
l3gd20_unit_t meas_unit;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @extends BaseGyroscope
|
* @extends BaseGyroscope
|
||||||
|
|
@ -296,19 +492,32 @@ struct L3GD20Driver {
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Get current MEMS temperature.
|
* @brief Change initial fullscale value.
|
||||||
* @detail This information is very useful especially for high accuracy IMU
|
|
||||||
*
|
*
|
||||||
* @param[in] ip pointer to a @p BaseGyroscope class.
|
* @param[in] ip pointer to a @p BaseGyroscope class.
|
||||||
* @param[out] temp the MEMS temperature as single precision floating.
|
* @param[in] fs the new full scale value.
|
||||||
*
|
*
|
||||||
* @return The operation status.
|
* @return The operation status.
|
||||||
* @retval MSG_OK if the function succeeded.
|
* @retval MSG_OK if the function succeeded.
|
||||||
* @retval MSG_RESET if one or more errors occurred.
|
* @retval MSG_RESET if one or more errors occurred.
|
||||||
* @api
|
* @api
|
||||||
*/
|
*/
|
||||||
#define gyroscopeGetTemp(ip, tpp) \
|
#define gyroscopeSetFullScale(ip, fs) \
|
||||||
(ip)->vmt_l3gd20->get_temperature(ip, tpp)
|
(ip)->vmt_l3gd20->set_full_scale(ip, fs)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set gyroscope cooked data measurement unit.
|
||||||
|
*
|
||||||
|
* @param[in] ip pointer to a @p BaseGyroscope class.
|
||||||
|
* @param[in] unit the MEMS measurement unit.
|
||||||
|
*
|
||||||
|
* @return The operation status.
|
||||||
|
* @retval MSG_OK if the function succeeded.
|
||||||
|
* @retval MSG_RESET if one or more errors occurred.
|
||||||
|
* @api
|
||||||
|
*/
|
||||||
|
#define gyroscopeSetMeasurementUnit(ip, unit) \
|
||||||
|
(ip)->vmt_l3gd20->set_meas_unit(ip, unit)
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* External declarations. */
|
/* External declarations. */
|
||||||
|
|
|
||||||
|
|
@ -139,7 +139,7 @@
|
||||||
* @brief Enables the SERIAL subsystem.
|
* @brief Enables the SERIAL subsystem.
|
||||||
*/
|
*/
|
||||||
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
||||||
#define HAL_USE_SERIAL TRUE
|
#define HAL_USE_SERIAL FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
||||||
|
|
@ -192,7 +192,7 @@
|
||||||
/*
|
/*
|
||||||
* SERIAL driver system settings.
|
* SERIAL driver system settings.
|
||||||
*/
|
*/
|
||||||
#define STM32_SERIAL_USE_USART1 TRUE
|
#define STM32_SERIAL_USE_USART1 FALSE
|
||||||
#define STM32_SERIAL_USE_USART2 FALSE
|
#define STM32_SERIAL_USE_USART2 FALSE
|
||||||
#define STM32_SERIAL_USE_USART3 FALSE
|
#define STM32_SERIAL_USE_USART3 FALSE
|
||||||
#define STM32_SERIAL_USE_UART4 FALSE
|
#define STM32_SERIAL_USE_UART4 FALSE
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue