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Starting EX improvements: improved L3GD20 driver. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9638 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2016-06-17 11:32:10 +00:00
parent fd47b671f8
commit beabb0d0ae
4 changed files with 960 additions and 727 deletions
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888
os/ex/ST/l3gd20.c
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@ -33,58 +33,7 @@
/* Driver local definitions. */ /* Driver local definitions. */
/*===========================================================================*/ /*===========================================================================*/
#define L3GD20_SENS_250DPS ((float)0.00875f) #define PI 3.14159f
#define L3GD20_SENS_500DPS ((float)0.01750f)
#define L3GD20_SENS_2000DPS ((float)0.07000f)
#define L3GD20_DI ((uint8_t)0xFF)
#define L3GD20_DI_0 ((uint8_t)0x01)
#define L3GD20_DI_1 ((uint8_t)0x02)
#define L3GD20_DI_2 ((uint8_t)0x04)
#define L3GD20_DI_3 ((uint8_t)0x08)
#define L3GD20_DI_4 ((uint8_t)0x10)
#define L3GD20_DI_5 ((uint8_t)0x20)
#define L3GD20_DI_6 ((uint8_t)0x40)
#define L3GD20_DI_7 ((uint8_t)0x80)
#define L3GD20_AD ((uint8_t)0x3F)
#define L3GD20_AD_0 ((uint8_t)0x01)
#define L3GD20_AD_1 ((uint8_t)0x02)
#define L3GD20_AD_2 ((uint8_t)0x04)
#define L3GD20_AD_3 ((uint8_t)0x08)
#define L3GD20_AD_4 ((uint8_t)0x10)
#define L3GD20_AD_5 ((uint8_t)0x20)
#define L3GD20_MS ((uint8_t)0x40)
#define L3GD20_RW ((uint8_t)0x80)
#define L3GD20_AD_WHO_AM_I ((uint8_t)0x0F)
#define L3GD20_AD_CTRL_REG1 ((uint8_t)0x20)
#define L3GD20_AD_CTRL_REG2 ((uint8_t)0x21)
#define L3GD20_AD_CTRL_REG3 ((uint8_t)0x22)
#define L3GD20_AD_CTRL_REG4 ((uint8_t)0x23)
#define L3GD20_AD_CTRL_REG5 ((uint8_t)0x24)
#define L3GD20_AD_REFERENCE ((uint8_t)0x25)
#define L3GD20_AD_OUT_TEMP ((uint8_t)0x26)
#define L3GD20_AD_STATUS_REG ((uint8_t)0x27)
#define L3GD20_AD_OUT_X_L ((uint8_t)0x28)
#define L3GD20_AD_OUT_X_H ((uint8_t)0x29)
#define L3GD20_AD_OUT_Y_L ((uint8_t)0x2A)
#define L3GD20_AD_OUT_Y_H ((uint8_t)0x2B)
#define L3GD20_AD_OUT_Z_L ((uint8_t)0x2C)
#define L3GD20_AD_OUT_Z_H ((uint8_t)0x2D)
#define L3GD20_AD_FIFO_CTRL_REG ((uint8_t)0x2E)
#define L3GD20_AD_FIFO_SRC_REG ((uint8_t)0x2F)
#define L3GD20_AD_INT1_CFG ((uint8_t)0x30)
#define L3GD20_AD_INT1_SRC ((uint8_t)0x31)
#define L3GD20_AD_INT1_TSH_XH ((uint8_t)0x32)
#define L3GD20_AD_INT1_TSH_XL ((uint8_t)0x33)
#define L3GD20_AD_INT1_TSH_YH ((uint8_t)0x34)
#define L3GD20_AD_INT1_TSH_YL ((uint8_t)0x35)
#define L3GD20_AD_INT1_TSH_ZH ((uint8_t)0x36)
#define L3GD20_AD_INT1_TSH_ZL ((uint8_t)0x37)
#define L3GD20_AD_INT1_DURATION ((uint8_t)0x38)
#define L3GD20_CTRL_REG4_FS_MASK ((uint8_t)0x30)
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
@ -94,389 +43,464 @@
/* Driver local variables and types. */ /* Driver local variables and types. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief L3GD20 Power Mode
*/
typedef enum {
L3GD20_PM_POWER_DOWN = 0x00, /**< Power down enabled. */
L3GD20_PM_SLEEP_NORMAL = 0x08 /**< Normal operation mode. */
}l3gd20_pm_t;
/*===========================================================================*/ /*===========================================================================*/
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
#if (L3GD20_USE_SPI) || defined(__DOXYGEN__) #if (L3GD20_USE_SPI) || defined(__DOXYGEN__)
/** /**
* @brief Reads a generic register value using SPI. * @brief Reads a generic register value using SPI.
* @pre The SPI interface must be initialized and the driver started. * @pre The SPI interface must be initialized and the driver started.
* *
* @param[in] spip pointer to the SPI interface * @param[in] spip pointer to the SPI interface
* @param[in] reg register number * @param[in] reg starting register address
* @return register value. * @param[in] n number of adjacent registers to write
*/ * @param[in] b pointer to a buffer.
static uint8_t l3gd20SPIReadRegister(SPIDriver *spip, uint8_t reg) { */
uint8_t txbuf[2] = {L3GD20_RW | reg, 0xFF}; static void l3gd20SPIReadRegister(SPIDriver *spip, uint8_t reg, size_t n,
uint8_t rxbuf[2] = {0x00, 0x00}; uint8_t* b) {
spiSelect(spip); uint8_t cmd;
spiExchange(spip, 2, txbuf, rxbuf); (n == 1) ? (cmd = reg) : (cmd = reg | L3GD20_RW | L3GD20_MS);
spiUnselect(spip); spiSelect(spip);
return rxbuf[1]; spiSend(spip, 1, &cmd);
} spiReceive(spip, n, b);
spiUnselect(spip);
/** }
* @brief Writes a value into a generic register using SPI.
* @pre The SPI interface must be initialized and the driver started. /**
* * @brief Writes a value into a generic register using SPI.
* @param[in] spip pointer to the SPI interface * @pre The SPI interface must be initialized and the driver started.
* @param[in] reg register number *
* @param[in] value register value. * @param[in] spip pointer to the SPI interface
*/ * @param[in] reg starting register address
static void l3gd20SPIWriteRegister(SPIDriver *spip, uint8_t reg, * @param[in] n number of adjacent registers to write
uint8_t value) { * @param[in] value pointer to a buffer of values.
*/
switch (reg) { static void l3gd20SPIWriteRegister(SPIDriver *spip, uint8_t reg, size_t n,
default: uint8_t* b) {
/* Reserved register must not be written, according to the datasheet uint8_t cmd;
* this could permanently damage the device. (n == 1) ? (cmd = reg) : (cmd = reg | L3GD20_MS);
*/ spiSelect(spip);
osalDbgAssert(FALSE, "l3gd20SPIWriteRegister(), reserved register"); spiSend(spip, 1, &cmd);
case L3GD20_AD_WHO_AM_I: spiSend(spip, n, b);
case L3GD20_AD_OUT_TEMP : spiUnselect(spip);
case L3GD20_AD_STATUS_REG: }
case L3GD20_AD_OUT_X_L: #endif /* L3GD20_USE_SPI */
case L3GD20_AD_OUT_X_H:
case L3GD20_AD_OUT_Y_L: /*
case L3GD20_AD_OUT_Y_H: * Interface implementation.
case L3GD20_AD_OUT_Z_L: */
case L3GD20_AD_OUT_Z_H: static size_t get_axes_number(void *ip) {
case L3GD20_AD_FIFO_SRC_REG:
case L3GD20_AD_INT1_SRC: osalDbgCheck(ip != NULL);
/* Read only registers cannot be written, the command is ignored.*/ return L3GD20_NUMBER_OF_AXES;
return; }
case L3GD20_AD_CTRL_REG1:
case L3GD20_AD_CTRL_REG2: static msg_t read_raw(void *ip, int32_t axes[L3GD20_NUMBER_OF_AXES]) {
case L3GD20_AD_CTRL_REG3: uint8_t buff [L3GD20_NUMBER_OF_AXES * 2], i;
case L3GD20_AD_CTRL_REG4: int16_t tmp;
case L3GD20_AD_CTRL_REG5: osalDbgCheck((ip != NULL) && (axes != NULL));
case L3GD20_AD_REFERENCE:
case L3GD20_AD_FIFO_CTRL_REG: osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY),
case L3GD20_AD_INT1_CFG: "read_raw(), invalid state");
case L3GD20_AD_INT1_TSH_XH:
case L3GD20_AD_INT1_TSH_XL: #if L3GD20_USE_SPI
case L3GD20_AD_INT1_TSH_YH: osalDbgAssert((((L3GD20Driver *)ip)->config->spip->state == SPI_READY),
case L3GD20_AD_INT1_TSH_YL: "read_raw(), channel not ready");
case L3GD20_AD_INT1_TSH_ZH: #if L3GD20_SHARED_SPI
case L3GD20_AD_INT1_TSH_ZL: spiAcquireBus(((L3GD20Driver *)ip)->config->spip);
case L3GD20_AD_INT1_DURATION: spiStart(((L3GD20Driver *)ip)->config->spip,
spiSelect(spip); ((L3GD20Driver *)ip)->config->spicfg);
uint8_t txbuf[2] = {reg, value}; #endif /* L3GD20_SHARED_SPI */
spiSend(spip, 2, txbuf); l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip, L3GD20_AD_OUT_X_L,
spiUnselect(spip); L3GD20_NUMBER_OF_AXES * 2, buff);
} for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
} tmp = buff[2*i] + (buff[2*i+1] << 8);
#endif /* L3GD20_USE_SPI */ axes[i] = (int32_t)tmp;
}
/* #if L3GD20_SHARED_SPI
* Interface implementation. spiReleaseBus(((L3GD20Driver *)ip)->config->spip);
*/ #endif /* L3GD20_SHARED_SPI */
static size_t get_axes_number(void *ip) { #endif /* L3GD20_USE_SPI */
return MSG_OK;
osalDbgCheck(ip != NULL); }
return L3GD20_NUMBER_OF_AXES;
} static msg_t read_cooked(void *ip, float axes[]) {
uint32_t i;
static msg_t read_raw(void *ip, int32_t axes[L3GD20_NUMBER_OF_AXES]) { int32_t raw[L3GD20_NUMBER_OF_AXES];
int16_t tmp; msg_t msg;
osalDbgCheck((ip != NULL) && (axes != NULL));
osalDbgCheck((ip != NULL) && (axes != NULL));
osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY),
"read_raw(), invalid state"); osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY),
"read_cooked(), invalid state");
#if L3GD20_USE_SPI
osalDbgAssert((((L3GD20Driver *)ip)->config->spip->state == SPI_READY), msg = read_raw(ip, raw);
"read_raw(), channel not ready"); for(i = 0; i < L3GD20_NUMBER_OF_AXES ; i++){
#if L3GD20_SHARED_SPI axes[i] = (raw[i] * ((L3GD20Driver *)ip)->sensitivity[i]);
spiAcquireBus(((L3GD20Driver *)ip)->config->spip); axes[i] -= ((L3GD20Driver *)ip)->bias[i];
spiStart(((L3GD20Driver *)ip)->config->spip, }
((L3GD20Driver *)ip)->config->spicfg); return msg;
#endif /* L3GD20_SHARED_SPI */ }
if(((L3GD20Driver *)ip)->config->axesenabling & L3GD20_AE_X){
tmp = l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip, static msg_t sample_bias(void *ip) {
L3GD20_AD_OUT_X_L); uint32_t i, j;
tmp += l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip, int32_t raw[L3GD20_NUMBER_OF_AXES];
L3GD20_AD_OUT_X_H) << 8; int32_t buff[L3GD20_NUMBER_OF_AXES] = {0, 0, 0};
axes[0] = (int32_t)tmp + ((L3GD20Driver *)ip)->bias[0];
} osalDbgCheck(ip != NULL);
if(((L3GD20Driver *)ip)->config->axesenabling & L3GD20_AE_Y){
tmp = l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip, osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY),
L3GD20_AD_OUT_Y_L); "sample_bias(), invalid state");
tmp += l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip,
L3GD20_AD_OUT_Y_H) << 8; for(i = 0; i < L3GD20_BIAS_ACQ_TIMES; i++){
axes[1] = (int32_t)tmp + ((L3GD20Driver *)ip)->bias[1]; read_raw(ip, raw);
} for(j = 0; j < L3GD20_NUMBER_OF_AXES; j++){
if(((L3GD20Driver *)ip)->config->axesenabling & L3GD20_AE_Z){ buff[j] += raw[j];
tmp = l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip, }
L3GD20_AD_OUT_Z_L); osalThreadSleepMicroseconds(L3GD20_BIAS_SETTLING_uS);
tmp += l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip, }
L3GD20_AD_OUT_Z_H) << 8;
axes[2] = (int32_t)tmp + ((L3GD20Driver *)ip)->bias[2]; for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++){
} ((L3GD20Driver *)ip)->bias[i] = (buff[i] / L3GD20_BIAS_ACQ_TIMES);
#if L3GD20_SHARED_SPI ((L3GD20Driver *)ip)->bias[i] *= ((L3GD20Driver *)ip)->sensitivity[i];
spiReleaseBus(((L3GD20Driver *)ip)->config->spip); }
#endif /* L3GD20_SHARED_SPI */ return MSG_OK;
#endif /* L3GD20_USE_SPI */ }
return MSG_OK;
} static msg_t set_bias(void *ip, int32_t *bp) {
uint32_t i;
static msg_t read_cooked(void *ip, float axes[]) {
uint32_t i; osalDbgCheck((ip != NULL) && (bp !=NULL));
int32_t raw[L3GD20_NUMBER_OF_AXES];
msg_t msg; osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY) ||
(((L3GD20Driver *)ip)->state == L3GD20_STOP),
osalDbgCheck((ip != NULL) && (axes != NULL)); "set_bias(), invalid state");
osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY), for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
"read_cooked(), invalid state"); ((L3GD20Driver *)ip)->bias[i] = bp[i];
}
msg = read_raw(ip, raw); return MSG_OK;
for(i = 0; i < L3GD20_NUMBER_OF_AXES ; i++){ }
axes[i] = raw[i] * ((L3GD20Driver *)ip)->sensitivity[i];
} static msg_t reset_bias(void *ip) {
return msg; uint32_t i;
}
osalDbgCheck(ip != NULL);
static msg_t sample_bias(void *ip) {
uint32_t i, j; osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY) ||
int32_t raw[L3GD20_NUMBER_OF_AXES]; (((L3GD20Driver *)ip)->state == L3GD20_STOP),
int32_t buff[L3GD20_NUMBER_OF_AXES] = {0, 0, 0}; "reset_bias(), invalid state");
osalDbgCheck(ip != NULL); for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
((L3GD20Driver *)ip)->bias[i] = 0;
osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY), return MSG_OK;
"sample_bias(), invalid state"); }
for(i = 0; i < L3GD20_BIAS_ACQ_TIMES; i++){ static msg_t set_sensivity(void *ip, float *sp) {
read_raw(ip, raw); uint32_t i;
for(j = 0; j < L3GD20_NUMBER_OF_AXES; j++){
buff[j] += raw[j]; osalDbgCheck((ip != NULL) && (sp !=NULL));
}
osalThreadSleepMicroseconds(L3GD20_BIAS_SETTLING_uS); osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY),
} "set_sensivity(), invalid state");
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++){ for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
((L3GD20Driver *)ip)->bias[i] = buff[i] / L3GD20_BIAS_ACQ_TIMES; ((L3GD20Driver *)ip)->sensitivity[i] = sp[i];
} }
return MSG_OK; return MSG_OK;
} }
static msg_t set_bias(void *ip, int32_t *bp) { static msg_t reset_sensivity(void *ip) {
uint32_t i; uint32_t i;
osalDbgCheck((ip != NULL) && (bp !=NULL)); osalDbgCheck(ip != NULL);
osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY) || osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY),
(((L3GD20Driver *)ip)->state == L3GD20_STOP), "reset_sensivity(), invalid state");
"set_bias(), invalid state");
if(((L3GD20Driver *)ip)->config->fullscale == L3GD20_FS_250DPS)
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) { for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
((L3GD20Driver *)ip)->bias[i] = bp[i]; ((L3GD20Driver *)ip)->sensitivity[i] = L3GD20_SENS_250DPS;
} else if(((L3GD20Driver *)ip)->config->fullscale == L3GD20_FS_500DPS)
return MSG_OK; for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
} ((L3GD20Driver *)ip)->sensitivity[i] = L3GD20_SENS_500DPS;
else if(((L3GD20Driver *)ip)->config->fullscale == L3GD20_FS_2000DPS)
static msg_t reset_bias(void *ip) { for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
uint32_t i; ((L3GD20Driver *)ip)->sensitivity[i] = L3GD20_SENS_2000DPS;
else {
osalDbgCheck(ip != NULL); osalDbgAssert(FALSE, "reset_sensivity(), full scale issue");
return MSG_RESET;
osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY) || }
(((L3GD20Driver *)ip)->state == L3GD20_STOP), return MSG_OK;
"reset_bias(), invalid state"); }
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) static msg_t set_full_scale(void *ip, l3gd20_fs_t fs) {
((L3GD20Driver *)ip)->bias[i] = 0; float newfs, scale;
return MSG_OK; unsigned i;
}
if(fs == L3GD20_FS_250DPS) {
static msg_t set_sensivity(void *ip, float *sp) { newfs = L3GD20_250DPS;
uint32_t i; }
else if(fs == L3GD20_FS_500DPS) {
osalDbgCheck((ip != NULL) && (sp !=NULL)); newfs = L3GD20_500DPS;
}
osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY), else if(fs == L3GD20_FS_2000DPS) {
"set_sensivity(), invalid state"); newfs = L3GD20_2000DPS;
}
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) { else {
((L3GD20Driver *)ip)->sensitivity[i] = sp[i]; return MSG_RESET;
} }
return MSG_OK;
} if(newfs != ((L3GD20Driver *)ip)->fullscale) {
scale = newfs / ((L3GD20Driver *)ip)->fullscale;
static msg_t reset_sensivity(void *ip) { ((L3GD20Driver *)ip)->fullscale = newfs;
uint32_t i; /* Scaling sensitivity and bias. Re-calibration is suggested anyway. */
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
osalDbgCheck(ip != NULL); ((L3GD20Driver *)ip)->sensitivity[i] *= scale;
((L3GD20Driver *)ip)->bias[i] *= scale;
osalDbgAssert((((L3GD20Driver *)ip)->state == L3GD20_READY), }
"reset_sensivity(), invalid state"); }
return MSG_OK;
if(((L3GD20Driver *)ip)->config->fullscale == L3GD20_FS_250DPS) }
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
((L3GD20Driver *)ip)->sensitivity[i] = L3GD20_SENS_250DPS; static l3gd20_fs_t get_full_scale(void *ip) {
else if(((L3GD20Driver *)ip)->config->fullscale == L3GD20_FS_500DPS) if(((L3GD20Driver *)ip)->fullscale == L3GD20_250DPS) {
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) return L3GD20_FS_250DPS;
((L3GD20Driver *)ip)->sensitivity[i] = L3GD20_SENS_500DPS; }
else if(((L3GD20Driver *)ip)->config->fullscale == L3GD20_FS_2000DPS) else if(((L3GD20Driver *)ip)->fullscale == L3GD20_500DPS) {
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) return L3GD20_FS_500DPS;
((L3GD20Driver *)ip)->sensitivity[i] = L3GD20_SENS_2000DPS; }
else { else {
osalDbgAssert(FALSE, "reset_sensivity(), full scale issue"); return L3GD20_FS_2000DPS;
return MSG_RESET; }
} }
return MSG_OK;
} static msg_t set_meas_unit(void *ip, l3gd20_unit_t unit) {
unsigned i;
static msg_t get_temperature(void *ip, float* tempp) { if(unit != ((L3GD20Driver *)ip)->meas_unit) {
((L3GD20Driver *)ip)->meas_unit = unit;
#if L3GD20_USE_SPI /* From RPS to DPS */
osalDbgAssert((((L3GD20Driver *)ip)->config->spip->state == SPI_READY), if(unit == L3GD20_UNIT_DPS)
"read_raw(), channel not ready"); for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
#if L3GD20_SHARED_SPI ((L3GD20Driver *)ip)->sensitivity[i] *= (2 * PI);
spiAcquireBus(((L3GD20Driver *)ip)->config->spip); /* From DPS to RPS */
spiStart(((L3GD20Driver *)ip)->config->spip, else if(unit == L3GD20_UNIT_RPS)
((L3GD20Driver *)ip)->config->spicfg); for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
#endif /* L3GD20_SHARED_SPI */ ((L3GD20Driver *)ip)->sensitivity[i] /= (2 * PI);
*tempp = (int8_t)l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip, else
L3GD20_AD_OUT_TEMP); return MSG_RESET;
#if L3GD20_SHARED_SPI }
spiReleaseBus(((L3GD20Driver *)ip)->config->spip); return MSG_OK;
#endif /* L3GD20_SHARED_SPI */ }
#endif /* L3GD20_USE_SPI */
return MSG_OK; static l3gd20_unit_t get_meas_unit(void *ip) {
}
return ((L3GD20Driver *)ip)->meas_unit;
static const struct BaseSensorVMT vmt_basesensor = { }
get_axes_number, read_raw, read_cooked
}; static const struct BaseSensorVMT vmt_basesensor = {
get_axes_number, read_raw, read_cooked
static const struct BaseGyroscopeVMT vmt_basegyroscope = { };
get_axes_number, read_raw, read_cooked,
sample_bias, set_bias, reset_bias, static const struct BaseGyroscopeVMT vmt_basegyroscope = {
set_sensivity, reset_sensivity get_axes_number, read_raw, read_cooked,
}; sample_bias, set_bias, reset_bias,
set_sensivity, reset_sensivity
static const struct L3GD20VMT vmt_l3gd20 = { };
get_axes_number, read_raw, read_cooked,
sample_bias, set_bias, reset_bias, static const struct L3GD20VMT vmt_l3gd20 = {
set_sensivity, reset_sensivity, get_temperature get_axes_number, read_raw, read_cooked,
}; sample_bias, set_bias, reset_bias,
set_sensivity, reset_sensivity,
/*===========================================================================*/ set_full_scale, get_full_scale,
/* Driver exported functions. */ set_meas_unit, get_meas_unit
/*===========================================================================*/ };
/** /*===========================================================================*/
* @brief Initializes an instance. /* Driver exported functions. */
* /*===========================================================================*/
* @param[out] devp pointer to the @p L3GD20Driver object
* /**
* @init * @brief Initializes an instance.
*/ *
void l3gd20ObjectInit(L3GD20Driver *devp) { * @param[out] devp pointer to the @p L3GD20Driver object
uint32_t i; *
devp->vmt_basesensor = &vmt_basesensor; * @init
devp->vmt_basegyroscope = &vmt_basegyroscope; */
devp->vmt_l3gd20 = &vmt_l3gd20; void l3gd20ObjectInit(L3GD20Driver *devp) {
devp->config = NULL; uint32_t i;
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) devp->vmt_basesensor = &vmt_basesensor;
devp->bias[i] = 0; devp->vmt_basegyroscope = &vmt_basegyroscope;
devp->state = L3GD20_STOP; devp->vmt_l3gd20 = &vmt_l3gd20;
} devp->config = NULL;
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
/** devp->bias[i] = 0;
* @brief Configures and activates L3GD20 Complex Driver peripheral. devp->state = L3GD20_STOP;
* }
* @param[in] devp pointer to the @p L3GD20Driver object
* @param[in] config pointer to the @p L3GD20Config object /**
* * @brief Configures and activates L3GD20 Complex Driver peripheral.
* @api *
*/ * @param[in] devp pointer to the @p L3GD20Driver object
void l3gd20Start(L3GD20Driver *devp, const L3GD20Config *config) { * @param[in] config pointer to the @p L3GD20Config object
uint32_t i; *
osalDbgCheck((devp != NULL) && (config != NULL)); * @api
*/
osalDbgAssert((devp->state == L3GD20_STOP) || (devp->state == L3GD20_READY), void l3gd20Start(L3GD20Driver *devp, const L3GD20Config *config) {
"l3gd20Start(), invalid state"); uint32_t i;
uint8_t cr[5] = {0, 0, 0, 0, 0};
devp->config = config; osalDbgCheck((devp != NULL) && (config != NULL));
#if L3GD20_USE_SPI osalDbgAssert((devp->state == L3GD20_STOP) || (devp->state == L3GD20_READY),
#if L3GD20_SHARED_SPI "l3gd20Start(), invalid state");
spiAcquireBus((devp)->config->spip);
#endif /* L3GD20_SHARED_SPI */ devp->config = config;
spiStart((devp)->config->spip,
(devp)->config->spicfg); #if L3GD20_USE_SPI
l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG1, #if L3GD20_SHARED_SPI
devp->config->axesenabling | spiAcquireBus((devp)->config->spip);
L3GD20_PM_SLEEP_NORMAL | #endif /* L3GD20_SHARED_SPI */
devp->config->outputdatarate); spiStart((devp)->config->spip,
l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG4, (devp)->config->spicfg);
devp->config->fullscale |
devp->config->blockdataupdate | /* Control register 1 configuration block */
devp->config->endianness); {
#if L3GD20_SHARED_SPI cr[0] = L3GD20_CTRL_REG1_XEN | L3GD20_CTRL_REG1_YEN |
spiReleaseBus((devp)->config->spip); L3GD20_CTRL_REG1_ZEN | L3GD20_CTRL_REG1_PD |
#endif /* L3GD20_SHARED_SPI */ devp->config->outputdatarate;
#endif /* L3GD20_USE_SPI */ #if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
cr[0] |= devp->config->bandwidth;
/* Storing sensitivity information according to full scale value */ #endif
if(devp->config->fullscale == L3GD20_FS_250DPS) }
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++)
devp->sensitivity[i] = L3GD20_SENS_250DPS; /* Control register 2 configuration block */
else if(devp->config->fullscale == L3GD20_FS_500DPS) {
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) #if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
devp->sensitivity[i] = L3GD20_SENS_500DPS; if(devp->config->hpmode != L3GD20_HPM_BYPASSED)
else if(devp->config->fullscale == L3GD20_FS_2000DPS) cr[1] = devp->config->hpmode | devp->config->hpconfiguration;
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) #endif
devp->sensitivity[i] = L3GD20_SENS_2000DPS; }
else
osalDbgAssert(FALSE, "l3gd20Start(), full scale issue"); /* Control register 3 configuration block */
/* This is the Gyroscope transient recovery time */ {
osalThreadSleepMilliseconds(10); }
devp->state = L3GD20_READY; /* Control register 4 configuration block */
} {
cr[3] = devp->config->fullscale;
/** #if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
* @brief Deactivates the L3GD20 Complex Driver peripheral. cr[3] |= devp->config->blockdataupdate |
* devp->config->endianness;
* @param[in] devp pointer to the @p L3GD20Driver object #endif
* }
* @api
*/ /* Control register 5 configuration block */
void l3gd20Stop(L3GD20Driver *devp) { {
osalDbgCheck(devp != NULL); #if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
if((devp->config->hpmode != L3GD20_HPM_BYPASSED)) {
osalDbgAssert((devp->state == L3GD20_STOP) || (devp->state == L3GD20_READY), cr[4] = L3GD20_CTRL_REG5_HPEN;
"l3gd20Stop(), invalid state"); if(devp->config->lp2mode != L3GD20_LP2M_BYPASSED) {
cr[4] |= L3GD20_CTRL_REG5_INT1_SEL1 |
#if (L3GD20_USE_SPI) L3GD20_CTRL_REG5_OUT_SEL1;
if (devp->state == L3GD20_STOP) { }
#if L3GD20_SHARED_SPI else {
spiAcquireBus((devp)->config->spip); cr[4] |= L3GD20_CTRL_REG5_INT1_SEL0 |
spiStart((devp)->config->spip, L3GD20_CTRL_REG5_OUT_SEL0;
(devp)->config->spicfg); }
#endif /* L3GD20_SHARED_SPI */ }
l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG1, #endif
L3GD20_PM_POWER_DOWN | L3GD20_AE_DISABLED); }
spiStop((devp)->config->spip); l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG1,
#if L3GD20_SHARED_SPI 5, cr);
spiReleaseBus((devp)->config->spip); #if L3GD20_SHARED_SPI
#endif /* L3GD20_SHARED_SPI */ spiReleaseBus((devp)->config->spip);
} #endif /* L3GD20_SHARED_SPI */
#endif /* L3GD20_USE_SPI */ #endif /* L3GD20_USE_SPI */
devp->state = L3GD20_STOP;
} /* Storing sensitivity information according to full scale and unit value */
/** @} */ if(devp->config->fullscale == L3GD20_FS_250DPS) {
devp->fullscale = L3GD20_250DPS;
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
if(devp->meas_unit == L3GD20_UNIT_DPS) {
devp->sensitivity[i] = L3GD20_SENS_250DPS;
}
else if (devp->meas_unit == L3GD20_UNIT_RPS) {
devp->sensitivity[i] = L3GD20_SENS_250DPS / (2 * PI);
}
else {
devp->sensitivity[i] = 1.0;
}
}
}
else if(devp->config->fullscale == L3GD20_FS_500DPS) {
devp->fullscale = L3GD20_500DPS;
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
if(devp->meas_unit == L3GD20_UNIT_DPS) {
devp->sensitivity[i] = L3GD20_SENS_500DPS;
}
else if (devp->meas_unit == L3GD20_UNIT_RPS) {
devp->sensitivity[i] = L3GD20_SENS_500DPS / (2 * PI);
}
else {
devp->sensitivity[i] = 1.0;
}
}
}
else if(devp->config->fullscale == L3GD20_FS_2000DPS) {
devp->fullscale = L3GD20_2000DPS;
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
if(devp->meas_unit == L3GD20_UNIT_DPS) {
devp->sensitivity[i] = L3GD20_SENS_500DPS;
}
else if (devp->meas_unit == L3GD20_UNIT_RPS) {
devp->sensitivity[i] = L3GD20_SENS_500DPS / (2 * PI);
}
else {
devp->sensitivity[i] = 1.0;
}
}
}
else
osalDbgAssert(FALSE, "l3gd20Start(), full scale issue");
/* This is the Gyroscope transient recovery time */
osalThreadSleepMilliseconds(10);
devp->state = L3GD20_READY;
}
/**
* @brief Deactivates the L3GD20 Complex Driver peripheral.
*
* @param[in] devp pointer to the @p L3GD20Driver object
*
* @api
*/
void l3gd20Stop(L3GD20Driver *devp) {
uint8_t cr1;
osalDbgCheck(devp != NULL);
osalDbgAssert((devp->state == L3GD20_STOP) || (devp->state == L3GD20_READY),
"l3gd20Stop(), invalid state");
#if (L3GD20_USE_SPI)
if (devp->state == L3GD20_STOP) {
#if L3GD20_SHARED_SPI
spiAcquireBus((devp)->config->spip);
spiStart((devp)->config->spip,
(devp)->config->spicfg);
#endif /* L3GD20_SHARED_SPI */
/* Disabling all axes and enabling power down mode */
cr1 = 0;
l3gd20SPIWriteRegister(devp->config->spip, L3GD20_AD_CTRL_REG1,
1, &cr1);
spiStop((devp)->config->spip);
#if L3GD20_SHARED_SPI
spiReleaseBus((devp)->config->spip);
#endif /* L3GD20_SHARED_SPI */
}
#endif /* L3GD20_USE_SPI */
devp->state = L3GD20_STOP;
}
/** @} */

795
os/ex/ST/l3gd20.h
View File

@ -35,296 +35,505 @@
/*===========================================================================*/ /*===========================================================================*/
/** /**
* @brief L3GD20 number of axes. * @brief L3GD20 characteristics
*/ */
#define L3GD20_NUMBER_OF_AXES ((size_t) 3U) #define L3GD20_NUMBER_OF_AXES 3U
/*===========================================================================*/ #define L3GD20_250DPS 250.0f
/* Driver pre-compile time settings. */ #define L3GD20_500DPS 500.0f
/*===========================================================================*/ #define L3GD20_2000DPS 2000.0f
/** #define L3GD20_SENS_250DPS 0.00875f
* @name Configuration options #define L3GD20_SENS_500DPS 0.01750f
* @{ #define L3GD20_SENS_2000DPS 0.07000f
*/ /** @} */
/**
* @brief L3GD20 SPI interface switch. /**
* @details If set to @p TRUE the support for SPI is included. * @name L3GD20 communication interfaces related bit masks
* @note The default is @p TRUE. * @{
*/ */
#if !defined(L3GD20_USE_SPI) || defined(__DOXYGEN__) #define L3GD20_DI_MASK 0xFF /**< Data In mask */
#define L3GD20_USE_SPI TRUE #define L3GD20_DI(n) (1 << n) /**< Data In bit n */
#endif #define L3GD20_AD_MASK 0x3F /**< Address Data mask */
#define L3GD20_AD(n) (1 << n) /**< Address Data bit n */
/** #define L3GD20_MS (1 << 6) /**< Multiple read write */
* @brief L3GD20 I2C interface switch. #define L3GD20_RW (1 << 7) /**< Read Write selector */
* @details If set to @p TRUE the support for I2C is included. /** @} */
* @note The default is @p FALSE.
*/ /**
#if !defined(L3GD20_USE_I2C) || defined(__DOXYGEN__) * @name L3GD20 register addresses
#define L3GD20_USE_I2C FALSE * @{
#endif */
#define L3GD20_AD_WHO_AM_I 0x0F
/** #define L3GD20_AD_CTRL_REG1 0x20
* @brief L3GD20 shared SPI switch. #define L3GD20_AD_CTRL_REG2 0x21
* @details If set to @p TRUE the device acquires SPI bus ownership #define L3GD20_AD_CTRL_REG3 0x22
* on each transaction. #define L3GD20_AD_CTRL_REG4 0x23
* @note The default is @p FALSE. Requires SPI_USE_MUTUAL_EXCLUSION #define L3GD20_AD_CTRL_REG5 0x24
*/ #define L3GD20_AD_REFERENCE 0x25
#if !defined(L3GD20_SHARED_SPI) || defined(__DOXYGEN__) #define L3GD20_AD_OUT_TEMP 0x26
#define L3GD20_SHARED_SPI FALSE #define L3GD20_AD_STATUS_REG 0x27
#endif #define L3GD20_AD_OUT_X_L 0x28
#define L3GD20_AD_OUT_X_H 0x29
/** #define L3GD20_AD_OUT_Y_L 0x2A
* @brief Number of acquisitions for bias removal #define L3GD20_AD_OUT_Y_H 0x2B
* @details This is the number of acquisitions performed to compute the #define L3GD20_AD_OUT_Z_L 0x2C
* bias. A repetition is required in order to remove noise. #define L3GD20_AD_OUT_Z_H 0x2D
*/ #define L3GD20_AD_FIFO_CTRL_REG 0x2E
#if !defined(L3GD20_BIAS_ACQ_TIMES) || defined(__DOXYGEN__) #define L3GD20_AD_FIFO_SRC_REG 0x2F
#define L3GD20_BIAS_ACQ_TIMES 50 #define L3GD20_AD_INT1_CFG 0x30
#endif #define L3GD20_AD_INT1_SRC 0x31
#define L3GD20_AD_INT1_TSH_XH 0x32
/** #define L3GD20_AD_INT1_TSH_XL 0x33
* @brief Settling time for bias removal #define L3GD20_AD_INT1_TSH_YH 0x34
* @details This is the time between each bias acquisition. #define L3GD20_AD_INT1_TSH_YL 0x35
*/ #define L3GD20_AD_INT1_TSH_ZH 0x36
#if !defined(L3GD20_BIAS_SETTLING_uS) || defined(__DOXYGEN__) #define L3GD20_AD_INT1_TSH_ZL 0x37
#define L3GD20_BIAS_SETTLING_uS 5000 #define L3GD20_AD_INT1_DURATION 0x38
#endif /** @} */
/** @} */
/**
/*===========================================================================*/ * @name L3GD20_CTRL_REG1 register bits definitions
/* Derived constants and error checks. */ * @{
/*===========================================================================*/ */
#define L3GD20_CTRL_REG1_MASK 0xFF /**< L3GD20_CTRL_REG1 mask */
#if !(L3GD20_USE_SPI ^ L3GD20_USE_I2C) #define L3GD20_CTRL_REG1_XEN (1 << 0) /**< X axis enable */
#error "L3GD20_USE_SPI and L3GD20_USE_I2C cannot be both true or both false" #define L3GD20_CTRL_REG1_YEN (1 << 1) /**< Y axis enable */
#endif #define L3GD20_CTRL_REG1_ZEN (1 << 2) /**< Z axis enable */
#define L3GD20_CTRL_REG1_PD (1 << 3) /**< Power-down mode enable */
#if L3GD20_USE_SPI && !HAL_USE_SPI #define L3GD20_CTRL_REG1_BW0 (1 << 4) /**< Bandwidth bit 0 */
#error "L3GD20_USE_SPI requires HAL_USE_SPI" #define L3GD20_CTRL_REG1_BW1 (1 << 5) /**< Bandwidth bit 1 */
#endif #define L3GD20_CTRL_REG1_DR0 (1 << 6) /**< Output data rate bit 0 */
#define L3GD20_CTRL_REG1_DR1 (1 << 7) /**< Output data rate bit 1 */
#if L3GD20_USE_I2C && !HAL_USE_I2C /** @} */
#error "L3GD20_USE_I2C requires HAL_USE_I2C"
#endif /**
* @name L3GD20_CTRL_REG2 register bits definitions
#if L3GD20_SHARED_SPI && !SPI_USE_MUTUAL_EXCLUSION * @{
#error "L3GD20_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION" */
#endif #define L3GD20_CTRL_REG2_MASK 0x3F /**< L3GD20_CTRL_REG2 mask */
#define L3GD20_CTRL_REG2_HPCF0 (1 << 0) /**< HP filter cutoff bit 0 */
/*===========================================================================*/ #define L3GD20_CTRL_REG2_HPCF1 (1 << 1) /**< HP filter cutoff bit 1 */
/* Driver data structures and types. */ #define L3GD20_CTRL_REG2_HPCF2 (1 << 2) /**< HP filter cutoff bit 2 */
/*===========================================================================*/ #define L3GD20_CTRL_REG2_HPCF3 (1 << 3) /**< HP filter cutoff bit 3 */
#define L3GD20_CTRL_REG2_HPM0 (1 << 4) /**< HP filter mode bit 0 */
/** #define L3GD20_CTRL_REG2_HPM1 (1 << 5) /**< HP filter mode bit 1 */
* @name L3GD20 data structures and types /** @} */
* @{
*/ /**
/** * @name L3GD20_CTRL_REG3 register bits definitions
* @brief L3GD20 full scale * @{
*/ */
typedef enum { #define L3GD20_CTRL_REG3_MASK 0xFF /**< L3GD20_CTRL_REG3 mask */
L3GD20_FS_250DPS = 0x00, /**< Full scale 250 degree per second. */ #define L3GD20_CTRL_REG3_I2_EMPTY (1 << 0) /**< FIFO empty IRQ */
L3GD20_FS_500DPS = 0x10, /**< Full scale 500 degree per second. */ #define L3GD20_CTRL_REG3_I2_ORUN (1 << 1) /**< FIFO overrun IRQ */
L3GD20_FS_2000DPS = 0x20 /**< Full scale 2000 degree per second. */ #define L3GD20_CTRL_REG3_I2_WTM (1 << 2) /**< FIFO watermark IRQ */
}l3gd20_fs_t; #define L3GD20_CTRL_REG3_I2_DRDY (1 << 3) /**< Data ready */
#define L3GD20_CTRL_REG3_PP_OD (1 << 4) /**< Push-pull / Open Drain */
/** #define L3GD20_CTRL_REG3_H_LACTIVE (1 << 5) /**< IRQ active */
* @brief L3GD20 output data rate and bandwidth #define L3GD20_CTRL_REG3_I1_BOOT (1 << 6) /**< Boot status available */
*/ #define L3GD20_CTRL_REG3_I1_INT1 (1 << 7) /**< IRQ enable */
typedef enum { /** @} */
L3GD20_ODR_95HZ_FC_12_5 = 0x00, /**< ODR 95 Hz, BW 12.5 Hz. */
L3GD20_ODR_95HZ_FC_25 = 0x10, /**< ODR 95 Hz, BW 25Hz. */ /**
L3GD20_ODR_190HZ_FC_12_5 = 0x40, /**< ODR 190 Hz, BW 12.5 Hz. */ * @name L3GD20_CTRL_REG4 register bits definitions
L3GD20_ODR_190HZ_FC_25 = 0x50, /**< ODR 190 Hz, BW 25 Hz. */ * @{
L3GD20_ODR_190HZ_FC_50 = 0x60, /**< ODR 190 Hz, BW 50 Hz. */ */
L3GD20_ODR_190HZ_FC_70 = 0x70, /**< ODR 190 Hz, BW 70 Hz. */ #define L3GD20_CTRL_REG4_MASK 0xF1 /**< L3GD20_CTRL_REG4 mask */
L3GD20_ODR_380HZ_FC_20 = 0x80, /**< ODR 380 Hz, BW 20 Hz. */ #define L3GD20_CTRL_REG4_SIM (1 << 0) /**< SPI mode */
L3GD20_ODR_380HZ_FC_25 = 0x90, /**< ODR 380 Hz, BW 25 Hz. */ #define L3GD20_CTRL_REG4_FS_MASK (3 << 4) /**< Full scale mask */
L3GD20_ODR_380HZ_FC_50 = 0xA0, /**< ODR 380 Hz, BW 50 Hz. */ #define L3GD20_CTRL_REG4_FS0 (1 << 4) /**< Full scale bit 0 */
L3GD20_ODR_380HZ_FC_100 = 0xB0, /**< ODR 380 Hz, BW 100 Hz. */ #define L3GD20_CTRL_REG4_FS1 (1 << 5) /**< Full scale bit 1 */
L3GD20_ODR_760HZ_FC_30 = 0xC0, /**< ODR 760 Hz, BW 30 Hz. */ #define L3GD20_CTRL_REG4_BLE (1 << 6) /**< Big/little endian data */
L3GD20_ODR_760HZ_FC_35 = 0xD0, /**< ODR 760 Hz, BW 35 Hz. */ #define L3GD20_CTRL_REG4_BDU (1 << 7) /**< Block data update */
L3GD20_ODR_760HZ_FC_50 = 0xE0, /**< ODR 760 Hz, BW 50 Hz. */ /** @} */
L3GD20_ODR_760HZ_FC_100 = 0xF0 /**< ODR 760 Hz, BW 100 Hz. */
}l3gd20_odr_t; /**
* @name L3GD20_CTRL_REG5 register bits definitions
/** * @{
* @brief L3GD20 axes enabling */
*/ #define L3GD20_CTRL_REG5_MASK 0xDF /**< L3GD20_CTRL_REG5 mask */
typedef enum { #define L3GD20_CTRL_REG5_OUT_SEL0 (1 << 0) /**< Out selection bit 0 */
L3GD20_AE_DISABLED = 0x00, /**< All axes disabled. */ #define L3GD20_CTRL_REG5_OUT_SEL1 (1 << 1) /**< Out selection bit 1 */
L3GD20_AE_X = 0x01, /**< Only X-axis enabled. */ #define L3GD20_CTRL_REG5_INT1_SEL0 (1 << 2) /**< INT1 selection bit 0 */
L3GD20_AE_Y = 0x02, /**< Only Y-axis enabled. */ #define L3GD20_CTRL_REG5_INT1_SEL1 (1 << 3) /**< INT1 selection bit 1 */
L3GD20_AE_XY = 0x03, /**< X and Y axes enabled. */ #define L3GD20_CTRL_REG5_HPEN (1 << 4) /**< HP filter enable */
L3GD20_AE_Z = 0x04, /**< Only Z-axis enabled. */ #define L3GD20_CTRL_REG5_FIFO_EN (1 << 6) /**< FIFO enable */
L3GD20_AE_XZ = 0x05, /**< X and Z axes enabled. */ #define L3GD20_CTRL_REG5_BOOT (1 << 7) /**< Reboot memory content */
L3GD20_AE_YZ = 0x06, /**< Y and Z axes enabled. */ /** @} */
L3GD20_AE_XYZ = 0x07 /**< All axes enabled. */
}l3gd20_ae_t; /*===========================================================================*/
/* Driver pre-compile time settings. */
/** /*===========================================================================*/
* @brief L3GD20 block data update
*/ /**
typedef enum { * @name Configuration options
L3GD20_BDU_CONTINUOUS = 0x00, /**< Block data continuously updated. */ * @{
L3GD20_BDU_BLOCKED = 0x80 /**< Block data updated after reading. */ */
}l3gd20_bdu_t; /**
* @brief L3GD20 SPI interface switch.
/** * @details If set to @p TRUE the support for SPI is included.
* @brief L3GD20 endianness * @note The default is @p TRUE.
*/ */
typedef enum { #if !defined(L3GD20_USE_SPI) || defined(__DOXYGEN__)
L3GD20_END_LITTLE = 0x00, /**< Little endian. */ #define L3GD20_USE_SPI TRUE
L3GD20_END_BIG = 0x40 /**< Big endian. */ #endif
}l3gd20_end_t;
/**
/** * @brief L3GD20 I2C interface switch.
* @brief Driver state machine possible states. * @details If set to @p TRUE the support for I2C is included.
*/ * @note The default is @p FALSE.
typedef enum { */
L3GD20_UNINIT = 0, /**< Not initialized. */ #if !defined(L3GD20_USE_I2C) || defined(__DOXYGEN__)
L3GD20_STOP = 1, /**< Stopped. */ #define L3GD20_USE_I2C FALSE
L3GD20_READY = 2, /**< Ready. */ #endif
} l3gd20_state_t;
/**
/** * @brief L3GD20 advanced configurations switch.
* @brief L3GD20 configuration structure. * @details If set to @p TRUE more configurations are available.
*/ * @note The default is @p FALSE.
typedef struct { */
#if !defined(L3GD20_USE_ADVANCED) || defined(__DOXYGEN__)
#if (L3GD20_USE_SPI) || defined(__DOXYGEN__) #define L3GD20_USE_ADVANCED FALSE
/** #endif
* @brief SPI driver associated to this L3GD20.
*/ /**
SPIDriver *spip; * @brief L3GD20 shared SPI switch.
/** * @details If set to @p TRUE the device acquires SPI bus ownership
* @brief SPI configuration associated to this L3GD20. * on each transaction.
*/ * @note The default is @p FALSE. Requires SPI_USE_MUTUAL_EXCLUSION
const SPIConfig *spicfg; */
#endif /* L3GD20_USE_SPI */ #if !defined(L3GD20_SHARED_SPI) || defined(__DOXYGEN__)
#if (L3GD20_USE_I2C) || defined(__DOXYGEN__) #define L3GD20_SHARED_SPI FALSE
/** #endif
* @brief I2C driver associated to this L3GD20.
*/ /**
I2CDriver *i2cp; * @brief Number of acquisitions for bias removal
/** * @details This is the number of acquisitions performed to compute the
* @brief I2C configuration associated to this L3GD20. * bias. A repetition is required in order to remove noise.
*/ */
const I2CConfig *i2ccfg; #if !defined(L3GD20_BIAS_ACQ_TIMES) || defined(__DOXYGEN__)
#endif /* L3GD20_USE_I2C */ #define L3GD20_BIAS_ACQ_TIMES 50
/** #endif
* @brief L3GD20 full scale value.
*/ /**
l3gd20_fs_t fullscale; * @brief Settling time for bias removal
/** * @details This is the time between each bias acquisition.
* @brief L3GD20 output data rate selection. */
*/ #if !defined(L3GD20_BIAS_SETTLING_uS) || defined(__DOXYGEN__)
l3gd20_odr_t outputdatarate; #define L3GD20_BIAS_SETTLING_uS 5000
/** #endif
* @brief L3GD20 axes enabling. /** @} */
*/
l3gd20_ae_t axesenabling; /*===========================================================================*/
/** /* Derived constants and error checks. */
* @brief L3GD20 block data update. /*===========================================================================*/
*/
l3gd20_bdu_t blockdataupdate; #if !(L3GD20_USE_SPI ^ L3GD20_USE_I2C)
/** #error "L3GD20_USE_SPI and L3GD20_USE_I2C cannot be both true or both false"
* @brief L3GD20 endianness. #endif
*/
l3gd20_end_t endianness; #if L3GD20_USE_SPI && !HAL_USE_SPI
} L3GD20Config; #error "L3GD20_USE_SPI requires HAL_USE_SPI"
#endif
/**
* @brief Structure representing a L3GD20 driver. #if L3GD20_USE_I2C && !HAL_USE_I2C
*/ #error "L3GD20_USE_I2C requires HAL_USE_I2C"
typedef struct L3GD20Driver L3GD20Driver; #endif
/** #if L3GD20_SHARED_SPI && !SPI_USE_MUTUAL_EXCLUSION
* @brief @p L3GD20 specific methods. #error "L3GD20_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION"
*/ #endif
#define _l3gd20_methods \
_base_gyroscope_methods \ /*===========================================================================*/
/* Retrieve the temperature of L3GD20 chip.*/ \ /* Driver data structures and types. */
msg_t (*get_temperature)(void *instance, float* temperature); /*===========================================================================*/
/**
/** * @name L3GD20 data structures and types.
* @extends BaseGyroscopeVMT * @{
* */
* @brief @p L3GD20 virtual methods table. /**
*/ * @brief L3GD20 full scale.
struct L3GD20VMT { */
_l3gd20_methods typedef enum {
}; L3GD20_FS_250DPS = 0x00, /**< Full scale 250 degree per second. */
L3GD20_FS_500DPS = 0x10, /**< Full scale 500 degree per second. */
/** L3GD20_FS_2000DPS = 0x20 /**< Full scale 2000 degree per second. */
* @brief @p L3GD20Driver specific data. }l3gd20_fs_t;
*/
#define _l3gd20_data \ /**
_base_gyroscope_data \ * @brief L3GD20 output data rate and bandwidth.
/* Driver state.*/ \ */
l3gd20_state_t state; \ typedef enum {
/* Current configuration data.*/ \ L3GD20_ODR_95HZ = 0x00, /**< Output data rate 95 Hz. */
const L3GD20Config *config; \ L3GD20_ODR_190HZ = 0x40, /**< Output data rate 190 Hz. */
/* Current sensitivity.*/ \ L3GD20_ODR_380HZ = 0x80, /**< Output data rate 380 Hz. */
float sensitivity[L3GD20_NUMBER_OF_AXES]; \ L3GD20_ODR_760HZ = 0xC0 /**< Output data rate 760 Hz. */
/* Bias data.*/ \ }l3gd20_odr_t;
int32_t bias[L3GD20_NUMBER_OF_AXES];
/**
/** * @brief L3GD20 low pass filter 1 bandwidth.
* @extends BaseGyroscope */
* typedef enum {
* @brief L3GD20 3-axis gyroscope class. L3GD20_BW0 = 0x00, /**< LPF1 bandwidth. Depends on ODR. */
* @details This class extends @p BaseGyroscope by adding physical L3GD20_BW1 = 0x40, /**< LPF1 bandwidth. Depends on ODR. */
* driver implementation. L3GD20_BW2 = 0x80, /**< LPF1 bandwidth. Depends on ODR. */
*/ L3GD20_BW3 = 0xC0 /**< LPF1 bandwidth. Depends on ODR. */
struct L3GD20Driver { }l3gd20_bw_t;
/** @brief BaseSensor Virtual Methods Table. */ /**
const struct BaseSensorVMT *vmt_basesensor; * @brief L3GD20 block data update.
/** @brief BaseGyroscope Virtual Methods Table. */ */
const struct BaseGyroscopeVMT *vmt_basegyroscope; typedef enum {
/** @brief L3GD20 Virtual Methods Table. */ L3GD20_BDU_CONTINUOUS = 0x00, /**< Block data continuously updated. */
const struct L3GD20VMT *vmt_l3gd20; L3GD20_BDU_BLOCKED = 0x80 /**< Block data updated after reading. */
_l3gd20_data }l3gd20_bdu_t;
};
/** @} */ /**
* @brief L3GD20 HP filter mode.
/*===========================================================================*/ */
/* Driver macros. */ typedef enum {
/*===========================================================================*/ L3GD20_HPM_NORMAL = 0x00, /**< Normal mode. */
L3GD20_HPM_REFERENCE = 0x10, /**< Reference signal for filtering. */
/** L3GD20_HPM_AUTORESET = 0x30, /**< Autoreset on interrupt event. */
* @brief Get current MEMS temperature. L3GD20_HPM_BYPASSED = 0xFF /**< HP filter bypassed */
* @detail This information is very useful especially for high accuracy IMU }l3gd20_hpm_t;
*
* @param[in] ip pointer to a @p BaseGyroscope class. /**
* @param[out] temp the MEMS temperature as single precision floating. * @brief L3GD20 HP configuration.
* */
* @return The operation status. typedef enum {
* @retval MSG_OK if the function succeeded. L3GD20_HPCF_0 = 0x00, /**< Depends on ODR (Table 26 for more).*/
* @retval MSG_RESET if one or more errors occurred. L3GD20_HPCF_1 = 0x01, /**< Depends on ODR (Table 26 for more).*/
* @api L3GD20_HPCF_2 = 0x02, /**< Depends on ODR (Table 26 for more).*/
*/ L3GD20_HPCF_3 = 0x03, /**< Depends on ODR (Table 26 for more).*/
#define gyroscopeGetTemp(ip, tpp) \ L3GD20_HPCF_4 = 0x04, /**< Depends on ODR (Table 26 for more).*/
(ip)->vmt_l3gd20->get_temperature(ip, tpp) L3GD20_HPCF_5 = 0x05, /**< Depends on ODR (Table 26 for more).*/
L3GD20_HPCF_6 = 0x06, /**< Depends on ODR (Table 26 for more).*/
/*===========================================================================*/ L3GD20_HPCF_7 = 0x07, /**< Depends on ODR (Table 26 for more).*/
/* External declarations. */ L3GD20_HPCF_8 = 0x08, /**< Depends on ODR (Table 26 for more).*/
/*===========================================================================*/ L3GD20_HPCF_9 = 0x09 /**< Depends on ODR (Table 26 for more).*/
}l3gd20_hpcf_t;
#ifdef __cplusplus
extern "C" { /**
#endif * @brief L3GD20 LP2 filter mode.
void l3gd20ObjectInit(L3GD20Driver *devp); * @detail To activate LP2 HP should be active
void l3gd20Start(L3GD20Driver *devp, const L3GD20Config *config); */
void l3gd20Stop(L3GD20Driver *devp); typedef enum {
#ifdef __cplusplus L3GD20_LP2M_ON = 0x00, /**< LP2 filter activated. */
} L3GD20_LP2M_BYPASSED = 0xFF, /**< LP2 filter bypassed. */
#endif }l3gd20_lp2m_t;
#endif /* _L3GD20_H_ */ /**
* @brief L3GD20 endianness.
/** @} */ */
typedef enum {
L3GD20_END_LITTLE = 0x00, /**< Little endian. */
L3GD20_END_BIG = 0x40 /**< Big endian. */
}l3gd20_end_t;
/**
* @brief L3GD20 measurement unit.
*/
typedef enum {
L3GD20_UNIT_DPS = 0x00, /**< Cooked data in degrees per seconds.*/
L3GD20_UNIT_RPS = 0x01, /**< Cooked data in radians per seconds.*/
} l3gd20_unit_t;
/**
* @brief Driver state machine possible states.
*/
typedef enum {
L3GD20_UNINIT = 0, /**< Not initialized. */
L3GD20_STOP = 1, /**< Stopped. */
L3GD20_READY = 2, /**< Ready. */
} l3gd20_state_t;
/**
* @brief L3GD20 configuration structure.
*/
typedef struct {
#if L3GD20_USE_SPI || defined(__DOXYGEN__)
/**
* @brief SPI driver associated to this L3GD20.
*/
SPIDriver *spip;
/**
* @brief SPI configuration associated to this L3GD20.
*/
const SPIConfig *spicfg;
#endif /* L3GD20_USE_SPI */
#if L3GD20_USE_I2C || defined(__DOXYGEN__)
/**
* @brief I2C driver associated to this L3GD20.
*/
I2CDriver *i2cp;
/**
* @brief I2C configuration associated to this L3GD20.
*/
const I2CConfig *i2ccfg;
#endif /* L3GD20_USE_I2C */
/**
* @brief L3GD20 initial sensitivity.
*/
float sensitivity[L3GD20_NUMBER_OF_AXES];
/**
* @brief L3GD20 initial bias.
*/
float bias[L3GD20_NUMBER_OF_AXES];
/**
* @brief L3GD20 initial full scale value.
*/
l3gd20_fs_t fullscale;
/**
* @brief L3GD20 output data rate selection.
*/
l3gd20_odr_t outputdatarate;
#if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
/**
* @brief L3GD20 block data update.
*/
l3gd20_bdu_t blockdataupdate;
/**
* @brief L3GD20 endianness.
*/
l3gd20_end_t endianness;
/**
* @brief L3GD20 LP1 filter bandwidth.
*/
l3gd20_bw_t bandwidth;
/**
* @brief L3GD20 HP filter mode.
*/
l3gd20_hpm_t hpmode;
/**
* @brief L3GD20 HP configuration.
*/
l3gd20_hpcf_t hpconfiguration;
/**
* @brief L3GD20 LP2 filter mode.
* @detail To activate LP2 HP should be active
*/
l3gd20_lp2m_t lp2mode;
#endif
/**
* @brief L3GD20 initial measurement unit.
*/
l3gd20_unit_t unit;
} L3GD20Config;
/**
* @brief Structure representing a L3GD20 driver.
*/
typedef struct L3GD20Driver L3GD20Driver;
/**
* @brief @p L3GD20 specific methods.
*/
#define _l3gd20_methods \
_base_gyroscope_methods \
/* Change full scale value of L3GD20 .*/ \
msg_t (*set_full_scale)(void *instance, l3gd20_fs_t fs); \
/* Get full scale value of L3GD20 .*/ \
l3gd20_fs_t (*get_full_scale)(void *instance); \
/* Change measurement unit of L3GD20 .*/ \
msg_t (*set_meas_unit)(void *instance, l3gd20_unit_t unit); \
/* Get measurement unit of L3GD20 .*/ \
l3gd20_unit_t (*get_meas_unit)(void *instance);
/**
* @extends BaseGyroscopeVMT
*
* @brief @p L3GD20 virtual methods table.
*/
struct L3GD20VMT {
_l3gd20_methods
};
/**
* @brief @p L3GD20Driver specific data.
*/
#define _l3gd20_data \
_base_gyroscope_data \
/* Driver state.*/ \
l3gd20_state_t state; \
/* Current configuration data.*/ \
const L3GD20Config *config; \
/* Current sensitivity data.*/ \
float sensitivity[L3GD20_NUMBER_OF_AXES]; \
/* Current Bias data.*/ \
float bias[L3GD20_NUMBER_OF_AXES]; \
/* Current full scale value.*/ \
float fullscale; \
/* Measurement unit.*/ \
l3gd20_unit_t meas_unit;
/**
* @extends BaseGyroscope
*
* @brief L3GD20 3-axis gyroscope class.
* @details This class extends @p BaseGyroscope by adding physical
* driver implementation.
*/
struct L3GD20Driver {
/** @brief BaseSensor Virtual Methods Table. */
const struct BaseSensorVMT *vmt_basesensor;
/** @brief BaseGyroscope Virtual Methods Table. */
const struct BaseGyroscopeVMT *vmt_basegyroscope;
/** @brief L3GD20 Virtual Methods Table. */
const struct L3GD20VMT *vmt_l3gd20;
_l3gd20_data
};
/** @} */
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Change initial fullscale value.
*
* @param[in] ip pointer to a @p BaseGyroscope class.
* @param[in] fs the new full scale value.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET if one or more errors occurred.
* @api
*/
#define gyroscopeSetFullScale(ip, fs) \
(ip)->vmt_l3gd20->set_full_scale(ip, fs)
/**
* @brief Set gyroscope cooked data measurement unit.
*
* @param[in] ip pointer to a @p BaseGyroscope class.
* @param[in] unit the MEMS measurement unit.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET if one or more errors occurred.
* @api
*/
#define gyroscopeSetMeasurementUnit(ip, unit) \
(ip)->vmt_l3gd20->set_meas_unit(ip, unit)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void l3gd20ObjectInit(L3GD20Driver *devp);
void l3gd20Start(L3GD20Driver *devp, const L3GD20Config *config);
void l3gd20Stop(L3GD20Driver *devp);
#ifdef __cplusplus
}
#endif
#endif /* _L3GD20_H_ */
/** @} */

2
testhal/STM32/STM32F3xx/SPI-L3GD20/halconf.h
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@ -139,7 +139,7 @@
* @brief Enables the SERIAL subsystem. * @brief Enables the SERIAL subsystem.
*/ */
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE #define HAL_USE_SERIAL FALSE
#endif #endif
/** /**

2
testhal/STM32/STM32F3xx/SPI-L3GD20/mcuconf.h
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@ -192,7 +192,7 @@
/* /*
* SERIAL driver system settings. * SERIAL driver system settings.
*/ */
#define STM32_SERIAL_USE_USART1 TRUE #define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE #define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART4 FALSE