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ChibiOS
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Shared some code between types 1 and 2. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15469 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2022-03-04 12:20:30 +00:00
parent 3935737530
commit c0f5c2b5ae
3 changed files with 69 additions and 113 deletions
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35
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -47,6 +47,41 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options (common)
* @{
*/
/**
* @brief Disables the PWR/RCC initialization in the HAL.
* @note All the clock tree constants are calculated but the initialization
* is not performed.
*/
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
#define STM32_NO_INIT FALSE
#endif
/**
* @brief MPU region to be used for no-cache RAM area.
*/
#if !defined(STM32_NOCACHE_MPU_REGION) || defined(__DOXYGEN__)
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#endif
/**
* @brief Add no-cache attribute to SRAM1 and SRAM2.
*/
#if !defined(STM32_NOCACHE_SRAM1_SRAM2) || defined(__DOXYGEN__)
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#endif
/**
* @brief Add no-cache attribute to SRAM3.
*/
#if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__)
#define STM32_NOCACHE_SRAM3 TRUE
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/

62
os/hal/ports/STM32/STM32H7xx/hal_lld_type1.h
View File

@ -76,6 +76,10 @@
#endif
/** @} */
/**
* @name Absolute Maximum Ratings
* @{
*/
#if !defined(STM32_ENFORCE_H7_REV_XY)
/**
* @brief Absolute maximum system clock.
@ -231,6 +235,7 @@
#define STM32_ADCCLK_MAX 36000000
#endif /* defined(STM32_ENFORCE_H7_REV_XY) */
/** @} */
/**
* @name Internal clock sources frequencies
@ -574,18 +579,9 @@
/*===========================================================================*/
/**
* @name Configuration options
* @name Configuration options (type 1)
* @{
*/
/**
* @brief Disables the PWR/RCC initialization in the HAL.
* @note All the clock tree constants are calculated but the initialization
* is not performed.
*/
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
#define STM32_NO_INIT FALSE
#endif
/**
* @brief Target code for this HAL configuration.
* @note Core 1 is the Cortex-M7, core 2 is the Cortex-M4.
@ -594,29 +590,6 @@
#define STM32_TARGET_CORE 1
#endif
/**
* @brief MPU region to be used for no-cache RAM area.
*/
#if !defined(STM32_NOCACHE_MPU_REGION) || defined(__DOXYGEN__)
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#endif
/**
* @brief Add no-cache attribute to SRAM1 and SRAM2.
* @note MPU region 7 is used if enabled.
*/
#if !defined(STM32_NOCACHE_SRAM1_SRAM2) || defined(__DOXYGEN__)
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#endif
/**
* @brief Add no-cache attribute to SRAM3.
* @note MPU region 7 is used if enabled.
*/
#if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__)
#define STM32_NOCACHE_SRAM3 TRUE
#endif
/**
* @brief PWR CR1 initializer.
*/
@ -2239,25 +2212,33 @@
#error "invalid STM32_D1HPRE value specified"
#endif
/*
* AHB frequency check.
*/
#if STM32_HCLK > STM32_HCLK_MAX
#error "STM32_HCLK exceeding maximum frequency (STM32_HCLK_MAX)"
#endif
/**
* @brief Core clock.
* @brief Core 1 clock.
*/
#define STM32_CORE1_CK STM32_SYS_D1CPRE_CK
/**
* @brief Core clock.
* @brief Core 2 clock.
*/
#define STM32_CORE2_CK STM32_HCLK
/**
* @brief Current core clock.
*/
#if (STM32_TARGET_CORE == 1) || defined(__DOXYGEN__)
#if STM32_HAS_M7 != TRUE
#error "Cortex-M7 not present in this device"
#endif
#define STM32_CORE_CK STM32_CORE1_CK
#elif STM32_TARGET_CORE == 2
#if STM32_HAS_M4 != TRUE
#error "Cortex-M4 not present in this device"
#endif
@ -2267,13 +2248,6 @@
#error "invalid STM32_TARGET_CORE value specified"
#endif
/*
* AHB frequency check.
*/
#if STM32_HCLK > STM32_HCLK_MAX
#error "STM32_HCLK exceeding maximum frequency (STM32_HCLK_MAX)"
#endif
/**
* @brief D1 PCLK3 clock.
*/

85
os/hal/ports/STM32/STM32H7xx/hal_lld_type2.h
View File

@ -523,49 +523,9 @@
/*===========================================================================*/
/**
* @name Configuration options
* @name Configuration options (type 2)
* @{
*/
/**
* @brief Disables the PWR/RCC initialization in the HAL.
* @note All the clock tree constants are calculated but the initialization
* is not performed.
*/
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
#define STM32_NO_INIT FALSE
#endif
/**
* @brief Target code for this HAL configuration.
* @note Core 1 is the Cortex-M7, core 2 is the Cortex-M4.
*/
#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__)
#define STM32_TARGET_CORE 1
#endif
/**
* @brief MPU region to be used for no-cache RAM area.
*/
#if !defined(STM32_NOCACHE_MPU_REGION) || defined(__DOXYGEN__)
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#endif
/**
* @brief Add no-cache attribute to SRAM1 and SRAM2.
* @note MPU region 7 is used if enabled.
*/
#if !defined(STM32_NOCACHE_SRAM1_SRAM2) || defined(__DOXYGEN__)
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#endif
/**
* @brief Add no-cache attribute to SRAM3.
* @note MPU region 7 is used if enabled.
*/
#if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__)
#define STM32_NOCACHE_SRAM3 TRUE
#endif
/**
* @brief PWR CR1 initializer.
*/
@ -2168,34 +2128,6 @@
#error "invalid STM32_D1HPRE value specified"
#endif
/**
* @brief Core clock.
*/
#define STM32_CORE1_CK STM32_SYS_D1CPRE_CK
/**
* @brief Core clock.
*/
#define STM32_CORE2_CK STM32_HCLK
#if (STM32_TARGET_CORE == 1) || defined(__DOXYGEN__)
#if STM32_HAS_M7 != TRUE
#error "Cortex-M7 not present in this device"
#endif
#define STM32_CORE_CK STM32_CORE1_CK
#elif STM32_TARGET_CORE == 2
#if STM32_HAS_M4 != TRUE
#error "Cortex-M4 not present in this device"
#endif
#define STM32_CORE_CK STM32_CORE2_CK
#else
#error "invalid STM32_TARGET_CORE value specified"
#endif
/*
* AHB frequency check.
*/
@ -2203,6 +2135,21 @@
#error "STM32_HCLK exceeding maximum frequency (STM32_HCLK_MAX)"
#endif
/**
* @brief Core 1 clock.
*/
#define STM32_CORE1_CK STM32_SYS_D1CPRE_CK
/**
* @brief Core 2 clock.
*/
#define STM32_CORE2_CK 0U
/**
* @brief Current core clock.
*/
#define STM32_CORE_CK STM32_CORE1_CK
/**
* @brief D1 PCLK3 clock.
*/