Fixed Bug #761.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_16.1.x@9666 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -88,8 +88,7 @@ static void hal_lld_backup_domain_init(void) {
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*/
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*/
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void hal_lld_init(void) {
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void hal_lld_init(void) {
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/* Reset of all peripherals. AHB3 is not reseted because it could have
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/* Reset of all peripherals.*/
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been initialized in the board initialization file (board.c).*/
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rccResetAHB1(~0);
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rccResetAHB1(~0);
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rccResetAHB2(~0);
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rccResetAHB2(~0);
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rccResetAHB3(~0);
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rccResetAHB3(~0);
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@ -109,8 +108,20 @@ void hal_lld_init(void) {
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/* Programmable voltage detector enable.*/
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/* Programmable voltage detector enable.*/
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#if STM32_PVD_ENABLE
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#if STM32_PVD_ENABLE
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PWR->CR1 |= PWR_CR1_PVDE | (STM32_PLS & STM32_PLS_MASK);
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PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK);
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#else
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PWR->CR2 = 0;
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#endif /* STM32_PVD_ENABLE */
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#endif /* STM32_PVD_ENABLE */
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/* Enabling independent VDDUSB.*/
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#if HAL_USE_USB
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PWR->CR2 |= PWR_CR2_USV;
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#endif /* HAL_USE_USB */
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/* Enabling independent VDDIO2 required by GPIOG.*/
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#if STM32_HAS_GPIOG
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PWR->CR2 |= PWR_CR2_IOSV;
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#endif /* STM32_HAS_GPIOG */
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}
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}
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/**
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/**
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@ -73,6 +73,7 @@
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*****************************************************************************
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*****************************************************************************
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*** 16.1.5 ***
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*** 16.1.5 ***
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- HAL: Fixed wrong PWR configurations in STM32L4xx\hal_lld (bug #761).
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- HAL: Fixed wrong comment in STM32L4xx\hal_lld (bug #760).
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- HAL: Fixed wrong comment in STM32L4xx\hal_lld (bug #760).
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- HAL: Fixed wrong MSIRANGE management for STM32L4xx in function
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- HAL: Fixed wrong MSIRANGE management for STM32L4xx in function
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stm32_clock_init() (bug #759).
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stm32_clock_init() (bug #759).
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