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Fixed STM32_ADCSEL name, added STM32_RNGSEL default value. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14627 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
vrepetenko 2021-07-28 14:24:03 +00:00
parent d21a907e0c
commit c7ea01877f
3 changed files with 11 additions and 4 deletions
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2
demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h
View File

@ -79,7 +79,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADC1SEL STM32_ADCSEL_NOCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK

11
os/hal/ports/STM32/STM32WLxx/hal_lld.h
View File

@ -708,6 +708,13 @@
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSI
#endif
/**
* @brief RNG clock source.
*/
#if !defined(STM32_RNGSEL) || defined(__DOXYGEN__)
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#endif
/** @} */
/*===========================================================================*/
@ -1244,7 +1251,7 @@
* PLL enable check.
*/
#if (STM32_SW == STM32_SW_PLL) || \
(STM32_ADC1SEL == STM32_ADCSEL_PLLPCLK) || \
(STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLPCLK) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLQCLK) || \
@ -1263,7 +1270,7 @@
/**
* @brief STM32_PLLPEN field.
*/
#if (STM32_ADC1SEL == STM32_ADCSEL_PLLPCLK) || \
#if (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLPCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLPEN (1U << 16)

2
testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -79,7 +79,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADC1SEL STM32_ADCSEL_NOCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK