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STM32H723 demo working. Improved mcuconf.h template for STM32H723 and similar. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15476 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2022-03-10 10:32:05 +00:00
parent c3146a7ae2
commit cf4d9f2584
4 changed files with 23 additions and 16 deletions
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13
demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h
View File

@ -46,8 +46,7 @@
* Memory attributes settings.
*/
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_SRAM1_SRAM2 TRUE
/*
* PWR system settings.
@ -104,11 +103,11 @@
#define STM32_PLL3_Q_ENABLED TRUE
#define STM32_PLL3_R_ENABLED TRUE
#define STM32_PLL3_DIVM_VALUE 4
#define STM32_PLL3_DIVN_VALUE 400
#define STM32_PLL3_DIVN_VALUE 240
#define STM32_PLL3_FRACN_VALUE 0
#define STM32_PLL3_DIVP_VALUE 8
#define STM32_PLL3_DIVQ_VALUE 8
#define STM32_PLL3_DIVR_VALUE 8
#define STM32_PLL3_DIVP_VALUE 10
#define STM32_PLL3_DIVQ_VALUE 10
#define STM32_PLL3_DIVR_VALUE 10
/*
* Core clocks dynamic settings (can be changed at runtime).
@ -149,7 +148,7 @@
#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE_CK
#define STM32_USBSEL STM32_USBSEL_PLL1_Q_CK
#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
#define STM32_I2C1235SEL STM32_I2C1235SEL_PCLK1
#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
#define STM32_USART16910SEL STM32_USART16910SEL_PCLK2

9
os/hal/ports/STM32/STM32H7xx/hal_lld.c
View File

@ -173,6 +173,7 @@ void hal_lld_init(void) {
{
uint32_t base, size;
#if defined(HAL_LLD_TYPE1_H)
#if (STM32_NOCACHE_SRAM1_SRAM2 == TRUE) && (STM32_NOCACHE_SRAM3 == TRUE)
base = 0x30000000U;
size = MPU_RASR_SIZE_512K;
@ -186,6 +187,14 @@ void hal_lld_init(void) {
#error "invalid constants used in mcuconf.h"
#endif
#elif defined(HAL_LLD_TYPE2_H)
#if STM32_NOCACHE_SRAM3 == TRUE
#error "SRAM3 not present on this device"
#endif
base = 0x30000000U;
size = MPU_RASR_SIZE_32K;
#endif
/* The SRAM2 bank can optionally made a non cache-able area for use by
DMA engines.*/
mpuConfigureRegion(STM32_NOCACHE_MPU_REGION,

2
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -86,7 +86,7 @@
* @brief Add no-cache attribute to SRAM3.
*/
#if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__)
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_SRAM3 FALSE
#endif
/** @} */

15
tools/ftl/processors/conf/mcuconf_stm32h723xx/mcuconf.h.ftl
View File

@ -29,7 +29,7 @@
#define MCUCONF_H
/*
* STM32H7xx drivers configuration.
* STM32H723/33/25/35 drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -57,8 +57,7 @@
* Memory attributes settings.
*/
#define STM32_NOCACHE_MPU_REGION ${doc.STM32_NOCACHE_MPU_REGION!"MPU_REGION_6"}
#define STM32_NOCACHE_SRAM1_SRAM2 ${doc.STM32_NOCACHE_SRAM1_SRAM2!"FALSE"}
#define STM32_NOCACHE_SRAM3 ${doc.STM32_NOCACHE_SRAM3!"TRUE"}
#define STM32_NOCACHE_SRAM1_SRAM2 ${doc.STM32_NOCACHE_SRAM1_SRAM2!"TRUE"}
/*
* PWR system settings.
@ -115,11 +114,11 @@
#define STM32_PLL3_Q_ENABLED ${doc.STM32_PLL3_Q_ENABLED!"TRUE"}
#define STM32_PLL3_R_ENABLED ${doc.STM32_PLL3_R_ENABLED!"TRUE"}
#define STM32_PLL3_DIVM_VALUE ${doc.STM32_PLL3_DIVM_VALUE!"4"}
#define STM32_PLL3_DIVN_VALUE ${doc.STM32_PLL3_DIVN_VALUE!"400"}
#define STM32_PLL3_DIVN_VALUE ${doc.STM32_PLL3_DIVN_VALUE!"240"}
#define STM32_PLL3_FRACN_VALUE ${doc.STM32_PLL3_FRACN_VALUE!"0"}
#define STM32_PLL3_DIVP_VALUE ${doc.STM32_PLL3_DIVP_VALUE!"8"}
#define STM32_PLL3_DIVQ_VALUE ${doc.STM32_PLL3_DIVQ_VALUE!"8"}
#define STM32_PLL3_DIVR_VALUE ${doc.STM32_PLL3_DIVR_VALUE!"8"}
#define STM32_PLL3_DIVP_VALUE ${doc.STM32_PLL3_DIVP_VALUE!"10"}
#define STM32_PLL3_DIVQ_VALUE ${doc.STM32_PLL3_DIVQ_VALUE!"10"}
#define STM32_PLL3_DIVR_VALUE ${doc.STM32_PLL3_DIVR_VALUE!"10"}
/*
* Core clocks dynamic settings (can be changed at runtime).
@ -160,7 +159,7 @@
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_PLL1_Q_CK"}
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
#define STM32_CECSEL ${doc.STM32_CECSEL!"STM32_CECSEL_LSE_CK"}
#define STM32_USBSEL ${doc.STM32_USBSEL!"STM32_USBSEL_PLL1_Q_CK"}
#define STM32_USBSEL ${doc.STM32_USBSEL!"STM32_USBSEL_PLL3_Q_CK"}
#define STM32_I2C1235SEL ${doc.STM32_I2C1235SEL!"STM32_I2C1235SEL_PCLK1"}
#define STM32_RNGSEL ${doc.STM32_RNGSEL!"STM32_RNGSEL_HSI48_CK"}
#define STM32_USART16910SEL ${doc.STM32_USART16910SEL!"STM32_USART16910SEL_PCLK2"}