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SPI test at maximum speed. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13333 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-02-08 11:23:54 +00:00
parent 0bbb79d995
commit d4bb13cec9
2 changed files with 5 additions and 5 deletions
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2
testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h
View File

@ -91,7 +91,7 @@
#define STM32_PLL1_DIVN_VALUE 480
#define STM32_PLL1_FRACN_VALUE 0
#define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 20
#define STM32_PLL1_DIVQ_VALUE 4
#define STM32_PLL1_DIVR_VALUE 8
#define STM32_PLL2_ENABLED TRUE
#define STM32_PLL2_P_ENABLED TRUE

8
testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/portab.c
View File

@ -37,7 +37,7 @@
void spi_circular_cb(SPIDriver *spip);
/*
* Circular SPI configuration (25MHz, CPHA=0, CPOL=0, MSb first).
* Circular SPI configuration (30MHz, CPHA=0, CPOL=0, MSb first).
*/
const SPIConfig c_spicfg = {
true,
@ -49,19 +49,19 @@ const SPIConfig c_spicfg = {
};
/*
* Maximum speed SPI configuration (25MHz, CPHA=0, CPOL=0, MSb first).
* Maximum speed SPI configuration (120MHz, CPHA=0, CPOL=0, MSb first).
*/
const SPIConfig hs_spicfg = {
false,
NULL,
GPIOD,
14,
SPI_CFG1_MBR_DIV8 | SPI_CFG1_DSIZE_VALUE(7),
SPI_CFG1_MBR_DIV2 | SPI_CFG1_DSIZE_VALUE(7),
0
};
/*
* Low speed SPI configuration (1.5625MHz, CPHA=0, CPOL=0, MSb first).
* Low speed SPI configuration (1,875MHz, CPHA=0, CPOL=0, MSb first).
*/
const SPIConfig ls_spicfg = {
false,