Missing NO_INIT check.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14297 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -121,6 +121,7 @@ void hal_lld_init(void) {
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*/
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void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* Reset of all peripherals.
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Note, GPIOs are not reset because initialized before this point in
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board files.*/
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@ -140,7 +141,7 @@ void stm32_clock_init(void) {
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
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/* Core voltage setup, backup domain access enabled and left open.*/
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PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
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@ -239,6 +240,7 @@ void stm32_clock_init(void) {
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(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
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}
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}
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#endif /* STM32_NO_INIT */
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}
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/** @} */
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@ -121,6 +121,7 @@ void hal_lld_init(void) {
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*/
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void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* Reset of all peripherals.
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Note, GPIOs are not reset because initialized before this point in
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board files.*/
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@ -140,7 +141,7 @@ void stm32_clock_init(void) {
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
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/* Core voltage setup, backup domain access enabled and left open.*/
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PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
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@ -238,6 +239,7 @@ void stm32_clock_init(void) {
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(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
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}
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}
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#endif /* STM32_NO_INIT */
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}
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/** @} */
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