More updaters for F4.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13848 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
8fc602dc53
commit
dc0302e867
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@ -1015,6 +1015,18 @@
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#error "Using a wrong mcuconf.h file, STM32F401_MCUCONF not defined"
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#endif
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#if defined(STM32F410xx) && !defined(STM32F410_MCUCONF)
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#error "Using a wrong mcuconf.h file, STM32F410_MCUCONF not defined"
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#endif
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#if defined(STM32F411xx) && !defined(STM32F411_MCUCONF)
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#error "Using a wrong mcuconf.h file, STM32F411_MCUCONF not defined"
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#endif
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#if defined(STM32F412xx) && !defined(STM32F412_MCUCONF)
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#error "Using a wrong mcuconf.h file, STM32F412_MCUCONF not defined"
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#endif
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#if defined(STM32F405xx) && !defined(STM32F405_MCUCONF)
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#error "Using a wrong mcuconf.h file, STM32F405_MCUCONF not defined"
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#endif
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@ -2372,7 +2372,7 @@
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#define STM32_HAS_I2C3 FALSE
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#define STM32_HAS_I2C4 FALSE
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#define STM32_HAS_I2C4 TRUE
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#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) |\
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STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C4_RX_DMA_CHN 0x00002007
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@ -76,8 +76,8 @@
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*** Next ***
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- NEW: Updated STM32F4xx platform with new IRQ handling, enabled the missing
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timers.
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- NEW: Added mcuconf.h updater for STM32F401, F427, F429, F437, F439,
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F446, F469, F479.
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- NEW: Added mcuconf.h updater for STM32F401, STM32F410, STM32F411, STM32F412,
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F427, F429, F437, F439, F446, F469, F479.
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- NEW: SIO STM32 implementation for USARTs without FIFO in STM32/LLD/USARTv2,
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implementation with FIFO in STM32/LLD/USARTv3.
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- NEW: Updated SIO driver model to support more use cases.
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@ -0,0 +1,267 @@
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[#ftl]
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[#--
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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--]
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[@pp.dropOutputFile /]
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[#import "/@lib/libutils.ftl" as utils /]
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[#import "/@lib/liblicense.ftl" as license /]
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[@pp.changeOutputFile name="mcuconf.h" /]
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/*
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[@license.EmitLicenseAsText /]
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32F4xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F4xx_MCUCONF
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#define STM32F410_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
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#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
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#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
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#define STM32_BKPRAM_ENABLE ${doc.STM32_BKPRAM_ENABLE!"FALSE"}
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#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
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#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
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#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
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#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
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#define STM32_CLOCK48_REQUIRED ${doc.STM32_CLOCK48_REQUIRED!"TRUE"}
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#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
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#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
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#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"16"}
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#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"200"}
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#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"2"}
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#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"8"}
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#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
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#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV2"}
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#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
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#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
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#define STM32_RTCPRE_VALUE ${doc.STM32_RTCPRE_VALUE!"8"}
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#define STM32_MCO1SEL ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI"}
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#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
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#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
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#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV5"}
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#define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_CKIN"}
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#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"200"}
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#define STM32_PLLI2SR_VALUE ${doc.STM32_PLLI2SR_VALUE!"4"}
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
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#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
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#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
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#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
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#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
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#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
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#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
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#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
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#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"15"}
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#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
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#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
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#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
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#define STM32_IRQ_EXTI21_PRIORITY ${doc.STM32_IRQ_EXTI21_PRIORITY!"15"}
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#define STM32_IRQ_EXTI22_PRIORITY ${doc.STM32_IRQ_EXTI22_PRIORITY!"15"}
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#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM9_PRIORITY!"7"}
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#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM10_PRIORITY!"7"}
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#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY!"7"}
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#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
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#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
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#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
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#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
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#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
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#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
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#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
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#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"12"}
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#define STM32_IRQ_USART6_PRIORITY ${doc.STM32_IRQ_USART6_PRIORITY!"12"}
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_ADCPRE ${doc.STM32_ADC_ADCPRE!"ADC_CCR_ADCPRE_DIV4"}
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#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
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#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
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#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
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#define STM32_ADC_IRQ_PRIORITY ${doc.STM32_ADC_IRQ_PRIORITY!"6"}
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"6"}
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
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#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
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#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
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#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
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#define STM32_GPT_USE_TIM9 ${doc.STM32_GPT_USE_TIM9!"FALSE"}
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#define STM32_GPT_USE_TIM11 ${doc.STM32_GPT_USE_TIM11!"FALSE"}
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
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#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
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#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
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#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
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#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
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#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
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#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
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#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
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#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
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#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
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#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
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#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
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#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
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#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
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#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
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#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
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/*
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* I2S driver system settings.
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*/
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#define STM32_I2S_USE_SPI1 ${doc.STM32_I2S_USE_SPI1!"FALSE"}
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#define STM32_I2S_USE_SPI2 ${doc.STM32_I2S_USE_SPI2!"FALSE"}
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#define STM32_I2S_USE_SPI5 ${doc.STM32_I2S_USE_SPI5!"FALSE"}
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#define STM32_I2S_SPI1_IRQ_PRIORITY ${doc.STM32_I2S_SPI1_IRQ_PRIORITY!"10"}
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#define STM32_I2S_SPI2_IRQ_PRIORITY ${doc.STM32_I2S_SPI2_IRQ_PRIORITY!"10"}
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#define STM32_I2S_SPI5_IRQ_PRIORITY ${doc.STM32_I2S_SPI5_IRQ_PRIORITY!"10"}
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#define STM32_I2S_SPI1_DMA_PRIORITY ${doc.STM32_I2S_SPI1_DMA_PRIORITY!"1"}
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#define STM32_I2S_SPI2_DMA_PRIORITY ${doc.STM32_I2S_SPI2_DMA_PRIORITY!"1"}
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#define STM32_I2S_SPI5_DMA_PRIORITY ${doc.STM32_I2S_SPI5_DMA_PRIORITY!"1"}
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#define STM32_I2S_SPI1_RX_DMA_STREAM ${doc.STM32_I2S_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
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#define STM32_I2S_SPI1_TX_DMA_STREAM ${doc.STM32_I2S_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
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#define STM32_I2S_SPI2_RX_DMA_STREAM ${doc.STM32_I2S_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
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#define STM32_I2S_SPI2_TX_DMA_STREAM ${doc.STM32_I2S_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
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#define STM32_I2S_SPI5_RX_DMA_STREAM ${doc.STM32_I2S_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
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#define STM32_I2S_SPI5_TX_DMA_STREAM ${doc.STM32_I2S_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
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#define STM32_I2S_DMA_ERROR_HOOK(i2sp) ${doc.STM32_I2S_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
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/*
|
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
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#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
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#define STM32_ICU_USE_TIM9 ${doc.STM32_ICU_USE_TIM9!"FALSE"}
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#define STM32_ICU_USE_TIM11 ${doc.STM32_ICU_USE_TIM11!"FALSE"}
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/*
|
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* PWM driver system settings.
|
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*/
|
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#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
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#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
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#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
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#define STM32_PWM_USE_TIM9 ${doc.STM32_PWM_USE_TIM9!"FALSE"}
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#define STM32_PWM_USE_TIM11 ${doc.STM32_PWM_USE_TIM11!"FALSE"}
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/*
|
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* RTC driver system settings.
|
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*/
|
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#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
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#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
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#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
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#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
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|
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/*
|
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* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
|
||||
|
||||
/*
|
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* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
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#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
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#define STM32_SPI_USE_SPI5 ${doc.STM32_SPI_USE_SPI5!"FALSE"}
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#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
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#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
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#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
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#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
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#define STM32_SPI_SPI5_RX_DMA_STREAM ${doc.STM32_SPI_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
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#define STM32_SPI_SPI5_TX_DMA_STREAM ${doc.STM32_SPI_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
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#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
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#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
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#define STM32_SPI_SPI5_DMA_PRIORITY ${doc.STM32_SPI_SPI5_DMA_PRIORITY!"1"}
|
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#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
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#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
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#define STM32_SPI_SPI5_IRQ_PRIORITY ${doc.STM32_SPI_SPI5_IRQ_PRIORITY!"10"}
|
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#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
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|
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/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
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|
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/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
#define STM32_USB_HOST_WAKEUP_DURATION ${doc.STM32_USB_HOST_WAKEUP_DURATION!"2"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F4xx_MCUCONF
|
||||
#define STM32F411_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_BKPRAM_ENABLE ${doc.STM32_BKPRAM_ENABLE!"FALSE"}
|
||||
#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_CLOCK48_REQUIRED ${doc.STM32_CLOCK48_REQUIRED!"TRUE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"16"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"384"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"4"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"8"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV2"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
#define STM32_RTCPRE_VALUE ${doc.STM32_RTCPRE_VALUE!"8"}
|
||||
#define STM32_MCO1SEL ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI"}
|
||||
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
|
||||
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
|
||||
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV5"}
|
||||
#define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_CKIN"}
|
||||
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
|
||||
#define STM32_PLLI2SR_VALUE ${doc.STM32_PLLI2SR_VALUE!"5"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_PRIORITY ${doc.STM32_IRQ_EXTI21_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI22_PRIORITY ${doc.STM32_IRQ_EXTI22_PRIORITY!"15"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM9_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM10_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART6_PRIORITY ${doc.STM32_IRQ_USART6_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ${doc.STM32_ADC_ADCPRE!"ADC_CCR_ADCPRE_DIV4"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_IRQ_PRIORITY ${doc.STM32_ADC_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"6"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM9 ${doc.STM32_GPT_USE_TIM9!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM10 ${doc.STM32_GPT_USE_TIM10!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM11 ${doc.STM32_GPT_USE_TIM11!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* I2S driver system settings.
|
||||
*/
|
||||
#define STM32_I2S_USE_SPI2 ${doc.STM32_I2S_USE_SPI2!"FALSE"}
|
||||
#define STM32_I2S_USE_SPI3 ${doc.STM32_I2S_USE_SPI3!"FALSE"}
|
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY ${doc.STM32_I2S_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2S_SPI3_IRQ_PRIORITY ${doc.STM32_I2S_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2S_SPI2_DMA_PRIORITY ${doc.STM32_I2S_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2S_SPI3_DMA_PRIORITY ${doc.STM32_I2S_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2S_SPI2_RX_DMA_STREAM ${doc.STM32_I2S_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2S_SPI2_TX_DMA_STREAM ${doc.STM32_I2S_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2S_SPI3_RX_DMA_STREAM ${doc.STM32_I2S_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2S_SPI3_TX_DMA_STREAM ${doc.STM32_I2S_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) ${doc.STM32_I2S_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM9 ${doc.STM32_ICU_USE_TIM9!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM10 ${doc.STM32_ICU_USE_TIM10!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM11 ${doc.STM32_ICU_USE_TIM11!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM9 ${doc.STM32_PWM_USE_TIM9!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM10 ${doc.STM32_PWM_USE_TIM10!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM11 ${doc.STM32_PWM_USE_TIM11!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
#define STM32_USB_HOST_WAKEUP_DURATION ${doc.STM32_USB_HOST_WAKEUP_DURATION!"2"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,312 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F4xx_MCUCONF
|
||||
#define STM32F412_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_BKPRAM_ENABLE ${doc.STM32_BKPRAM_ENABLE!"FALSE"}
|
||||
#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_CLOCK48_REQUIRED ${doc.STM32_CLOCK48_REQUIRED!"TRUE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"8"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"334"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"4"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"8"}
|
||||
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"4"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV2"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
#define STM32_RTCPRE_VALUE ${doc.STM32_RTCPRE_VALUE!"8"}
|
||||
#define STM32_MCO1SEL ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI"}
|
||||
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
|
||||
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
|
||||
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV5"}
|
||||
#define STM32_PLLI2SSRC ${doc.STM32_PLLI2SSRC!"STM32_PLLI2SSRC_PLLSRC"}
|
||||
#define STM32_I2SCKIN_VALUE ${doc.STM32_I2SCKIN_VALUE!"0"}
|
||||
#define STM32_PLLI2SM_VALUE ${doc.STM32_PLLI2SM_VALUE!"8"}
|
||||
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
|
||||
#define STM32_PLLI2SR_VALUE ${doc.STM32_PLLI2SR_VALUE!"4"}
|
||||
#define STM32_PLLI2SQ_VALUE ${doc.STM32_PLLI2SQ_VALUE!"4"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_PRIORITY ${doc.STM32_IRQ_EXTI21_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI22_PRIORITY ${doc.STM32_IRQ_EXTI22_PRIORITY!"15"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM9_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM10_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY ${doc.STM32_IRQ_TIM8_BRK_TIM12_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY ${doc.STM32_IRQ_TIM8_UP_TIM13_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY ${doc.STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART6_PRIORITY ${doc.STM32_IRQ_USART6_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ${doc.STM32_ADC_ADCPRE!"ADC_CCR_ADCPRE_DIV4"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_IRQ_PRIORITY ${doc.STM32_ADC_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"6"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_USE_CAN2 ${doc.STM32_CAN_USE_CAN2!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY ${doc.STM32_CAN_CAN2_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM9 ${doc.STM32_GPT_USE_TIM9!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM10 ${doc.STM32_GPT_USE_TIM10!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM11 ${doc.STM32_GPT_USE_TIM11!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM12 ${doc.STM32_GPT_USE_TIM12!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM13 ${doc.STM32_GPT_USE_TIM13!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM14 ${doc.STM32_GPT_USE_TIM14!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* I2S driver system settings.
|
||||
*/
|
||||
#define STM32_I2S_USE_SPI2 ${doc.STM32_I2S_USE_SPI2!"FALSE"}
|
||||
#define STM32_I2S_USE_SPI3 ${doc.STM32_I2S_USE_SPI3!"FALSE"}
|
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY ${doc.STM32_I2S_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2S_SPI3_IRQ_PRIORITY ${doc.STM32_I2S_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2S_SPI2_DMA_PRIORITY ${doc.STM32_I2S_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2S_SPI3_DMA_PRIORITY ${doc.STM32_I2S_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2S_SPI2_RX_DMA_STREAM ${doc.STM32_I2S_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2S_SPI2_TX_DMA_STREAM ${doc.STM32_I2S_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2S_SPI3_RX_DMA_STREAM ${doc.STM32_I2S_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2S_SPI3_TX_DMA_STREAM ${doc.STM32_I2S_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) ${doc.STM32_I2S_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM9 ${doc.STM32_ICU_USE_TIM9!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM10 ${doc.STM32_ICU_USE_TIM10!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM11 ${doc.STM32_ICU_USE_TIM11!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM12 ${doc.STM32_ICU_USE_TIM12!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM13 ${doc.STM32_ICU_USE_TIM13!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM14 ${doc.STM32_ICU_USE_TIM14!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM9 ${doc.STM32_PWM_USE_TIM9!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM10 ${doc.STM32_PWM_USE_TIM10!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM11 ${doc.STM32_PWM_USE_TIM11!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM12 ${doc.STM32_PWM_USE_TIM12!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM13 ${doc.STM32_PWM_USE_TIM13!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM14 ${doc.STM32_PWM_USE_TIM14!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"TRUE"}
|
||||
#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI4 ${doc.STM32_SPI_USE_SPI4!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI5 ${doc.STM32_SPI_USE_SPI5!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM ${doc.STM32_SPI_SPI4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM ${doc.STM32_SPI_SPI4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_SPI_SPI5_RX_DMA_STREAM ${doc.STM32_SPI_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_SPI_SPI5_TX_DMA_STREAM ${doc.STM32_SPI_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY ${doc.STM32_SPI_SPI4_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY ${doc.STM32_SPI_SPI5_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY ${doc.STM32_SPI_SPI4_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY ${doc.STM32_SPI_SPI5_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
#define STM32_USB_HOST_WAKEUP_DURATION ${doc.STM32_USB_HOST_WAKEUP_DURATION!"2"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#!/bin/bash
|
||||
if [ $# -eq 2 ]
|
||||
then
|
||||
if [ $1 = "rootpath" ]
|
||||
then
|
||||
find $2 -name "mcuconf.h" -exec bash update_mcuconf_stm32f410xx.sh "{}" \;
|
||||
else
|
||||
echo "Usage: update_mcuconf_stm32f410xx.sh [rootpath <root path>]"
|
||||
fi
|
||||
elif [ $# -eq 1 ]
|
||||
then
|
||||
declare conffile=$(<$1)
|
||||
if egrep -q "STM32F410_MCUCONF" <<< "$conffile"
|
||||
then
|
||||
echo Processing: $1
|
||||
egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[^\s]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt
|
||||
if ! fmpp -q -C conf.fmpp -S ../ftl/processors/conf/mcuconf_stm32f410xx
|
||||
then
|
||||
echo
|
||||
echo "aborted"
|
||||
exit 1
|
||||
fi
|
||||
cp ./mcuconf.h $1
|
||||
rm ./mcuconf.h ./values.txt
|
||||
fi
|
||||
else
|
||||
echo "Usage: update_mcuconf_stm32f410xx.sh [rootpath <root path>]"
|
||||
echo " update_mcuconf_stm32f410xx.sh <configuration file>]"
|
||||
fi
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#!/bin/bash
|
||||
if [ $# -eq 2 ]
|
||||
then
|
||||
if [ $1 = "rootpath" ]
|
||||
then
|
||||
find $2 -name "mcuconf.h" -exec bash update_mcuconf_stm32f411xx.sh "{}" \;
|
||||
else
|
||||
echo "Usage: update_mcuconf_stm32f411xx.sh [rootpath <root path>]"
|
||||
fi
|
||||
elif [ $# -eq 1 ]
|
||||
then
|
||||
declare conffile=$(<$1)
|
||||
if egrep -q "STM32F411_MCUCONF" <<< "$conffile"
|
||||
then
|
||||
echo Processing: $1
|
||||
egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[^\s]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt
|
||||
if ! fmpp -q -C conf.fmpp -S ../ftl/processors/conf/mcuconf_stm32f411xx
|
||||
then
|
||||
echo
|
||||
echo "aborted"
|
||||
exit 1
|
||||
fi
|
||||
cp ./mcuconf.h $1
|
||||
rm ./mcuconf.h ./values.txt
|
||||
fi
|
||||
else
|
||||
echo "Usage: update_mcuconf_stm32f411xx.sh [rootpath <root path>]"
|
||||
echo " update_mcuconf_stm32f411xx.sh <configuration file>]"
|
||||
fi
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#!/bin/bash
|
||||
if [ $# -eq 2 ]
|
||||
then
|
||||
if [ $1 = "rootpath" ]
|
||||
then
|
||||
find $2 -name "mcuconf.h" -exec bash update_mcuconf_stm32f412xx.sh "{}" \;
|
||||
else
|
||||
echo "Usage: update_mcuconf_stm32f412xx.sh [rootpath <root path>]"
|
||||
fi
|
||||
elif [ $# -eq 1 ]
|
||||
then
|
||||
declare conffile=$(<$1)
|
||||
if egrep -q "STM32F412_MCUCONF" <<< "$conffile"
|
||||
then
|
||||
echo Processing: $1
|
||||
egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[^\s]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt
|
||||
if ! fmpp -q -C conf.fmpp -S ../ftl/processors/conf/mcuconf_stm32f412xx
|
||||
then
|
||||
echo
|
||||
echo "aborted"
|
||||
exit 1
|
||||
fi
|
||||
cp ./mcuconf.h $1
|
||||
rm ./mcuconf.h ./values.txt
|
||||
fi
|
||||
else
|
||||
echo "Usage: update_mcuconf_stm32f412xx.sh [rootpath <root path>]"
|
||||
echo " update_mcuconf_stm32f412xx.sh <configuration file>]"
|
||||
fi
|
||||
Loading…
Reference in New Issue