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Style-related fixes, mainly white space. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14999 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-11-03 07:01:57 +00:00
parent ba6f180920
commit dcc0824e97
49 changed files with 5870 additions and 5892 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
View File

@ -31,7 +31,7 @@
/*===========================================================================*/
#if STM32_ADC_DUAL_MODE == TRUE
#define ADC12_CCR_DUAL ADC_CCR_DUAL_REG_SIMULT
#define ADC12_CCR_DUAL ADC_CCR_DUAL_REG_SIMULT
#if STM32_ADC_SAMPLES_SIZE == 8
/* Compact type dual mode, 2x8-bit.*/
#define ADC12_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
@ -46,7 +46,7 @@
#endif /* STM32_ADC_SAMPLES_SIZE == 8 */
#else /* STM32_ADC_DUAL_MODE == FALSE */
#define ADC12_CCR_DUAL ADC_CCR_DUAL_INDEPENDENT
#define ADC12_CCR_DUAL ADC_CCR_DUAL_INDEPENDENT
#if STM32_ADC_SAMPLES_SIZE == 8
/* Compact type single mode, 8-bit.*/
#define ADC12_DMA_SIZE (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
@ -641,9 +641,9 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adcm->ISR = adcp->adcm->ISR;
/* If a callback is set enable the overflow and analog watch dog interrupts. */
if (grpp->error_cb != NULL) {
adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE
| ADC_IER_AWD2IE
| ADC_IER_AWD3IE;
adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE |
ADC_IER_AWD2IE |
ADC_IER_AWD3IE;
}
#if STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE
/* Configuration for dual mode ADC12 */
@ -652,9 +652,10 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adcs->ISR = adcp->adcs->ISR;
/* If a callback is set enable the overflow and analog watch dog interrupts. */
if (grpp->error_cb != NULL) {
adcp->adcs->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE
| ADC_IER_AWD2IE
| ADC_IER_AWD3IE;
adcp->adcs->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE |
ADC_IER_AWD2IE |
ADC_IER_AWD3IE;
/* Configuring the CCR register with the user-specified settings
in the conversion group configuration structure, static settings are
preserved.*/

6
os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
View File

@ -199,7 +199,7 @@
/**
* @brief Specifies the ADC samples width.
* @note Must be 8, 16 or 32.
* @note 10, 12, 14 and 16 bits sampling modes must not be used when
* @note 10, 12, 14 and 16 bits sampling modes must not be used when
* this option is set to 8.
* @note 32 is useful when oversampling is activated.
*/
@ -374,8 +374,8 @@
#error "Invalid IRQ priority assigned to ADC3"
#endif
#if ((STM32_ADC_SAMPLES_SIZE != 8) && \
(STM32_ADC_SAMPLES_SIZE != 16) && \
#if ((STM32_ADC_SAMPLES_SIZE != 8) && \
(STM32_ADC_SAMPLES_SIZE != 16) && \
(STM32_ADC_SAMPLES_SIZE != 32))
#error "STM32_ADC_SAMPLES_SIZE must be 8, 16 or 32"
#endif

1
os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
View File

@ -254,7 +254,6 @@
#error "ADC DMA stream not defined"
#endif
/* ADC clock source checks.*/
#if STM32_ADC_PRESCALER_VALUE == 2
#define STM32_ADC_PRESC 1U

2
os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c
View File

@ -1540,7 +1540,7 @@ cryerror_t cry_lld_SHA256_init(CRYDriver *cryp, SHA256Context *sha256ctxp) {
sha256ctxp->last_size = 0U;
/* Initializing operation.*/
HASH->CR = /*HASH_CR_MDMAT |*/ HASH_CR_ALGO_1 | HASH_CR_ALGO_0 |
HASH->CR = /* HASH_CR_MDMAT |*/ HASH_CR_ALGO_1 | HASH_CR_ALGO_0 |
HASH_CR_DATATYPE_1 | HASH_CR_INIT;
return CRY_NOERROR;

7
os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.c
View File

@ -89,7 +89,6 @@
#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TMSA + \
(STM32_FDCAN_TM_NBR * SRAMCAN_TM_SIZE)))
#define TIMEOUT_INIT_MS 250U
#define TIMEOUT_CSA_MS 250U
@ -389,7 +388,7 @@ void can_lld_transmit(CANDriver *canp, canmbx_t mailbox, const CANTxFrame *ctfp)
/* Writing frame.*/
tx_address = canp->ram_base +
((SRAMCAN_TBSA + (put_index * SRAMCAN_TB_SIZE)) / sizeof (uint32_t));
*tx_address++ = ctfp->header32[0];
*tx_address++ = ctfp->header32[1];
for (unsigned i = 0U; i < dlc_to_bytes[ctfp->DLC]; i += 4U) {
@ -451,7 +450,7 @@ void can_lld_receive(CANDriver *canp, canmbx_t mailbox, CANRxFrame *crfp) {
return;
}
}
if (mailbox == 1U) {
/* GET index RXF0, add it and the length to the rx_address.*/
get_index = (canp->fdcan->RXF0S & FDCAN_RXF0S_F0GI_Msk) >> FDCAN_RXF0S_F0GI_Pos;
@ -567,7 +566,7 @@ void can_lld_serve_interrupt(CANDriver *canp) {
}
/* Overflow events.*/
if (((ir & FDCAN_IR_RF0L) != 0U) || ((ir & FDCAN_IR_RF1L) != 0U) ) {
if (((ir & FDCAN_IR_RF0L) != 0U) || ((ir & FDCAN_IR_RF1L) != 0U)) {
_can_error_isr(canp, CAN_OVERFLOW_ERROR);
}

2
os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.h
View File

@ -287,7 +287,6 @@ typedef struct {
};
} CANRxStandardFilter;
/**
* @brief CAN extended filter.
* @note Accessing the frame data as word16 or word32 is not portable
@ -311,7 +310,6 @@ typedef struct {
};
} CANRxExtendedFilter;
/**
* @brief Type of a CAN configuration structure.
*/

6
os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
View File

@ -81,7 +81,7 @@
#define I2C_EV9_MASTER_ADD10 \
((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_ADD10))
#define I2C_EV5_MASTER_MODE_INVALID \
((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | (I2C_SR1_SB | \
I2C_SR1_STOPF)))
@ -284,7 +284,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
break;
case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
/* Catches BTF event after the end of transmission.*/
(void)dp->DR; /* clear BTF.*/
(void)dp->DR; /* Clear BTF.*/
if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) {
/* Starts "read after write" operation, LSB = 1 -> receive.*/
i2cp->addr |= 0x01;
@ -306,7 +306,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))
(void)dp->SR2;
/* BERR flag doesn’t happen anymore in event handling */
/* BERR flag doesn<EFBFBD>t happen anymore in event handling */
#if 0
/* Errata 2.4.6 for STM32F40x, Spurious Bus Error detection in Master mode.*/
if (event & I2C_SR1_BERR) {

22
os/hal/ports/STM32/LLD/MACv2/hal_mac_lld.c
View File

@ -279,7 +279,7 @@ OSAL_IRQ_HANDLER(STM32_ETH_HANDLER) {
* @notapi
*/
void mac_lld_init(void) {
unsigned i,j;
unsigned i, j;
macObjectInit(&ETHD1);
ETHD1.link_up = false;
@ -292,7 +292,7 @@ void mac_lld_init(void) {
__eth_rd[i].rdes2 = 0;
__eth_rd[i].rdes3 = STM32_RDES3_OWN | STM32_RDES3_IOC | STM32_RDES3_BUF1V;
for (j = 0; j < BUFFER_SIZE; j++) {
__eth_rb[i][j] = 825373492; /* telltale "1234" */
__eth_rb[i][j] = 825373492; /* Telltale "1234".*/
}
}
for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) {
@ -301,7 +301,7 @@ void mac_lld_init(void) {
__eth_td[i].tdes2 = 0;
__eth_td[i].tdes3 = 0;
for (j = 0; j < BUFFER_SIZE; j++) {
__eth_tb[i][j] = 892745528; /* telltale "5678" */
__eth_tb[i][j] = 892745528; /* Telltale "5678".*/
}
}
@ -376,7 +376,7 @@ void mac_lld_start(MACDriver *macp) {
/* MAC clocks activation and commanded reset procedure.*/
rccEnableETH(true);
/* ISR vector enabled.*/
nvicEnableVector(STM32_ETH_NUMBER, STM32_MAC_ETH1_IRQ_PRIORITY);
@ -426,7 +426,6 @@ void mac_lld_start(MACDriver *macp) {
ETH->DMACSR = ETH_DMACSR_NIS;
ETH->DMACIER = ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE;
/* Check because errata on some devices. There should be no need to
disable flushing because the TXFIFO should be empty on macStart().*/
#if !defined(STM32_MAC_DISABLE_TX_FLUSH)
@ -440,9 +439,8 @@ void mac_lld_start(MACDriver *macp) {
ETH->MTLRQOMR = ETH_MTLRQOMR_DISTCPEF | ETH_MTLRQOMR_RSF;
ETH->MTLTQOMR = ETH_MTLTQOMR_TSF;
ETH->DMACTCR = ETH_DMACTCR_ST | ETH_DMACTCR_TPBL_1PBL;
ETH->DMACRCR = ETH_DMACRCR_SR | ETH_DMACRCR_RPBL_1PBL
| (STM32_MAC_BUFFERS_SIZE << ETH_DMACRCR_RBSZ_Pos
& ETH_DMACRCR_RBSZ);
ETH->DMACRCR = ETH_DMACRCR_SR | ETH_DMACRCR_RPBL_1PBL |
(STM32_MAC_BUFFERS_SIZE << ETH_DMACRCR_RBSZ_Pos & ETH_DMACRCR_RBSZ);
}
/**
@ -503,9 +501,9 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
return MSG_TIMEOUT;
}
tdes->tdes0 = (uint32_t )__eth_tb[macp->tdindex];
/* Marks the current descriptor as locked using a reserved bit.*/
/*tdes->tdes0 |= STM32_TDES0_LOCKED; */
tdes->tdes0 = (uint32_t)__eth_tb[macp->tdindex];
/* Marks the current descriptor as locked using a reserved bit.
tdes->tdes0 |= STM32_TDES0_LOCKED; */
tdes->tdes1++;
/* Next TX descriptor to use.*/
@ -589,7 +587,7 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
&& (rdes->rdes3 & STM32_RDES3_FD) && (rdes->rdes3 & STM32_RDES3_LD)) {
/* Found a valid one.*/
rdp->offset = 0;
rdp->size = (rdes->rdes3 & STM32_RDES3_PL_MASK) -2; /* Lose CRC */
rdp->size = (rdes->rdes3 & STM32_RDES3_PL_MASK) -2; /* Lose CRC.*/
rdp->physdesc = rdes;
/* Reposition in ring.*/
macp->rdindex++;

12
os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
View File

@ -510,12 +510,14 @@ static void otg_isoc_out_failed_handler(USBDriver *usbp) {
for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) &&
((otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) != 0)) {
/* Endpoint enabled -> ISOC OUT transfer failed */
/* Disable endpoint */
#if 0
/* Endpoint enabled -> ISOC OUT transfer failed.*/
/* Disable endpoint.*/
/* CHTODO:: Core stucks here */
/*otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK);
otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK);
while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA)
;*/
;
#endif
/* Prepare transfer for next frame.*/
_usb_isr_invoke_out_cb(usbp, ep);
}
@ -1148,7 +1150,7 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
usbp->epc[ep]->out_maxsize;
rxsize = (pcnt * usbp->epc[ep]->out_maxsize + 3U) & 0xFFFFFFFCU;
/*Setting up transaction parameters in DOEPTSIZ.*/
/* Setting up transaction parameters in DOEPTSIZ.*/
usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) |
DOEPTSIZ_XFRSIZ(rxsize);

778
os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h
View File

File diff suppressed because it is too large Load Diff

1
os/hal/ports/STM32/LLD/RTCv3/hal_rtc_lld.h
View File

@ -249,7 +249,6 @@ typedef struct hal_rtc_wakeup {
/* Pointer to TAMPER registers block. */ \
TAMP_TypeDef *tamp
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/

1
os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h
View File

@ -319,7 +319,6 @@
#error "invalid DMA stream associated to SPI3 TX"
#endif
#endif /* STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX */
#if !defined(STM32_DMA_REQUIRED)

2
os/hal/ports/STM32/LLD/SPIv2/hal_spi_v2_lld.c
View File

@ -277,7 +277,7 @@ static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
* @return The operation status.
*/
static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream,
uint32_t txstream, uint32_t priority){
uint32_t txstream, uint32_t priority) {
spip->dmarx = dmaStreamAllocI(rxstream, priority,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,

4
os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c
View File

@ -396,7 +396,7 @@ static void spi_lld_serve_interrupt(SPIDriver *spip) {
* @return The operation status.
*/
static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream,
uint32_t txstream, uint32_t priority){
uint32_t txstream, uint32_t priority) {
spip->rx.dma = dmaStreamAllocI(rxstream, priority,
(stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
@ -428,7 +428,7 @@ static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream,
* @return The operation status.
*/
static msg_t spi_lld_get_bdma(SPIDriver *spip, uint32_t rxstream,
uint32_t txstream, uint32_t priority){
uint32_t txstream, uint32_t priority) {
spip->rx.bdma = bdmaStreamAllocI(rxstream, priority,
(stm32_bdmaisr_t)spi_lld_serve_bdma_rx_interrupt,

4
os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.h
View File

@ -137,7 +137,7 @@
#if !defined(STM32_HAS_TIM22)
#define STM32_HAS_TIM22 FALSE
#endif
/**/
/* End of checks to be removed.*/
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
@ -684,7 +684,6 @@ extern "C" {
/* Driver inline functions. */
/*===========================================================================*/
#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
/**
@ -786,7 +785,6 @@ static inline bool st_lld_is_alarm_active(void) {
*/
static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) {
STM32_ST_TIM->CCR[alarm] = (uint32_t)abstime;
STM32_ST_TIM->SR = 0;
STM32_ST_TIM->DIER |= (STM32_TIM_DIER_CC1IE << alarm);

306
os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.c
View File

@ -1,153 +1,153 @@
/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SYSTICKv2/hal_st_lld.h
* @brief ST Driver subsystem low level driver code.
*
* @addtogroup ST
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define ST_HANDLER STM32_RTC_ALARM_HANDLER
#define ST_NUMBER STM32_RTC_ALARM_NUMBER
#define STM32_ST_RTC_PREDIVA (STM32_RTCCLK / OSAL_ST_FREQUENCY)
/**
* Initialization for the RTC_PRER register.
*/
#define STM32_ST_RTC_PRER_BITS ((STM32_ST_RTC_PREDIVA - 1) << RTC_PRER_PREDIV_A_Pos)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if !defined(STM32_SYSTICK_SUPPRESS_ISR)
/**
* @brief Interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(ST_HANDLER) {
OSAL_IRQ_PROLOGUE();
st_lld_serve_interrupt();
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level ST driver initialization.
*
* @notapi
*/
void st_lld_init(void) {
/* Enabling the stop mode during debug for RTC.*/
DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_RTC_STOP;
/* Enable RTC kernel clock.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
/* Enable RTC APB bus clock.*/
rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true);
/* Disable RTC write protection.*/
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Disable all alarms and interrupts.*/
RTC->CR &= ~(RTC_CR_ALRAIE | RTC_CR_ALRBIE | RTC_CR_ALRAE | RTC_CR_ALRBE);
/* Enter initialization mode.*/
RTC->ICSR |= RTC_ICSR_INIT;
while ((RTC->ICSR & RTC_ICSR_INITF) == 0U) {
/* Waint for init flag.*/
}
/* Activate free running Binary mode.*/
RTC->ICSR |= RTC_ICSR_BIN_0;
/* Set RTC prescaler.*/
RTC->PRER = STM32_ST_RTC_PRER_BITS;
/* Exit initialization mode.*/
RTC->ICSR &= ~RTC_ICSR_INIT;
/* Wait for shadow reg. update.*/
while ((RTC->ICSR & RTC_ICSR_RSF) == 0U) {
// wait RSF flag
}
/* Compare all Sub Seconds 32 bits for RTC Alarm A.*/
RTC->ALRMASSR = (32UL << RTC_ALRMASSR_MASKSS_Pos);
/* EXTI enable.*/
extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI), EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT);
/* IRQ enable.*/
nvicEnableVector(ST_NUMBER, STM32_ST_IRQ_PRIORITY);
}
/**
* @brief IRQ handling code.
*/
void st_lld_serve_interrupt(void) {
uint32_t isr;
/* Get and clear the RTC interrupts. */
isr = RTC->MISR;
RTC->SCR = isr;
if ((isr & RTC_MISR_ALRAMF) != 0U) {
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
}
}
/** @} */
/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SYSTICKv2/hal_st_lld.h
* @brief ST Driver subsystem low level driver code.
*
* @addtogroup ST
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define ST_HANDLER STM32_RTC_ALARM_HANDLER
#define ST_NUMBER STM32_RTC_ALARM_NUMBER
#define STM32_ST_RTC_PREDIVA (STM32_RTCCLK / OSAL_ST_FREQUENCY)
/**
* Initialization for the RTC_PRER register.
*/
#define STM32_ST_RTC_PRER_BITS ((STM32_ST_RTC_PREDIVA - 1) << RTC_PRER_PREDIV_A_Pos)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if !defined(STM32_SYSTICK_SUPPRESS_ISR)
/**
* @brief Interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(ST_HANDLER) {
OSAL_IRQ_PROLOGUE();
st_lld_serve_interrupt();
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level ST driver initialization.
*
* @notapi
*/
void st_lld_init(void) {
/* Enabling the stop mode during debug for RTC.*/
DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_RTC_STOP;
/* Enable RTC kernel clock.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
/* Enable RTC APB bus clock.*/
rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true);
/* Disable RTC write protection.*/
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Disable all alarms and interrupts.*/
RTC->CR &= ~(RTC_CR_ALRAIE | RTC_CR_ALRBIE | RTC_CR_ALRAE | RTC_CR_ALRBE);
/* Enter initialization mode.*/
RTC->ICSR |= RTC_ICSR_INIT;
while ((RTC->ICSR & RTC_ICSR_INITF) == 0U) {
/* Waint for init flag.*/
}
/* Activate free running Binary mode.*/
RTC->ICSR |= RTC_ICSR_BIN_0;
/* Set RTC prescaler.*/
RTC->PRER = STM32_ST_RTC_PRER_BITS;
/* Exit initialization mode.*/
RTC->ICSR &= ~RTC_ICSR_INIT;
/* Wait for shadow reg. update.*/
while ((RTC->ICSR & RTC_ICSR_RSF) == 0U) {
/* Wait RSF flag.*/
}
/* Compare all Sub Seconds 32 bits for RTC Alarm A.*/
RTC->ALRMASSR = (32UL << RTC_ALRMASSR_MASKSS_Pos);
/* EXTI enable.*/
extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI), EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT);
/* IRQ enable.*/
nvicEnableVector(ST_NUMBER, STM32_ST_IRQ_PRIORITY);
}
/**
* @brief IRQ handling code.
*/
void st_lld_serve_interrupt(void) {
uint32_t isr;
/* Get and clear the RTC interrupts. */
isr = RTC->MISR;
RTC->SCR = isr;
if ((isr & RTC_MISR_ALRAMF) != 0U) {
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
}
}
/** @} */

436
os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.h
View File

@ -1,219 +1,217 @@
/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SYSTICKv2/hal_st_lld.h
* @brief RTC V3 based ST Driver subsystem low level driver header.
*
* @addtogroup ST
* @{
*/
#ifndef HAL_RTC_ST_LLD_H
#define HAL_RTC_ST_LLD_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief RTC SSR registry initial value.
*/
#define STM32_RTC_SSR_INIT_VALUE 0xFFFFFFFFUL
/* Requires services from the EXTI driver.*/
#if !defined(STM32_EXTI_REQUIRED)
#define STM32_EXTI_REQUIRED
#endif
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief SysTick timer IRQ priority.
*/
#if !defined(STM32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ST_IRQ_PRIORITY 8
#endif
/**
* @brief RTC binary mode attribute default value.
*/
#if !defined(STM32_RTC_HAS_BINARY_MODE) || defined(__DOXYGEN__)
#define STM32_RTC_HAS_BINARY_MODE FALSE
#endif
/**
* @brief RTC mixed mode attribute default value.
*/
#if !defined(STM32_RTC_HAS_MIXED_MODE) || defined(__DOXYGEN__)
#define STM32_RTC_HAS_MIXED_MODE FALSE
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if OSAL_ST_MODE != OSAL_ST_MODE_FREERUNNING
#error "ST based on RTC supports only free running mode. Change CH_CFG_ST_TIMEDELTA to enable tick-less mode."
#endif
#if STM32_HAS_RTC == FALSE
#error "RTC not present in the selected device"
#endif
#if HAL_USE_RTC == TRUE
#error "ST requires RTC but it is already used"
#endif
#if STM32_RTC_HAS_BINARY_MODE == FALSE
#error "RTC does not support binary mode"
#endif
#if (OSAL_ST_RESOLUTION != 32)
#error "ST based on RTC requires 32bits resolution. Set CH_CFG_ST_RESOLUTION to 32."
#endif
#if (STM32_RTCCLK % OSAL_ST_FREQUENCY) != 0
#error "the selected ST frequency is not obtainable because integer rounding"
#endif
#if (STM32_RTCCLK / OSAL_ST_FREQUENCY) > 128
#error "the selected ST frequency is not obtainable because RTC Prescaler A limits"
#endif
/**
* @brief ST Deep Sleep support attrubute.
*/
#define STM32_ST_DEEP_SLEEP_SUPPORT TRUE
/**
* @brief ST Alarms number.
*/
#define ST_LLD_NUM_ALARMS 1
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void st_lld_init(void);
void st_lld_serve_interrupt(void);
#ifdef __cplusplus
}
#endif
/*===========================================================================*/
/* Driver inline functions. */
/*===========================================================================*/
/**
* @brief Returns the time counter value.
*
* @return The counter value.
*
* @notapi
*/
static inline systime_t st_lld_get_counter(void) {
return (systime_t)(STM32_RTC_SSR_INIT_VALUE - RTC->SSR);
}
/**
* @brief Starts the alarm.
* @note Makes sure that no spurious alarms are triggered after
* this call.
*
* @param[in] abstime the time to be set for the first alarm
*
* @notapi
*/
static inline void st_lld_start_alarm(systime_t abstime) {
/* Disable RTC Alarm A.*/
RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE);
/* Set alarm time.*/
RTC->ALRABINR = (STM32_RTC_SSR_INIT_VALUE - (uint32_t)abstime);
/* Enabel RTC Alarm A.*/
RTC->CR |= (RTC_CR_ALRAE | RTC_CR_ALRAIE);
}
/**
* @brief Sets the alarm time.
*
* @param[in] abstime the time to be set for the next alarm
*
* @notapi
*/
static inline void st_lld_set_alarm(systime_t abstime) {
st_lld_start_alarm(abstime);
}
/**
* @brief Determines if the alarm is active.
*
* @return The alarm status.
* @retval false if the alarm is not active.
* @retval true is the alarm is active
*
* @notapi
*/
static inline bool st_lld_is_alarm_active(void) {
return (bool)((RTC->CR & RTC_CR_ALRAE) != 0);
}
/**
* @brief Stops the alarm interrupt.
*
* @notapi
*/
static inline void st_lld_stop_alarm(void) {
RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE);
}
/**
* @brief Returns the current alarm time.
*
* @return The currently set alarm time.
*
* @notapi
*/
static inline systime_t st_lld_get_alarm(void) {
return (systime_t)(STM32_RTC_SSR_INIT_VALUE - RTC->ALRABINR);
}
#endif /* HAL_RTC_ST_LLD_H */
/** @} */
/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SYSTICKv2/hal_st_lld.h
* @brief RTC V3 based ST Driver subsystem low level driver header.
*
* @addtogroup ST
* @{
*/
#ifndef HAL_RTC_ST_LLD_H
#define HAL_RTC_ST_LLD_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief RTC SSR registry initial value.
*/
#define STM32_RTC_SSR_INIT_VALUE 0xFFFFFFFFUL
/* Requires services from the EXTI driver.*/
#if !defined(STM32_EXTI_REQUIRED)
#define STM32_EXTI_REQUIRED
#endif
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief SysTick timer IRQ priority.
*/
#if !defined(STM32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ST_IRQ_PRIORITY 8
#endif
/**
* @brief RTC binary mode attribute default value.
*/
#if !defined(STM32_RTC_HAS_BINARY_MODE) || defined(__DOXYGEN__)
#define STM32_RTC_HAS_BINARY_MODE FALSE
#endif
/**
* @brief RTC mixed mode attribute default value.
*/
#if !defined(STM32_RTC_HAS_MIXED_MODE) || defined(__DOXYGEN__)
#define STM32_RTC_HAS_MIXED_MODE FALSE
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if OSAL_ST_MODE != OSAL_ST_MODE_FREERUNNING
#error "ST based on RTC supports only free running mode. Change CH_CFG_ST_TIMEDELTA to enable tick-less mode."
#endif
#if STM32_HAS_RTC == FALSE
#error "RTC not present in the selected device"
#endif
#if HAL_USE_RTC == TRUE
#error "ST requires RTC but it is already used"
#endif
#if STM32_RTC_HAS_BINARY_MODE == FALSE
#error "RTC does not support binary mode"
#endif
#if (OSAL_ST_RESOLUTION != 32)
#error "ST based on RTC requires 32bits resolution. Set CH_CFG_ST_RESOLUTION to 32."
#endif
#if (STM32_RTCCLK % OSAL_ST_FREQUENCY) != 0
#error "the selected ST frequency is not obtainable because integer rounding"
#endif
#if (STM32_RTCCLK / OSAL_ST_FREQUENCY) > 128
#error "the selected ST frequency is not obtainable because RTC Prescaler A limits"
#endif
/**
* @brief ST Deep Sleep support attrubute.
*/
#define STM32_ST_DEEP_SLEEP_SUPPORT TRUE
/**
* @brief ST Alarms number.
*/
#define ST_LLD_NUM_ALARMS 1
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void st_lld_init(void);
void st_lld_serve_interrupt(void);
#ifdef __cplusplus
}
#endif
/*===========================================================================*/
/* Driver inline functions. */
/*===========================================================================*/
/**
* @brief Returns the time counter value.
*
* @return The counter value.
*
* @notapi
*/
static inline systime_t st_lld_get_counter(void) {
return (systime_t)(STM32_RTC_SSR_INIT_VALUE - RTC->SSR);
}
/**
* @brief Starts the alarm.
* @note Makes sure that no spurious alarms are triggered after
* this call.
*
* @param[in] abstime the time to be set for the first alarm
*
* @notapi
*/
static inline void st_lld_start_alarm(systime_t abstime) {
/* Disable RTC Alarm A.*/
RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE);
/* Set alarm time.*/
RTC->ALRABINR = (STM32_RTC_SSR_INIT_VALUE - (uint32_t)abstime);
/* Enabel RTC Alarm A.*/
RTC->CR |= (RTC_CR_ALRAE | RTC_CR_ALRAIE);
}
/**
* @brief Sets the alarm time.
*
* @param[in] abstime the time to be set for the next alarm
*
* @notapi
*/
static inline void st_lld_set_alarm(systime_t abstime) {
st_lld_start_alarm(abstime);
}
/**
* @brief Determines if the alarm is active.
*
* @return The alarm status.
* @retval false if the alarm is not active.
* @retval true is the alarm is active
*
* @notapi
*/
static inline bool st_lld_is_alarm_active(void) {
return (bool)((RTC->CR & RTC_CR_ALRAE) != 0);
}
/**
* @brief Stops the alarm interrupt.
*
* @notapi
*/
static inline void st_lld_stop_alarm(void) {
RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE);
}
/**
* @brief Returns the current alarm time.
*
* @return The currently set alarm time.
*
* @notapi
*/
static inline systime_t st_lld_get_alarm(void) {
return (systime_t)(STM32_RTC_SSR_INIT_VALUE - RTC->ALRABINR);
}
#endif /* HAL_RTC_ST_LLD_H */
/** @} */

2
os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c
View File

@ -377,7 +377,6 @@ msg_t sio_lld_start(SIODriver *siop) {
siop->sync_rx = NULL;
siop->sync_tx = NULL;
siop->sync_txend = NULL;
// siop->events = 0U;
#endif
}
@ -387,7 +386,6 @@ msg_t sio_lld_start(SIODriver *siop) {
return HAL_RET_SUCCESS;
}
/**
* @brief Deactivates the SIO peripheral.
*

2
os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c
View File

@ -385,7 +385,6 @@ msg_t sio_lld_start(SIODriver *siop) {
siop->sync_rx = NULL;
siop->sync_tx = NULL;
siop->sync_txend = NULL;
// siop->events = 0U;
#endif
}
@ -395,7 +394,6 @@ msg_t sio_lld_start(SIODriver *siop) {
return HAL_RET_SUCCESS;
}
/**
* @brief Deactivates the SIO peripheral.
*

4
os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c
View File

@ -539,8 +539,8 @@ void usb_lld_reset(USBDriver *usbp) {
STM32_USB->BTABLE = BTABLE_ADDR;
STM32_USB->ISTR = 0;
STM32_USB->DADDR = DADDR_EF;
cntr = /*CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM |
CNTR_WKUPM | /*CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM;
cntr = /* CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM |
CNTR_WKUPM | /* CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM;
/* The SOF interrupt is only enabled if a callback is defined for
this service because it is an high rate source.*/
if (usbp->config->sof_cb != NULL)

1640
os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c
View File

File diff suppressed because it is too large Load Diff

316
os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h
View File

@ -1,158 +1,158 @@
/*
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.h
* @brief STM32F4xx Embedded Flash subsystem low level driver header.
*
* @addtogroup HAL_EFL
* @{
*/
#ifndef HAL_EFL_LLD_H
#define HAL_EFL_LLD_H
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name STM32F412/413 EFL driver configuration options
* @{
*/
/**
* @brief Suggested wait time during erase operations polling.
*/
#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define STM32_FLASH_WAIT_TIME_MS 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || defined(STM32F40_41xxx) \
|| defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size...
*
*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH1_SIZE 1536U
#define STM32_FLASH2_SIZE 1024U
#define STM32_FLASH1_SECTORS_TOTAL 16
#define STM32_FLASH2_SECTORS_TOTAL 12
#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size is:
* 1M for STM32F4x7/4x9 suffix G devices
* 2M for STM32F4x7/4x9 suffix I devices.
*
* For 1M devices SBM is organised as 16K x 4 + 64K + 128K x 7 sectors.
* For 1M devices DBM is organised as 16K x 4 + 64K + 128K x 3 sectors per bank.
*
* For 2M devices are organised as 16K x 4 + 64K + 128K x 7 sectors per bank.
*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
#define STM32_FLASH_SIZE_1M 1024U
#define STM32_FLASH_SIZE_2M 2048U
#define STM32_FLASH_SECTORS_TOTAL_1M_SBM 12
#define STM32_FLASH_SECTORS_TOTAL_1M_DBM 20
#define STM32_FLASH_SECTORS_TOTAL_2M 24
#else
#error "This EFL driver does not support the selected device"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/* A flash size declaration. */
typedef struct {
const flash_descriptor_t* desc;
} efl_lld_size_t;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Low level fields of the embedded flash driver structure.
*/
#define efl_lld_driver_fields \
/* Flash registers.*/ \
FLASH_TypeDef *flash; \
const flash_descriptor_t *descriptor;
/**
* @brief Low level fields of the embedded flash configuration structure.
*/
#define efl_lld_config_fields \
/* Dummy configuration, it is not needed.*/ \
uint32_t dummy
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern EFlashDriver EFLD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void efl_lld_init(void);
void efl_lld_start(EFlashDriver *eflp);
void efl_lld_stop(EFlashDriver *eflp);
const flash_descriptor_t *efl_lld_get_descriptor(void *instance);
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp);
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp);
flash_error_t efl_lld_start_erase_all(void *instance);
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector);
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec);
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EFL == TRUE */
#endif /* HAL_EFL_LLD_H */
/** @} */
/*
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.h
* @brief STM32F4xx Embedded Flash subsystem low level driver header.
*
* @addtogroup HAL_EFL
* @{
*/
#ifndef HAL_EFL_LLD_H
#define HAL_EFL_LLD_H
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name STM32F412/413 EFL driver configuration options
* @{
*/
/**
* @brief Suggested wait time during erase operations polling.
*/
#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define STM32_FLASH_WAIT_TIME_MS 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size...
*
*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH1_SIZE 1536U
#define STM32_FLASH2_SIZE 1024U
#define STM32_FLASH1_SECTORS_TOTAL 16
#define STM32_FLASH2_SECTORS_TOTAL 12
#elif defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size is:
* 1M for STM32F4x7/4x9 suffix G devices
* 2M for STM32F4x7/4x9 suffix I devices.
*
* For 1M devices SBM is organised as 16K x 4 + 64K + 128K x 7 sectors.
* For 1M devices DBM is organised as 16K x 4 + 64K + 128K x 3 sectors per bank.
*
* For 2M devices are organised as 16K x 4 + 64K + 128K x 7 sectors per bank.
*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
#define STM32_FLASH_SIZE_1M 1024U
#define STM32_FLASH_SIZE_2M 2048U
#define STM32_FLASH_SECTORS_TOTAL_1M_SBM 12
#define STM32_FLASH_SECTORS_TOTAL_1M_DBM 20
#define STM32_FLASH_SECTORS_TOTAL_2M 24
#else
#error "This EFL driver does not support the selected device"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/* A flash size declaration. */
typedef struct {
const flash_descriptor_t* desc;
} efl_lld_size_t;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Low level fields of the embedded flash driver structure.
*/
#define efl_lld_driver_fields \
/* Flash registers.*/ \
FLASH_TypeDef *flash; \
const flash_descriptor_t *descriptor;
/**
* @brief Low level fields of the embedded flash configuration structure.
*/
#define efl_lld_config_fields \
/* Dummy configuration, it is not needed.*/ \
uint32_t dummy
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern EFlashDriver EFLD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void efl_lld_init(void);
void efl_lld_start(EFlashDriver *eflp);
void efl_lld_stop(EFlashDriver *eflp);
const flash_descriptor_t *efl_lld_get_descriptor(void *instance);
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp);
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp);
flash_error_t efl_lld_start_erase_all(void *instance);
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector);
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec);
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EFL == TRUE */
#endif /* HAL_EFL_LLD_H */
/** @} */

4
os/hal/ports/STM32/STM32G0xx/hal_efl_lld.c
View File

@ -193,8 +193,8 @@ void efl_lld_init(void) {
/* Find the size of the flash and set descriptor reference. */
uint8_t i;
for (i = 0; i < (sizeof(efl_lld_flash_sizes) / sizeof(efl_lld_size_t)); i++) {
if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) {
EFLD1.descriptor = efl_lld_flash_sizes[i].desc;
if (efl_lld_flash_sizes[i].desc->size == stm32_flash_get_size()) {
EFLD1.descriptor = efl_lld_flash_sizes[i].desc;
if (stm32_flash_dual_bank(&EFLD1)) {
/* Point to the dual bank descriptor. */
EFLD1.descriptor++;

4
os/hal/ports/STM32/STM32G0xx/hal_efl_lld.h
View File

@ -51,8 +51,8 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(STM32G070xx) || defined(STM32G071xx) || \
defined(STM32G081xx) || \
#if defined(STM32G070xx) || defined(STM32G071xx) || \
defined(STM32G081xx) || \
defined(__DOXYGEN__)
/* Flash size register. */

12
os/hal/ports/STM32/STM32G0xx/hal_lld.c
View File

@ -354,7 +354,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
/* PLL VCO frequency.*/
pllvcoclk = (pllselclk / (halfreq_t)pllmdiv) * (halfreq_t)pllndiv;
if((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) {
if ((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) {
return true;
}
@ -363,7 +363,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLPEN) != 0U) {
pllpclk = pllvcoclk / pllpdiv;
if((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) {
if ((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) {
return true;
}
}
@ -373,7 +373,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLQEN) != 0U) {
pllqclk = pllvcoclk / pllqdiv;
if((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) {
if ((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) {
return true;
}
}
@ -383,14 +383,14 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLREN) != 0U) {
pllrclk = pllvcoclk / pllrdiv;
if((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) {
if ((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) {
return true;
}
}
}
/* SYSCLK frequency.*/
switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case RCC_CFGR_SW_HSI:
sysclk = hsisysclk;
break;
@ -427,7 +427,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* MCO clock.*/
switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
case STM32_MCOSEL_NOCLOCK:
mcoclk = 0U;
break;

2
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -288,7 +288,6 @@
#define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */
/** @} */
/**
* @name RCC_CCIPR2 register bits definitions
* @{
@ -1569,7 +1568,6 @@
#elif STM32_RNGSEL == STM32_RNGSEL_PLLQCLK
#define STM32_RNGCLK (hal_lld_get_clock_point(CLK_PLLQCLK) / STM32_RNGDIV_VALUE)
#else
#error "invalid source selected for RNG clock"
#endif

1
os/hal/ports/STM32/STM32G0xx/stm32_registry.h
View File

@ -95,7 +95,6 @@
#define STM32_RCC_HAS_PLL TRUE
#define STM32_RCC_PLL_HAS_P TRUE
/*#define STM32_RCC_PLL_HAS_Q TRUE*/ /* Varies, see below.*/
#define STM32_RCC_PLL_HAS_R TRUE
#define STM32_RCC_HAS_PLLSAI1 FALSE

12
os/hal/ports/STM32/STM32G4xx/hal_lld.c
View File

@ -364,7 +364,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
/* PLL VCO frequency.*/
pllvcoclk = (pllselclk / (halfreq_t)pllmdiv) * (halfreq_t)pllndiv;
if((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) {
if ((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) {
return true;
}
@ -384,7 +384,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLPEN) != 0U) {
pllpclk = pllvcoclk / pllpdiv;
if((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) {
if ((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) {
return true;
}
}
@ -394,7 +394,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLQEN) != 0U) {
pllqclk = pllvcoclk / pllqdiv;
if((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) {
if ((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) {
return true;
}
}
@ -404,14 +404,14 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLREN) != 0U) {
pllrclk = pllvcoclk / pllrdiv;
if((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) {
if ((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) {
return true;
}
}
}
/* SYSCLK frequency.*/
switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case RCC_CFGR_SW_HSI:
sysclk = hsi16clk;
break;
@ -451,7 +451,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* MCO clock.*/
switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
case STM32_MCOSEL_NOCLOCK:
mcoclk = 0U;
break;

3
os/hal/ports/STM32/STM32G4xx/stm32_registry.h
View File

@ -166,7 +166,6 @@
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
@ -381,7 +380,6 @@
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
@ -596,7 +594,6 @@
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2

16
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -1296,35 +1296,35 @@
#error "Using a wrong mcuconf.h file, STM32H7xx_MCUCONF not defined"
#endif
#if defined(STM32H750xx)&& !defined(STM32H750_MCUCONF)
#if defined(STM32H750xx) && !defined(STM32H750_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H750_MCUCONF not defined"
#endif
#if defined(STM32H742xx)&& !defined(STM32H742_MCUCONF)
#if defined(STM32H742xx) && !defined(STM32H742_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H742_MCUCONF not defined"
#endif
#if defined(STM32H743xx)&& !defined(STM32H743_MCUCONF)
#if defined(STM32H743xx) && !defined(STM32H743_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H743_MCUCONF not defined"
#endif
#if defined(STM32H753xx)&& !defined(STM32H753_MCUCONF)
#if defined(STM32H753xx) && !defined(STM32H753_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H753_MCUCONF not defined"
#endif
#if defined(STM32H745xx)&& !defined(STM32H745_MCUCONF)
#if defined(STM32H745xx) && !defined(STM32H745_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H745_MCUCONF not defined"
#endif
#if defined(STM32H755xx)&& !defined(STM32H755_MCUCONF)
#if defined(STM32H755xx) && !defined(STM32H755_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H755_MCUCONF not defined"
#endif
#if defined(STM32H747xx)&& !defined(STM32H747_MCUCONF)
#if defined(STM32H747xx) && !defined(STM32H747_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H747_MCUCONF not defined"
#endif
#if defined(STM32H757xx)&& !defined(STM32H757_MCUCONF)
#if defined(STM32H757xx) && !defined(STM32H757_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H757_MCUCONF not defined"
#endif

1
os/hal/ports/STM32/STM32L0xx/stm32_registry.h
View File

@ -574,7 +574,6 @@
#define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE
/*===========================================================================*/
/* STM32L052xx, STM32L062xx, STM32L053xx, STM32L063xx. */
/*===========================================================================*/

1262
os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.c
View File

File diff suppressed because it is too large Load Diff

318
os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.h
View File

@ -1,159 +1,159 @@
/*
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.h
* @brief STM32L4+ Embedded Flash subsystem low level driver header.
*
* @addtogroup HAL_EFL
* @{
*/
#ifndef HAL_EFL_LLD_H
#define HAL_EFL_LLD_H
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name STM32L4xx configuration options
* @{
*/
/**
* @brief Suggested wait time during erase operations polling.
*/
#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define STM32_FLASH_WAIT_TIME_MS 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || \
defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
defined(STM32L4S7xx) || defined(STM32L4S9xx) || defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF75E0
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size is:
* 1M for STM32L4+ suffix G devices
* 2M for STM32L4+ suffix I devices.
*
* For 1M devices SBM is organised as 128 x 8K pages.
* For 1M devices DBM is organised as 128 x 4K pages per bank.
*
* For 2M devices SBM is organised as 256 x 8K pages.
* For 2M devices DBM is organised as 256 x 4K pages per bank.
*/
#define STM32_FLASH_SIZE_1M 1024U
#define STM32_FLASH_SIZE_2M 2048U
#define STM32_FLASH_SECTORS_TOTAL_1M 128
#define STM32_FLASH_SECTORS_TOTAL_2M 256
/* Single bank mode bank 1 for 1M device.*/
#define STM32_FLASH_SECTOR_SIZE_1M ((STM32_FLASH_SIZE_1M \
* STM32_FLASH_SIZE_SCALE) \
/ STM32_FLASH_SECTORS_TOTAL_1M)
/* Dual bank mode banks 1 & 2 for 1M device.*/
#define STM32_FLASH_DUAL_SECTOR_SIZE_1M (STM32_FLASH_SECTOR_SIZE_1M / 2)
/* Single bank mode bank 1 for 2M device.*/
#define STM32_FLASH_SECTOR_SIZE_2M ((STM32_FLASH_SIZE_2M \
* STM32_FLASH_SIZE_SCALE) \
/ STM32_FLASH_SECTORS_TOTAL_2M)
/* Dual bank mode banks 1 & 2 for 2M device.*/
#define STM32_FLASH_DUAL_SECTOR_SIZE_2M (STM32_FLASH_SECTOR_SIZE_2M / 2)
#else
#error "This EFL driver does not support the selected device"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/* A flash size declaration. */
typedef struct {
const flash_descriptor_t* desc;
} efl_lld_size_t;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Low level fields of the embedded flash driver structure.
*/
#define efl_lld_driver_fields \
/* Flash registers.*/ \
FLASH_TypeDef *flash; \
const flash_descriptor_t *descriptor;
/**
* @brief Low level fields of the embedded flash configuration structure.
*/
#define efl_lld_config_fields \
/* Dummy configuration, it is not needed.*/ \
uint32_t dummy
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern EFlashDriver EFLD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void efl_lld_init(void);
void efl_lld_start(EFlashDriver *eflp);
void efl_lld_stop(EFlashDriver *eflp);
const flash_descriptor_t *efl_lld_get_descriptor(void *instance);
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp);
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp);
flash_error_t efl_lld_start_erase_all(void *instance);
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector);
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec);
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EFL == TRUE */
#endif /* HAL_EFL_LLD_H */
/** @} */
/*
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.h
* @brief STM32L4+ Embedded Flash subsystem low level driver header.
*
* @addtogroup HAL_EFL
* @{
*/
#ifndef HAL_EFL_LLD_H
#define HAL_EFL_LLD_H
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name STM32L4xx configuration options
* @{
*/
/**
* @brief Suggested wait time during erase operations polling.
*/
#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define STM32_FLASH_WAIT_TIME_MS 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || \
defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
defined(STM32L4S7xx) || defined(STM32L4S9xx) || defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF75E0
#define STM32_FLASH_SIZE_SCALE 1024U
/*
* Device flash size is:
* 1M for STM32L4+ suffix G devices
* 2M for STM32L4+ suffix I devices.
*
* For 1M devices SBM is organised as 128 x 8K pages.
* For 1M devices DBM is organised as 128 x 4K pages per bank.
*
* For 2M devices SBM is organised as 256 x 8K pages.
* For 2M devices DBM is organised as 256 x 4K pages per bank.
*/
#define STM32_FLASH_SIZE_1M 1024U
#define STM32_FLASH_SIZE_2M 2048U
#define STM32_FLASH_SECTORS_TOTAL_1M 128
#define STM32_FLASH_SECTORS_TOTAL_2M 256
/* Single bank mode bank 1 for 1M device.*/
#define STM32_FLASH_SECTOR_SIZE_1M ((STM32_FLASH_SIZE_1M \
* STM32_FLASH_SIZE_SCALE) \
/ STM32_FLASH_SECTORS_TOTAL_1M)
/* Dual bank mode banks 1 & 2 for 1M device.*/
#define STM32_FLASH_DUAL_SECTOR_SIZE_1M (STM32_FLASH_SECTOR_SIZE_1M / 2)
/* Single bank mode bank 1 for 2M device.*/
#define STM32_FLASH_SECTOR_SIZE_2M ((STM32_FLASH_SIZE_2M \
* STM32_FLASH_SIZE_SCALE) \
/ STM32_FLASH_SECTORS_TOTAL_2M)
/* Dual bank mode banks 1 & 2 for 2M device.*/
#define STM32_FLASH_DUAL_SECTOR_SIZE_2M (STM32_FLASH_SECTOR_SIZE_2M / 2)
#else
#error "This EFL driver does not support the selected device"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/* A flash size declaration. */
typedef struct {
const flash_descriptor_t* desc;
} efl_lld_size_t;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Low level fields of the embedded flash driver structure.
*/
#define efl_lld_driver_fields \
/* Flash registers.*/ \
FLASH_TypeDef *flash; \
const flash_descriptor_t *descriptor;
/**
* @brief Low level fields of the embedded flash configuration structure.
*/
#define efl_lld_config_fields \
/* Dummy configuration, it is not needed.*/ \
uint32_t dummy
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern EFlashDriver EFLD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void efl_lld_init(void);
void efl_lld_start(EFlashDriver *eflp);
void efl_lld_stop(EFlashDriver *eflp);
const flash_descriptor_t *efl_lld_get_descriptor(void *instance);
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp);
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp);
flash_error_t efl_lld_start_erase_all(void *instance);
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector);
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec);
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EFL == TRUE */
#endif /* HAL_EFL_LLD_H */
/** @} */

12
os/hal/ports/STM32/STM32L4xx+/hal_lld.c
View File

@ -348,7 +348,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
/* PLL VCO frequency.*/
vcoclk = (selclk / (halfreq_t)mdiv) * (halfreq_t)ndiv;
if((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) {
if ((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) {
return true;
}
@ -368,7 +368,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLPEN) != 0U) {
pclk = vcoclk / pdiv;
if((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) {
if ((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) {
return true;
}
}
@ -378,7 +378,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLQEN) != 0U) {
qclk = vcoclk / qdiv;
if((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) {
if ((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) {
return true;
}
}
@ -388,7 +388,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLREN) != 0U) {
rclk = vcoclk / rdiv;
if((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) {
if ((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) {
return true;
}
}
@ -502,7 +502,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* SYSCLK frequency.*/
switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case RCC_CFGR_SW_MSI:
sysclk = msiclk;
break;
@ -545,7 +545,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* MCO clock.*/
switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
case STM32_MCOSEL_NOCLOCK:
mcoclk = 0U;
break;

1
os/hal/ports/STM32/STM32L4xx+/stm32_isr.h
View File

@ -160,7 +160,6 @@
#define STM32_I2C4_ERROR_NUMBER 83
#define STM32_I2C4_EVENT_NUMBER 84
/*
* OCTOSPI unit.
*/

2
os/hal/ports/STM32/STM32L5xx/stm32_rcc.h
View File

@ -525,7 +525,7 @@
*
* @api
*/
#define rccResetGTZC() /*rccResetAHB1(RCC_AHB1RST_GTZCRST)*/
#define rccResetGTZC() /* Disabled rccResetAHB1(RCC_AHB1RST_GTZCRST) */
/** @} */
/**

1
os/hal/ports/STM32/STM32MP1xx/hal_lld.h
View File

@ -238,7 +238,6 @@
#define STM32_HSI_ENABLED TRUE
#endif
/**
* @brief HSI divider setting.
* @note This initialization is performed only if TZEN=0 or MCKPROT=0

486
os/hal/ports/STM32/STM32WBxx/hal_lld.c
View File

@ -1,243 +1,243 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Ilya Kharin.
*/
/**
* @file STM32WBxx/hal_lld.c
* @brief STM32WBxx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief CMSIS system core clock variable.
*/
uint32_t SystemCoreClock = STM32_HCLK;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Safe setting of flash ACR register.
*
* @param[in] acr value for the ACR register
*/
__STATIC_INLINE void flash_set_acr(uint32_t acr) {
FLASH->ACR = acr;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) {
/* Waiting for flash wait states setup.*/
}
}
/**
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
*/
__STATIC_INLINE void hal_lld_set_static_pwr(void) {
/* Static PWR configurations.*/
PWR->CR3 = STM32_PWR_CR3;
PWR->CR4 = STM32_PWR_CR4;
PWR->PUCRA = STM32_PWR_PUCRA;
PWR->PDCRA = STM32_PWR_PDCRA;
PWR->PUCRB = STM32_PWR_PUCRB;
PWR->PDCRB = STM32_PWR_PDCRB;
PWR->PUCRC = STM32_PWR_PUCRC;
PWR->PDCRC = STM32_PWR_PDCRC;
PWR->PUCRD = STM32_PWR_PUCRD;
PWR->PDCRD = STM32_PWR_PDCRD;
PWR->PUCRE = STM32_PWR_PUCRE;
PWR->PDCRE = STM32_PWR_PDCRE;
PWR->PUCRH = STM32_PWR_PUCRH;
PWR->PDCRH = STM32_PWR_PDCRH;
}
/**
* @brief Initializes static muxes and dividers.
*/
__STATIC_INLINE void hal_lld_set_static_clocks(void) {
uint32_t ccipr;
/* Clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Waiting for PPRE2, PPRE1 and HPRE applied. */
while ((RCC->CFGR & (RCC_CFGR_PPRE2F_Msk | RCC_CFGR_PPRE1F_Msk |
RCC_CFGR_HPREF_Msk)) !=
(RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF))
;
/* CCIPR2 register initialization, note, must take care of the _OFF
pseudo settings.*/
ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_CLK48SEL |
STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C1SEL |
STM32_USART1SEL | STM32_LPUART1SEL;
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
ccipr |= STM32_SAI1SEL;
#endif
RCC->CCIPR = ccipr;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* NVIC initialization.*/
nvicInit();
/* IRQ subsystem initialization.*/
irqInit();
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK);
#else
PWR->CR2 = 0;
#endif /* STM32_PVD_ENABLE */
/* Enabling independent VDDUSB.*/
#if HAL_USE_USB
PWR->CR2 |= PWR_CR2_USV;
#endif /* HAL_USE_USB */
}
/**
* @brief STM32WBxx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~0);
rccResetAHB2(~STM32_GPIO_EN_MASK);
rccResetAHB3(~0);
rccResetAPB1R1(~0);
rccResetAPB1R2(~0);
rccResetAPB2(~0);
/* Flash setup for selected MSI speed setting.*/
flash_set_acr(FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
STM32_MSI_FLASHBITS);
/* Static PWR configurations.*/
hal_lld_set_static_pwr();
/* Core voltage setup, backup domain access enabled and left open.*/
PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
/* Additional PWR configurations.*/
PWR->CR2 = STM32_PWR_CR2;
/* Wait until regulator is stable. */
while ((PWR->SR2 & PWR_SR2_VOSF) != 0)
;
/* MSI clock reset.*/
msi_reset();
/* Backup domain reset.*/
bd_reset();
/* Clocks setup.*/
lse_init();
lsi_init();
msi_init();
hsi16_init();
hsi48_init();
hse32_init();
/* Backup domain initializations.*/
bd_init();
/* Static clocks setup.*/
hal_lld_set_static_clocks();
/* PLLs activation, if required.*/
pll_init();
pllsai1_init();
/* Extended clock recovery register (HCLK2, HCLK4, HCLK5). */
RCC->EXTCFGR = STM32_RFCSSSEL | STM32_C2HPRE | STM32_SHDHPRE;
/* Waiting for C2HPRE and SHDHPRE. */
while ((RCC->EXTCFGR & (RCC_EXTCFGR_C2HPREF_Msk |
RCC_EXTCFGR_SHDHPREF_Msk)) !=
(RCC_EXTCFGR_C2HPREF | RCC_EXTCFGR_SHDHPREF))
;
/* Set flash WS's for SYSCLK source */
if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS);
}
/* Switching to the configured SYSCLK source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
/* Wait until SYSCLK is stable.*/
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {
flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS);
}
#endif /* STM32_NO_INIT */
}
/** @} */
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Ilya Kharin.
*/
/**
* @file STM32WBxx/hal_lld.c
* @brief STM32WBxx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief CMSIS system core clock variable.
*/
uint32_t SystemCoreClock = STM32_HCLK;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Safe setting of flash ACR register.
*
* @param[in] acr value for the ACR register
*/
__STATIC_INLINE void flash_set_acr(uint32_t acr) {
FLASH->ACR = acr;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) {
/* Waiting for flash wait states setup.*/
}
}
/**
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
*/
__STATIC_INLINE void hal_lld_set_static_pwr(void) {
/* Static PWR configurations.*/
PWR->CR3 = STM32_PWR_CR3;
PWR->CR4 = STM32_PWR_CR4;
PWR->PUCRA = STM32_PWR_PUCRA;
PWR->PDCRA = STM32_PWR_PDCRA;
PWR->PUCRB = STM32_PWR_PUCRB;
PWR->PDCRB = STM32_PWR_PDCRB;
PWR->PUCRC = STM32_PWR_PUCRC;
PWR->PDCRC = STM32_PWR_PDCRC;
PWR->PUCRD = STM32_PWR_PUCRD;
PWR->PDCRD = STM32_PWR_PDCRD;
PWR->PUCRE = STM32_PWR_PUCRE;
PWR->PDCRE = STM32_PWR_PDCRE;
PWR->PUCRH = STM32_PWR_PUCRH;
PWR->PDCRH = STM32_PWR_PDCRH;
}
/**
* @brief Initializes static muxes and dividers.
*/
__STATIC_INLINE void hal_lld_set_static_clocks(void) {
uint32_t ccipr;
/* Clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Waiting for PPRE2, PPRE1 and HPRE applied. */
while ((RCC->CFGR & (RCC_CFGR_PPRE2F_Msk | RCC_CFGR_PPRE1F_Msk |
RCC_CFGR_HPREF_Msk)) !=
(RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF))
;
/* CCIPR2 register initialization, note, must take care of the _OFF
pseudo settings.*/
ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_CLK48SEL |
STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C1SEL |
STM32_USART1SEL | STM32_LPUART1SEL;
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
ccipr |= STM32_SAI1SEL;
#endif
RCC->CCIPR = ccipr;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* NVIC initialization.*/
nvicInit();
/* IRQ subsystem initialization.*/
irqInit();
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK);
#else
PWR->CR2 = 0;
#endif /* STM32_PVD_ENABLE */
/* Enabling independent VDDUSB.*/
#if HAL_USE_USB
PWR->CR2 |= PWR_CR2_USV;
#endif /* HAL_USE_USB */
}
/**
* @brief STM32WBxx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~0);
rccResetAHB2(~STM32_GPIO_EN_MASK);
rccResetAHB3(~0);
rccResetAPB1R1(~0);
rccResetAPB1R2(~0);
rccResetAPB2(~0);
/* Flash setup for selected MSI speed setting.*/
flash_set_acr(FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
STM32_MSI_FLASHBITS);
/* Static PWR configurations.*/
hal_lld_set_static_pwr();
/* Core voltage setup, backup domain access enabled and left open.*/
PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
/* Additional PWR configurations.*/
PWR->CR2 = STM32_PWR_CR2;
/* Wait until regulator is stable. */
while ((PWR->SR2 & PWR_SR2_VOSF) != 0)
;
/* MSI clock reset.*/
msi_reset();
/* Backup domain reset.*/
bd_reset();
/* Clocks setup.*/
lse_init();
lsi_init();
msi_init();
hsi16_init();
hsi48_init();
hse32_init();
/* Backup domain initializations.*/
bd_init();
/* Static clocks setup.*/
hal_lld_set_static_clocks();
/* PLLs activation, if required.*/
pll_init();
pllsai1_init();
/* Extended clock recovery register (HCLK2, HCLK4, HCLK5). */
RCC->EXTCFGR = STM32_RFCSSSEL | STM32_C2HPRE | STM32_SHDHPRE;
/* Waiting for C2HPRE and SHDHPRE. */
while ((RCC->EXTCFGR & (RCC_EXTCFGR_C2HPREF_Msk |
RCC_EXTCFGR_SHDHPREF_Msk)) !=
(RCC_EXTCFGR_C2HPREF | RCC_EXTCFGR_SHDHPREF))
;
/* Set flash WS's for SYSCLK source */
if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS);
}
/* Switching to the configured SYSCLK source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
/* Wait until SYSCLK is stable.*/
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {
flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS);
}
#endif /* STM32_NO_INIT */
}
/** @} */

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os/hal/ports/STM32/STM32WBxx/hal_lld.h
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218
os/hal/ports/STM32/STM32WBxx/stm32_dmamux.h
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@ -1,109 +1,109 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Ilya Kharin.
*/
/**
* @file STM32WBxx/stm32_dmamux.h
* @brief STM32WBxx DMAMUX handler header.
*
* @addtogroup STM32WBxxp_DMAMUX
* @{
*/
#ifndef STM32_DMAMUX_H
#define STM32_DMAMUX_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name DMAMUX1 request sources
* @{
*/
#define STM32_DMAMUX1_REQ_GEN0 1
#define STM32_DMAMUX1_REQ_GEN1 2
#define STM32_DMAMUX1_REQ_GEN2 3
#define STM32_DMAMUX1_REQ_GEN3 4
#define STM32_DMAMUX1_ADC1 5
#define STM32_DMAMUX1_SPI1_RX 6
#define STM32_DMAMUX1_SPI1_TX 7
#define STM32_DMAMUX1_SPI2_RX 8
#define STM32_DMAMUX1_SPI2_TX 9
#define STM32_DMAMUX1_I2C1_RX 10
#define STM32_DMAMUX1_I2C1_TX 11
#define STM32_DMAMUX1_I2C3_RX 12
#define STM32_DMAMUX1_I2C3_TX 13
#define STM32_DMAMUX1_USART1_RX 14
#define STM32_DMAMUX1_USART1_TX 15
#define STM32_DMAMUX1_LPUART1_RX 16
#define STM32_DMAMUX1_LPUART1_TX 17
#define STM32_DMAMUX1_SAI1_A 18
#define STM32_DMAMUX1_SAI1_B 19
#define STM32_DMAMUX1_QUADSPI 20
#define STM32_DMAMUX1_TIM1_CH1 21
#define STM32_DMAMUX1_TIM1_CH2 22
#define STM32_DMAMUX1_TIM1_CH3 23
#define STM32_DMAMUX1_TIM1_CH4 24
#define STM32_DMAMUX1_TIM1_UP 25
#define STM32_DMAMUX1_TIM1_TRIG 26
#define STM32_DMAMUX1_TIM1_COM 27
#define STM32_DMAMUX1_TIM2_CH1 28
#define STM32_DMAMUX1_TIM2_CH2 29
#define STM32_DMAMUX1_TIM2_CH3 30
#define STM32_DMAMUX1_TIM2_CH4 31
#define STM32_DMAMUX1_TIM2_UP 32
#define STM32_DMAMUX1_TIM16_CH1 33
#define STM32_DMAMUX1_TIM16_UP 34
#define STM32_DMAMUX1_TIM17_CH1 35
#define STM32_DMAMUX1_TIM17_UP 36
#define STM32_DMAMUX1_CRYP_IN 37
#define STM32_DMAMUX1_CRYP_OUT 38
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32_DMAMUX_H */
/** @} */
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Ilya Kharin.
*/
/**
* @file STM32WBxx/stm32_dmamux.h
* @brief STM32WBxx DMAMUX handler header.
*
* @addtogroup STM32WBxxp_DMAMUX
* @{
*/
#ifndef STM32_DMAMUX_H
#define STM32_DMAMUX_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name DMAMUX1 request sources
* @{
*/
#define STM32_DMAMUX1_REQ_GEN0 1
#define STM32_DMAMUX1_REQ_GEN1 2
#define STM32_DMAMUX1_REQ_GEN2 3
#define STM32_DMAMUX1_REQ_GEN3 4
#define STM32_DMAMUX1_ADC1 5
#define STM32_DMAMUX1_SPI1_RX 6
#define STM32_DMAMUX1_SPI1_TX 7
#define STM32_DMAMUX1_SPI2_RX 8
#define STM32_DMAMUX1_SPI2_TX 9
#define STM32_DMAMUX1_I2C1_RX 10
#define STM32_DMAMUX1_I2C1_TX 11
#define STM32_DMAMUX1_I2C3_RX 12
#define STM32_DMAMUX1_I2C3_TX 13
#define STM32_DMAMUX1_USART1_RX 14
#define STM32_DMAMUX1_USART1_TX 15
#define STM32_DMAMUX1_LPUART1_RX 16
#define STM32_DMAMUX1_LPUART1_TX 17
#define STM32_DMAMUX1_SAI1_A 18
#define STM32_DMAMUX1_SAI1_B 19
#define STM32_DMAMUX1_QUADSPI 20
#define STM32_DMAMUX1_TIM1_CH1 21
#define STM32_DMAMUX1_TIM1_CH2 22
#define STM32_DMAMUX1_TIM1_CH3 23
#define STM32_DMAMUX1_TIM1_CH4 24
#define STM32_DMAMUX1_TIM1_UP 25
#define STM32_DMAMUX1_TIM1_TRIG 26
#define STM32_DMAMUX1_TIM1_COM 27
#define STM32_DMAMUX1_TIM2_CH1 28
#define STM32_DMAMUX1_TIM2_CH2 29
#define STM32_DMAMUX1_TIM2_CH3 30
#define STM32_DMAMUX1_TIM2_CH4 31
#define STM32_DMAMUX1_TIM2_UP 32
#define STM32_DMAMUX1_TIM16_CH1 33
#define STM32_DMAMUX1_TIM16_UP 34
#define STM32_DMAMUX1_TIM17_CH1 35
#define STM32_DMAMUX1_TIM17_UP 36
#define STM32_DMAMUX1_CRYP_IN 37
#define STM32_DMAMUX1_CRYP_OUT 38
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32_DMAMUX_H */
/** @} */

268
os/hal/ports/STM32/STM32WBxx/stm32_isr.c
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@ -1,134 +1,134 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Ilya Kharin.
*/
/**
* @file STM32WBxx/stm32_isr.h
* @brief STM32WBxx ISR handler code.
*
* @addtogroup STM32WBxx_ISR
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#define exti_serve_irq(pr, channel) { \
\
if ((pr) & (1U << (channel))) { \
_pal_isr_code(channel); \
} \
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#include "stm32_exti0.inc"
#include "stm32_exti1.inc"
#include "stm32_exti2.inc"
#include "stm32_exti3.inc"
#include "stm32_exti4.inc"
#include "stm32_exti5_9.inc"
#include "stm32_exti10_15.inc"
#include "stm32_exti16-31-33.inc"
#include "stm32_exti17.inc"
#include "stm32_exti18.inc"
#include "stm32_exti19.inc"
#include "stm32_exti20_21.inc"
#include "stm32_usart1.inc"
#include "stm32_lpuart1.inc"
#include "stm32_tim1_16_17.inc"
#include "stm32_tim2.inc"
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables IRQ sources.
*
* @notapi
*/
void irqInit(void) {
exti0_irq_init();
exti1_irq_init();
exti2_irq_init();
exti3_irq_init();
exti4_irq_init();
exti5_9_irq_init();
exti10_15_irq_init();
exti16_exti31_exti33_irq_init();
exti17_irq_init();
exti18_irq_init();
exti19_irq_init();
exti20_exti21_irq_init();
tim1_tim16_tim17_irq_init();
tim2_irq_init();
usart1_irq_init();
lpuart1_irq_init();
}
/**
* @brief Disables IRQ sources.
*
* @notapi
*/
void irqDeinit(void) {
exti0_irq_deinit();
exti1_irq_deinit();
exti2_irq_deinit();
exti3_irq_deinit();
exti4_irq_deinit();
exti5_9_irq_deinit();
exti10_15_irq_deinit();
exti16_exti31_exti33_irq_deinit();
exti17_irq_deinit();
exti18_irq_deinit();
exti19_irq_deinit();
exti20_exti21_irq_deinit();
tim1_tim16_tim17_irq_deinit();
tim2_irq_deinit();
usart1_irq_deinit();
lpuart1_irq_deinit();
}
/** @} */
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Ilya Kharin.
*/
/**
* @file STM32WBxx/stm32_isr.h
* @brief STM32WBxx ISR handler code.
*
* @addtogroup STM32WBxx_ISR
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#define exti_serve_irq(pr, channel) { \
\
if ((pr) & (1U << (channel))) { \
_pal_isr_code(channel); \
} \
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#include "stm32_exti0.inc"
#include "stm32_exti1.inc"
#include "stm32_exti2.inc"
#include "stm32_exti3.inc"
#include "stm32_exti4.inc"
#include "stm32_exti5_9.inc"
#include "stm32_exti10_15.inc"
#include "stm32_exti16-31-33.inc"
#include "stm32_exti17.inc"
#include "stm32_exti18.inc"
#include "stm32_exti19.inc"
#include "stm32_exti20_21.inc"
#include "stm32_usart1.inc"
#include "stm32_lpuart1.inc"
#include "stm32_tim1_16_17.inc"
#include "stm32_tim2.inc"
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables IRQ sources.
*
* @notapi
*/
void irqInit(void) {
exti0_irq_init();
exti1_irq_init();
exti2_irq_init();
exti3_irq_init();
exti4_irq_init();
exti5_9_irq_init();
exti10_15_irq_init();
exti16_exti31_exti33_irq_init();
exti17_irq_init();
exti18_irq_init();
exti19_irq_init();
exti20_exti21_irq_init();
tim1_tim16_tim17_irq_init();
tim2_irq_init();
usart1_irq_init();
lpuart1_irq_init();
}
/**
* @brief Disables IRQ sources.
*
* @notapi
*/
void irqDeinit(void) {
exti0_irq_deinit();
exti1_irq_deinit();
exti2_irq_deinit();
exti3_irq_deinit();
exti4_irq_deinit();
exti5_9_irq_deinit();
exti10_15_irq_deinit();
exti16_exti31_exti33_irq_deinit();
exti17_irq_deinit();
exti18_irq_deinit();
exti19_irq_deinit();
exti20_exti21_irq_deinit();
tim1_tim16_tim17_irq_deinit();
tim2_irq_deinit();
usart1_irq_deinit();
lpuart1_irq_deinit();
}
/** @} */

412
os/hal/ports/STM32/STM32WBxx/stm32_isr.h
View File

@ -1,206 +1,206 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Ilya Kharin.
*/
/**
* @file STM32WBxx/stm32_isr.h
* @brief STM32WBxx ISR handler header.
*
* @addtogroup SRM32WBxx_ISR
* @{
*/
#ifndef STM32_ISR_H
#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISRs suppressed in standard drivers
* @{
*/
#define STM32_TIM1_SUPPRESS_ISR
#define STM32_TIM2_SUPPRESS_ISR
#define STM32_TIM16_SUPPRESS_ISR
#define STM32_TIM17_SUPPRESS_ISR
#define STM32_USART1_SUPPRESS_ISR
#define STM32_LPUART1_SUPPRESS_ISR
/** @} */
/**
* @name ISR names and numbers
* @{
*/
/*
* ADC unit.
*/
#define STM32_ADC1_HANDLER Vector88
#define STM32_ADC1_NUMBER 18
/*
* DMA unit.
*/
#define STM32_DMA1_CH1_HANDLER Vector6C
#define STM32_DMA1_CH2_HANDLER Vector70
#define STM32_DMA1_CH3_HANDLER Vector74
#define STM32_DMA1_CH4_HANDLER Vector78
#define STM32_DMA1_CH5_HANDLER Vector7C
#define STM32_DMA1_CH6_HANDLER Vector80
#define STM32_DMA1_CH7_HANDLER Vector84
#define STM32_DMA2_CH1_HANDLER Vector11C
#define STM32_DMA2_CH2_HANDLER Vector120
#define STM32_DMA2_CH3_HANDLER Vector124
#define STM32_DMA2_CH4_HANDLER Vector128
#define STM32_DMA2_CH5_HANDLER Vector12C
#define STM32_DMA2_CH6_HANDLER Vector130
#define STM32_DMA2_CH7_HANDLER Vector134
#define STM32_DMA1_CH1_NUMBER 11
#define STM32_DMA1_CH2_NUMBER 12
#define STM32_DMA1_CH3_NUMBER 13
#define STM32_DMA1_CH4_NUMBER 14
#define STM32_DMA1_CH5_NUMBER 15
#define STM32_DMA1_CH6_NUMBER 16
#define STM32_DMA1_CH7_NUMBER 17
#define STM32_DMA2_CH1_NUMBER 55
#define STM32_DMA2_CH2_NUMBER 56
#define STM32_DMA2_CH3_NUMBER 57
#define STM32_DMA2_CH4_NUMBER 58
#define STM32_DMA2_CH5_NUMBER 59
#define STM32_DMA2_CH6_NUMBER 60
#define STM32_DMA2_CH7_NUMBER 61
/*
* EXTI unit.
*/
#define STM32_EXTI0_HANDLER Vector58
#define STM32_EXTI1_HANDLER Vector5C
#define STM32_EXTI2_HANDLER Vector60
#define STM32_EXTI3_HANDLER Vector64
#define STM32_EXTI4_HANDLER Vector68
#define STM32_EXTI5_9_HANDLER Vector9C
#define STM32_EXTI10_15_HANDLER VectorE0
#define STM32_EXTI16_31_33_HANDLER Vector44 /* PVD PVM0 PVM2 */
#define STM32_EXTI17_HANDLER VectorE4 /* RTC ALARM */
#define STM32_EXTI18_HANDLER Vector48 /* RTC TAMP CSS */
#define STM32_EXTI19_HANDLER Vector4C /* RTC WAKEUP */
#define STM32_EXTI20_21_HANDLER Vector98 /* COMP2 COMP1 */
#define STM32_EXTI0_NUMBER 6
#define STM32_EXTI1_NUMBER 7
#define STM32_EXTI2_NUMBER 8
#define STM32_EXTI3_NUMBER 9
#define STM32_EXTI4_NUMBER 10
#define STM32_EXTI5_9_NUMBER 23
#define STM32_EXTI10_15_NUMBER 40
#define STM32_EXTI16_31_33_NUMBER 1
#define STM32_EXTI17_NUMBER 41
#define STM32_EXTI18_NUMBER 2
#define STM32_EXTI19_NUMBER 3
#define STM32_EXTI20_21_NUMBER 22
/*
* I2C units.
*/
#define STM32_I2C1_EVENT_HANDLER VectorB8
#define STM32_I2C1_ERROR_HANDLER VectorBC
#define STM32_I2C3_EVENT_HANDLER VectorC0
#define STM32_I2C3_ERROR_HANDLER VectorC4
#define STM32_I2C1_EVENT_NUMBER 30
#define STM32_I2C1_ERROR_NUMBER 31
#define STM32_I2C3_EVENT_NUMBER 32
#define STM32_I2C3_ERROR_NUMBER 33
/*
* QUADSPI unit.
*/
#define STM32_QUADSPI1_HANDLER Vector108
#define STM32_QUADSPI1_NUMBER 50
/*
* TIM units.
*/
#define STM32_TIM1_BRK_HANDLER VectorA0
#define STM32_TIM1_UP_TIM16_HANDLER VectorA4
#define STM32_TIM1_TRGCO_TIM17_HANDLER VectorA8
#define STM32_TIM1_CC_HANDLER VectorAC
#define STM32_TIM2_HANDLER VectorB0
#define STM32_TIM1_BRK_NUMBER 24
#define STM32_TIM1_UP_TIM16_NUMBER 25
#define STM32_TIM1_TRGCO_TIM17_NUMBER 26
#define STM32_TIM1_CC_NUMBER 27
#define STM32_TIM2_NUMBER 28
/*
* USART/UART units.
*/
#define STM32_USART1_HANDLER VectorD0
#define STM32_LPUART1_HANDLER VectorD4
#define STM32_USART1_NUMBER 36
#define STM32_LPUART1_NUMBER 37
/*
* USB unit.
*/
#define STM32_USB1_HP_HANDLER Vector8C
#define STM32_USB1_LP_HANDLER Vector90
#define STM32_USB1_HP_NUMBER 19
#define STM32_USB1_LP_NUMBER 20
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void irqInit(void);
void irqDeinit(void);
#ifdef __cplusplus
}
#endif
#endif /* STM32_ISR_H */
/** @} */
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
Concepts and parts of this file have been contributed by Ilya Kharin.
*/
/**
* @file STM32WBxx/stm32_isr.h
* @brief STM32WBxx ISR handler header.
*
* @addtogroup SRM32WBxx_ISR
* @{
*/
#ifndef STM32_ISR_H
#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISRs suppressed in standard drivers
* @{
*/
#define STM32_TIM1_SUPPRESS_ISR
#define STM32_TIM2_SUPPRESS_ISR
#define STM32_TIM16_SUPPRESS_ISR
#define STM32_TIM17_SUPPRESS_ISR
#define STM32_USART1_SUPPRESS_ISR
#define STM32_LPUART1_SUPPRESS_ISR
/** @} */
/**
* @name ISR names and numbers
* @{
*/
/*
* ADC unit.
*/
#define STM32_ADC1_HANDLER Vector88
#define STM32_ADC1_NUMBER 18
/*
* DMA unit.
*/
#define STM32_DMA1_CH1_HANDLER Vector6C
#define STM32_DMA1_CH2_HANDLER Vector70
#define STM32_DMA1_CH3_HANDLER Vector74
#define STM32_DMA1_CH4_HANDLER Vector78
#define STM32_DMA1_CH5_HANDLER Vector7C
#define STM32_DMA1_CH6_HANDLER Vector80
#define STM32_DMA1_CH7_HANDLER Vector84
#define STM32_DMA2_CH1_HANDLER Vector11C
#define STM32_DMA2_CH2_HANDLER Vector120
#define STM32_DMA2_CH3_HANDLER Vector124
#define STM32_DMA2_CH4_HANDLER Vector128
#define STM32_DMA2_CH5_HANDLER Vector12C
#define STM32_DMA2_CH6_HANDLER Vector130
#define STM32_DMA2_CH7_HANDLER Vector134
#define STM32_DMA1_CH1_NUMBER 11
#define STM32_DMA1_CH2_NUMBER 12
#define STM32_DMA1_CH3_NUMBER 13
#define STM32_DMA1_CH4_NUMBER 14
#define STM32_DMA1_CH5_NUMBER 15
#define STM32_DMA1_CH6_NUMBER 16
#define STM32_DMA1_CH7_NUMBER 17
#define STM32_DMA2_CH1_NUMBER 55
#define STM32_DMA2_CH2_NUMBER 56
#define STM32_DMA2_CH3_NUMBER 57
#define STM32_DMA2_CH4_NUMBER 58
#define STM32_DMA2_CH5_NUMBER 59
#define STM32_DMA2_CH6_NUMBER 60
#define STM32_DMA2_CH7_NUMBER 61
/*
* EXTI unit.
*/
#define STM32_EXTI0_HANDLER Vector58
#define STM32_EXTI1_HANDLER Vector5C
#define STM32_EXTI2_HANDLER Vector60
#define STM32_EXTI3_HANDLER Vector64
#define STM32_EXTI4_HANDLER Vector68
#define STM32_EXTI5_9_HANDLER Vector9C
#define STM32_EXTI10_15_HANDLER VectorE0
#define STM32_EXTI16_31_33_HANDLER Vector44 /* PVD PVM0 PVM2 */
#define STM32_EXTI17_HANDLER VectorE4 /* RTC ALARM */
#define STM32_EXTI18_HANDLER Vector48 /* RTC TAMP CSS */
#define STM32_EXTI19_HANDLER Vector4C /* RTC WAKEUP */
#define STM32_EXTI20_21_HANDLER Vector98 /* COMP2 COMP1 */
#define STM32_EXTI0_NUMBER 6
#define STM32_EXTI1_NUMBER 7
#define STM32_EXTI2_NUMBER 8
#define STM32_EXTI3_NUMBER 9
#define STM32_EXTI4_NUMBER 10
#define STM32_EXTI5_9_NUMBER 23
#define STM32_EXTI10_15_NUMBER 40
#define STM32_EXTI16_31_33_NUMBER 1
#define STM32_EXTI17_NUMBER 41
#define STM32_EXTI18_NUMBER 2
#define STM32_EXTI19_NUMBER 3
#define STM32_EXTI20_21_NUMBER 22
/*
* I2C units.
*/
#define STM32_I2C1_EVENT_HANDLER VectorB8
#define STM32_I2C1_ERROR_HANDLER VectorBC
#define STM32_I2C3_EVENT_HANDLER VectorC0
#define STM32_I2C3_ERROR_HANDLER VectorC4
#define STM32_I2C1_EVENT_NUMBER 30
#define STM32_I2C1_ERROR_NUMBER 31
#define STM32_I2C3_EVENT_NUMBER 32
#define STM32_I2C3_ERROR_NUMBER 33
/*
* QUADSPI unit.
*/
#define STM32_QUADSPI1_HANDLER Vector108
#define STM32_QUADSPI1_NUMBER 50
/*
* TIM units.
*/
#define STM32_TIM1_BRK_HANDLER VectorA0
#define STM32_TIM1_UP_TIM16_HANDLER VectorA4
#define STM32_TIM1_TRGCO_TIM17_HANDLER VectorA8
#define STM32_TIM1_CC_HANDLER VectorAC
#define STM32_TIM2_HANDLER VectorB0
#define STM32_TIM1_BRK_NUMBER 24
#define STM32_TIM1_UP_TIM16_NUMBER 25
#define STM32_TIM1_TRGCO_TIM17_NUMBER 26
#define STM32_TIM1_CC_NUMBER 27
#define STM32_TIM2_NUMBER 28
/*
* USART/UART units.
*/
#define STM32_USART1_HANDLER VectorD0
#define STM32_LPUART1_HANDLER VectorD4
#define STM32_USART1_NUMBER 36
#define STM32_LPUART1_NUMBER 37
/*
* USB unit.
*/
#define STM32_USB1_HP_HANDLER Vector8C
#define STM32_USB1_LP_HANDLER Vector90
#define STM32_USB1_HP_NUMBER 19
#define STM32_USB1_LP_NUMBER 20
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void irqInit(void);
void irqDeinit(void);
#ifdef __cplusplus
}
#endif
#endif /* STM32_ISR_H */
/** @} */

1590
os/hal/ports/STM32/STM32WBxx/stm32_rcc.h
View File

File diff suppressed because it is too large Load Diff

17
os/hal/ports/STM32/STM32WLxx/hal_lld.c
View File

@ -279,7 +279,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
/* PLL VCO frequency.*/
vcoclk = (selclk / (halfreq_t)mdiv) * (halfreq_t)ndiv;
if((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) {
if ((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) {
return true;
}
@ -291,9 +291,9 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
}
if ((cfgr & RCC_PLLCFGR_PLLPEN) != 0U) {
pclk = vcoclk / pdiv ;
pclk = vcoclk / pdiv;
if((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) {
if ((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) {
return true;
}
}
@ -308,7 +308,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLQEN) != 0U) {
qclk = vcoclk / qdiv;
if((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) {
if ((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) {
return true;
}
}
@ -323,7 +323,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLREN) != 0U) {
rclk = vcoclk / rdiv;
if((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) {
if ((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) {
return true;
}
}
@ -415,7 +415,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* SYSCLK frequency.*/
switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case STM32_SW_HSI16:
sysclk = hsi16clk;
break;
@ -437,7 +437,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* LPRUN sysclk check.*/
if (((ccp->pwr_cr1 & PWR_CR1_LPR_Msk) != 0U) && (sysclk > STM32_LPRUN_SYSCLK_MAX) ) {
if (((ccp->pwr_cr1 & PWR_CR1_LPR_Msk) != 0U) && (sysclk > STM32_LPRUN_SYSCLK_MAX)) {
return true;
}
@ -469,7 +469,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
hclk3 = sysclk / hprediv[(ccp->rcc_extcfgr & RCC_EXTCFGR_SHDHPRE_Msk) >> RCC_EXTCFGR_SHDHPRE_Pos];
/* MCO clock.*/
switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
case STM32_MCOSEL_NOCLOCK:
mcoclk = 0U;
break;
@ -662,7 +662,6 @@ void hal_lld_init(void) {
irqInit();
}
/**
* @brief STM32WLxx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.

1
os/hal/ports/STM32/STM32WLxx/hal_lld.h
View File

@ -473,7 +473,6 @@
#define STM32_LSI_ENABLED TRUE
#endif
/**
* @brief LSI prescaler value.
*/

2
os/nil/include/ch.h
View File

@ -418,7 +418,7 @@ typedef uint8_t ucnt_t; /**< Generic unsigned counter. */
#error "unsupported PORT_ARCH_REGISTERS_WIDTH value"
#endif
/** @} */
#endif /* defined(PORT_DOES_NOT_PROVIDE_TYPES) */
#endif
#if (CH_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
/**

1
os/oslib/src/chobjcaches.c
View File

@ -200,7 +200,6 @@ static oc_object_t *lru_get_last_s(objects_cache_t *ocp) {
return objp;
}
/* Out of critical section.*/
chSysUnlock();

12
os/rt/include/chearly.h
View File

@ -119,7 +119,7 @@ typedef uint8_t ucnt_t; /**< Generic unsigned counter. */
#error "unsupported PORT_ARCH_REGISTERS_WIDTH value"
#endif
/** @} */
#endif /* defined(PORT_DOES_NOT_PROVIDE_TYPES) */
#endif
/**
* @brief Type of a core identifier.
@ -195,16 +195,16 @@ typedef struct ch_os_instance os_instance_t;
#endif
/**
* @brief Safe cast of a queue pointer to a thread pointer.
* @note Casting to a thread pointer should always be performed using
* @brief Safe cast of a queue pointer to a thread pointer.
* @note Casting to a thread pointer should always be performed using
* this macro. Casting to threads pointer is allowed by design
* and this is the single check point for this operation.
*
* @param[in] p pointer to a queue/list structure
* @return The pointer to the thread containing the queue/list
* @param[in] p pointer to a queue/list structure
* @return The pointer to the thread containing the queue/list
* element.
*/
#define threadref(p) ((thread_t *)(void *)(p))
#define threadref(p) ((thread_t *)(void *)(p))
/*===========================================================================*/
/* External declarations. */

2
os/rt/include/chsys.h
View File

@ -91,7 +91,7 @@
#else
#define currcore (&ch0)
#endif
#endif /* defined(PORT_INSTANCE_ACCESS) */
#endif
/*===========================================================================*/
/* Module macros. */