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Style-related fixes, mainly white space. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14999 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-11-03 07:01:57 +00:00
parent ba6f180920
commit dcc0824e97
49 changed files with 5870 additions and 5892 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
View File

@ -641,9 +641,9 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adcm->ISR = adcp->adcm->ISR;
/* If a callback is set enable the overflow and analog watch dog interrupts. */
if (grpp->error_cb != NULL) {
adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE
| ADC_IER_AWD2IE
| ADC_IER_AWD3IE;
adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE |
ADC_IER_AWD2IE |
ADC_IER_AWD3IE;
}
#if STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE
/* Configuration for dual mode ADC12 */
@ -652,9 +652,10 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adcs->ISR = adcp->adcs->ISR;
/* If a callback is set enable the overflow and analog watch dog interrupts. */
if (grpp->error_cb != NULL) {
adcp->adcs->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE
| ADC_IER_AWD2IE
| ADC_IER_AWD3IE;
adcp->adcs->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE |
ADC_IER_AWD2IE |
ADC_IER_AWD3IE;
/* Configuring the CCR register with the user-specified settings
in the conversion group configuration structure, static settings are
preserved.*/

1
os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
View File

@ -254,7 +254,6 @@
#error "ADC DMA stream not defined"
#endif
/* ADC clock source checks.*/
#if STM32_ADC_PRESCALER_VALUE == 2
#define STM32_ADC_PRESC 1U

1
os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.c
View File

@ -89,7 +89,6 @@
#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TMSA + \
(STM32_FDCAN_TM_NBR * SRAMCAN_TM_SIZE)))
#define TIMEOUT_INIT_MS 250U
#define TIMEOUT_CSA_MS 250U

2
os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.h
View File

@ -287,7 +287,6 @@ typedef struct {
};
} CANRxStandardFilter;
/**
* @brief CAN extended filter.
* @note Accessing the frame data as word16 or word32 is not portable
@ -311,7 +310,6 @@ typedef struct {
};
} CANRxExtendedFilter;
/**
* @brief Type of a CAN configuration structure.
*/

4
os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
View File

@ -284,7 +284,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
break;
case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
/* Catches BTF event after the end of transmission.*/
(void)dp->DR; /* clear BTF.*/
(void)dp->DR; /* Clear BTF.*/
if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) {
/* Starts "read after write" operation, LSB = 1 -> receive.*/
i2cp->addr |= 0x01;
@ -306,7 +306,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))
(void)dp->SR2;
/* BERR flag doesn’t happen anymore in event handling */
/* BERR flag doesn<EFBFBD>t happen anymore in event handling */
#if 0
/* Errata 2.4.6 for STM32F40x, Spurious Bus Error detection in Master mode.*/
if (event & I2C_SR1_BERR) {

16
os/hal/ports/STM32/LLD/MACv2/hal_mac_lld.c
View File

@ -292,7 +292,7 @@ void mac_lld_init(void) {
__eth_rd[i].rdes2 = 0;
__eth_rd[i].rdes3 = STM32_RDES3_OWN | STM32_RDES3_IOC | STM32_RDES3_BUF1V;
for (j = 0; j < BUFFER_SIZE; j++) {
__eth_rb[i][j] = 825373492; /* telltale "1234" */
__eth_rb[i][j] = 825373492; /* Telltale "1234".*/
}
}
for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) {
@ -301,7 +301,7 @@ void mac_lld_init(void) {
__eth_td[i].tdes2 = 0;
__eth_td[i].tdes3 = 0;
for (j = 0; j < BUFFER_SIZE; j++) {
__eth_tb[i][j] = 892745528; /* telltale "5678" */
__eth_tb[i][j] = 892745528; /* Telltale "5678".*/
}
}
@ -426,7 +426,6 @@ void mac_lld_start(MACDriver *macp) {
ETH->DMACSR = ETH_DMACSR_NIS;
ETH->DMACIER = ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE;
/* Check because errata on some devices. There should be no need to
disable flushing because the TXFIFO should be empty on macStart().*/
#if !defined(STM32_MAC_DISABLE_TX_FLUSH)
@ -440,9 +439,8 @@ void mac_lld_start(MACDriver *macp) {
ETH->MTLRQOMR = ETH_MTLRQOMR_DISTCPEF | ETH_MTLRQOMR_RSF;
ETH->MTLTQOMR = ETH_MTLTQOMR_TSF;
ETH->DMACTCR = ETH_DMACTCR_ST | ETH_DMACTCR_TPBL_1PBL;
ETH->DMACRCR = ETH_DMACRCR_SR | ETH_DMACRCR_RPBL_1PBL
| (STM32_MAC_BUFFERS_SIZE << ETH_DMACRCR_RBSZ_Pos
& ETH_DMACRCR_RBSZ);
ETH->DMACRCR = ETH_DMACRCR_SR | ETH_DMACRCR_RPBL_1PBL |
(STM32_MAC_BUFFERS_SIZE << ETH_DMACRCR_RBSZ_Pos & ETH_DMACRCR_RBSZ);
}
/**
@ -504,8 +502,8 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
}
tdes->tdes0 = (uint32_t)__eth_tb[macp->tdindex];
/* Marks the current descriptor as locked using a reserved bit.*/
/*tdes->tdes0 |= STM32_TDES0_LOCKED; */
/* Marks the current descriptor as locked using a reserved bit.
tdes->tdes0 |= STM32_TDES0_LOCKED; */
tdes->tdes1++;
/* Next TX descriptor to use.*/
@ -589,7 +587,7 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
&& (rdes->rdes3 & STM32_RDES3_FD) && (rdes->rdes3 & STM32_RDES3_LD)) {
/* Found a valid one.*/
rdp->offset = 0;
rdp->size = (rdes->rdes3 & STM32_RDES3_PL_MASK) -2; /* Lose CRC */
rdp->size = (rdes->rdes3 & STM32_RDES3_PL_MASK) -2; /* Lose CRC.*/
rdp->physdesc = rdes;
/* Reposition in ring.*/
macp->rdindex++;

10
os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
View File

@ -510,12 +510,14 @@ static void otg_isoc_out_failed_handler(USBDriver *usbp) {
for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) &&
((otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) != 0)) {
/* Endpoint enabled -> ISOC OUT transfer failed */
/* Disable endpoint */
#if 0
/* Endpoint enabled -> ISOC OUT transfer failed.*/
/* Disable endpoint.*/
/* CHTODO:: Core stucks here */
/*otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK);
otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK);
while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA)
;*/
;
#endif
/* Prepare transfer for next frame.*/
_usb_isr_invoke_out_cb(usbp, ep);
}

42
os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h
View File

@ -360,7 +360,7 @@ typedef struct {
#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6)
#define GRXSTSR_DPID_MASK (3U << 15) /**< Data PID mask. */
#define GRXSTSR_DPID(n) ((n) << 15) /**< Data PID value. */
#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
#define GRXSTSR_BCNT_MASK (0x7FFU << 4) /**< Byte count mask. */
#define GRXSTSR_BCNT(n) ((n) << 4) /**< Byte count value. */
#define GRXSTSR_CHNUM_MASK (15U << 0) /**< Channel number mask. */
#define GRXSTSR_CHNUM(n) ((n) << 0) /**< Channel number value. */
@ -372,7 +372,7 @@ typedef struct {
* @name GRXSTSP register bit definitions
* @{
*/
#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */
#define GRXSTSP_PKTSTS_MASK (15U << 17) /**< Packet status mask. */
#define GRXSTSP_PKTSTS(n) ((n) << 17) /**< Packet status value. */
#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1)
#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2)
@ -381,7 +381,7 @@ typedef struct {
#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6)
#define GRXSTSP_DPID_MASK (3U << 15) /**< Data PID mask. */
#define GRXSTSP_DPID(n) ((n) << 15) /**< Data PID value. */
#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
#define GRXSTSP_BCNT_MASK (0x7FFU << 4) /**< Byte count mask. */
#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */
#define GRXSTSP_BCNT(n) ((n) << 4) /**< Byte count value. */
#define GRXSTSP_CHNUM_MASK (15U << 0) /**< Channel number mask. */
@ -395,7 +395,7 @@ typedef struct {
* @name GRXFSIZ register bit definitions
* @{
*/
#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */
#define GRXFSIZ_RXFD_MASK (0xFFFFU << 0) /**< RxFIFO depth mask. */
#define GRXFSIZ_RXFD(n) ((n) << 0) /**< RxFIFO depth value. */
/** @} */
@ -407,7 +407,7 @@ typedef struct {
mask. */
#define DIEPTXF_INEPTXFD(n) ((n) << 16) /**< IN endpoint TxFIFO depth
value. */
#define DIEPTXF_INEPTXSA_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit
#define DIEPTXF_INEPTXSA_MASK (0xFFFFU << 0) /**< IN endpoint FIFOx transmit
RAM start address mask.*/
#define DIEPTXF_INEPTXSA(n) ((n) << 0) /**< IN endpoint FIFOx transmit
RAM start address value.*/
@ -469,8 +469,10 @@ typedef struct {
* @name HFNUM register bit definitions
* @{
*/
#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/
#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/
#define HFNUM_FTREM_MASK (0xFFFFU << 16) /**< Frame time Remaining
mask. */
#define HFNUM_FTREM(n) ((n) << 16) /**< Frame time Remaining
value. */
#define HFNUM_FRNUM_MASK (0xFFFFU << 0) /**< Frame number mask. */
#define HFNUM_FRNUM(n) ((n) << 0) /**< Frame number value. */
/** @} */
@ -503,8 +505,10 @@ typedef struct {
* @name HAINT register bit definitions
* @{
*/
#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */
#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */
#define HAINT_HAINT_MASK (0xFFFFU << 0) /**< Channel interrupts
mask. */
#define HAINT_HAINT(n) ((n) << 0) /**< Channel interrupts
value. */
/** @} */
/**
@ -524,7 +528,7 @@ typedef struct {
#define HPRT_PSPD_MASK (3U << 17) /**< Port speed mask. */
#define HPRT_PSPD_FS (1U << 17) /**< Full speed value. */
#define HPRT_PSPD_LS (2U << 17) /**< Low speed value. */
#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */
#define HPRT_PTCTL_MASK (15U << 13) /**< Port Test control mask. */
#define HPRT_PTCTL(n) ((n) << 13) /**< Port Test control value. */
#define HPRT_PPWR (1U << 12) /**< Port power. */
#define HPRT_PLSTS_MASK (3U << 11) /**< Port Line status mask. */
@ -620,7 +624,7 @@ typedef struct {
#define HCTSIZ_DPID_SETUP (3U << 29) /**< SETUP. */
#define HCTSIZ_PKTCNT_MASK (0x3FFU << 19) /**< Packet count mask. */
#define HCTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */
#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */
#define HCTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */
#define HCTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */
/** @} */
@ -669,12 +673,12 @@ typedef struct {
* @name DSTS register bit definitions
* @{
*/
#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received
SOF mask. */
#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received
SOF value. */
#define DSTS_FNSOF_ODD (1U<<8) /**< Frame parity of the received
SOF value. */
#define DSTS_FNSOF_MASK (0x3FFU << 8) /**< Frame number of the
received SOF mask. */
#define DSTS_FNSOF(n) ((n) << 8) /**< Frame number of the
received SOF value. */
#define DSTS_FNSOF_ODD (1U << 8) /**< Frame parity of the
received SOF value. */
#define DSTS_EERR (1U << 3) /**< Erratic error. */
#define DSTS_ENUMSPD_MASK (3U << 1) /**< Enumerated speed mask. */
#define DSTS_ENUMSPD_FS_48 (3U << 1) /**< Full speed (PHY clock is
@ -784,7 +788,7 @@ typedef struct {
#define DIEPCTL_TXFNUM(n) ((n) << 22) /**< TxFIFO number value. */
#define DIEPCTL_STALL (1U << 21) /**< STALL handshake. */
#define DIEPCTL_SNPM (1U << 20) /**< Snoop mode. */
#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */
#define DIEPCTL_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */
#define DIEPCTL_EPTYP_CTRL (0U << 18) /**< Control. */
#define DIEPCTL_EPTYP_ISO (1U << 18) /**< Isochronous. */
#define DIEPCTL_EPTYP_BULK (2U << 18) /**< Bulk. */
@ -827,7 +831,7 @@ typedef struct {
* @name DTXFSTS register bit definitions.
* @{
*/
#define DTXFSTS_INEPTFSAV_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space
#define DTXFSTS_INEPTFSAV_MASK (0xFFFFU << 0) /**< IN endpoint TxFIFO space
available. */
/** @} */

1
os/hal/ports/STM32/LLD/RTCv3/hal_rtc_lld.h
View File

@ -249,7 +249,6 @@ typedef struct hal_rtc_wakeup {
/* Pointer to TAMPER registers block. */ \
TAMP_TypeDef *tamp
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/

1
os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h
View File

@ -319,7 +319,6 @@
#error "invalid DMA stream associated to SPI3 TX"
#endif
#endif /* STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX */
#if !defined(STM32_DMA_REQUIRED)

4
os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.h
View File

@ -137,7 +137,7 @@
#if !defined(STM32_HAS_TIM22)
#define STM32_HAS_TIM22 FALSE
#endif
/**/
/* End of checks to be removed.*/
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
@ -684,7 +684,6 @@ extern "C" {
/* Driver inline functions. */
/*===========================================================================*/
#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
/**
@ -786,7 +785,6 @@ static inline bool st_lld_is_alarm_active(void) {
*/
static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) {
STM32_ST_TIM->CCR[alarm] = (uint32_t)abstime;
STM32_ST_TIM->SR = 0;
STM32_ST_TIM->DIER |= (STM32_TIM_DIER_CC1IE << alarm);

2
os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.c
View File

@ -117,7 +117,7 @@ void st_lld_init(void) {
/* Wait for shadow reg. update.*/
while ((RTC->ICSR & RTC_ICSR_RSF) == 0U) {
// wait RSF flag
/* Wait RSF flag.*/
}
/* Compare all Sub Seconds 32 bits for RTC Alarm A.*/

2
os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.h
View File

@ -84,7 +84,6 @@
#error "RTC does not support binary mode"
#endif
#if (OSAL_ST_RESOLUTION != 32)
#error "ST based on RTC requires 32bits resolution. Set CH_CFG_ST_RESOLUTION to 32."
#endif
@ -177,7 +176,6 @@ static inline void st_lld_set_alarm(systime_t abstime) {
st_lld_start_alarm(abstime);
}
/**
* @brief Determines if the alarm is active.
*

2
os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c
View File

@ -377,7 +377,6 @@ msg_t sio_lld_start(SIODriver *siop) {
siop->sync_rx = NULL;
siop->sync_tx = NULL;
siop->sync_txend = NULL;
// siop->events = 0U;
#endif
}
@ -387,7 +386,6 @@ msg_t sio_lld_start(SIODriver *siop) {
return HAL_RET_SUCCESS;
}
/**
* @brief Deactivates the SIO peripheral.
*

2
os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c
View File

@ -385,7 +385,6 @@ msg_t sio_lld_start(SIODriver *siop) {
siop->sync_rx = NULL;
siop->sync_tx = NULL;
siop->sync_txend = NULL;
// siop->events = 0U;
#endif
}
@ -395,7 +394,6 @@ msg_t sio_lld_start(SIODriver *siop) {
return HAL_RET_SUCCESS;
}
/**
* @brief Deactivates the SIO peripheral.
*

4
os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c
View File

@ -65,8 +65,8 @@ EFlashDriver EFLD1;
/* Driver local variables and types. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || defined(STM32F40_41xxx) \
|| defined(__DOXYGEN__)
#if defined(STM32F413xx) || defined(STM32F412xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
/* Sector table for 1.5M device. */
static const flash_sector_descriptor_t efl_lld_sect1[STM32_FLASH1_SECTORS_TOTAL] = {

4
os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h
View File

@ -51,8 +51,8 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || defined(STM32F40_41xxx) \
|| defined(__DOXYGEN__)
#if defined(STM32F413xx) || defined(STM32F412xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22

2
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -288,7 +288,6 @@
#define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */
/** @} */
/**
* @name RCC_CCIPR2 register bits definitions
* @{
@ -1569,7 +1568,6 @@
#elif STM32_RNGSEL == STM32_RNGSEL_PLLQCLK
#define STM32_RNGCLK (hal_lld_get_clock_point(CLK_PLLQCLK) / STM32_RNGDIV_VALUE)
#else
#error "invalid source selected for RNG clock"
#endif

1
os/hal/ports/STM32/STM32G0xx/stm32_registry.h
View File

@ -95,7 +95,6 @@
#define STM32_RCC_HAS_PLL TRUE
#define STM32_RCC_PLL_HAS_P TRUE
/*#define STM32_RCC_PLL_HAS_Q TRUE*/ /* Varies, see below.*/
#define STM32_RCC_PLL_HAS_R TRUE
#define STM32_RCC_HAS_PLLSAI1 FALSE

3
os/hal/ports/STM32/STM32G4xx/stm32_registry.h
View File

@ -166,7 +166,6 @@
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
@ -381,7 +380,6 @@
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
@ -596,7 +594,6 @@
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2

1
os/hal/ports/STM32/STM32L0xx/stm32_registry.h
View File

@ -574,7 +574,6 @@
#define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE
/*===========================================================================*/
/* STM32L052xx, STM32L062xx, STM32L053xx, STM32L063xx. */
/*===========================================================================*/

1
os/hal/ports/STM32/STM32L4xx+/stm32_isr.h
View File

@ -160,7 +160,6 @@
#define STM32_I2C4_ERROR_NUMBER 83
#define STM32_I2C4_EVENT_NUMBER 84
/*
* OCTOSPI unit.
*/

2
os/hal/ports/STM32/STM32L5xx/stm32_rcc.h
View File

@ -525,7 +525,7 @@
*
* @api
*/
#define rccResetGTZC() /*rccResetAHB1(RCC_AHB1RST_GTZCRST)*/
#define rccResetGTZC() /* Disabled rccResetAHB1(RCC_AHB1RST_GTZCRST) */
/** @} */
/**

1
os/hal/ports/STM32/STM32MP1xx/hal_lld.h
View File

@ -238,7 +238,6 @@
#define STM32_HSI_ENABLED TRUE
#endif
/**
* @brief HSI divider setting.
* @note This initialization is performed only if TZEN=0 or MCKPROT=0

1
os/hal/ports/STM32/STM32WBxx/hal_lld.h
View File

@ -1251,7 +1251,6 @@
#define STM32_ACTIVATE_PLL FALSE
#endif
/**
* @brief STM32_PLLPEN field.
*/

1
os/hal/ports/STM32/STM32WLxx/hal_lld.c
View File

@ -662,7 +662,6 @@ void hal_lld_init(void) {
irqInit();
}
/**
* @brief STM32WLxx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.

1
os/hal/ports/STM32/STM32WLxx/hal_lld.h
View File

@ -473,7 +473,6 @@
#define STM32_LSI_ENABLED TRUE
#endif
/**
* @brief LSI prescaler value.
*/

2
os/nil/include/ch.h
View File

@ -418,7 +418,7 @@ typedef uint8_t ucnt_t; /**< Generic unsigned counter. */
#error "unsupported PORT_ARCH_REGISTERS_WIDTH value"
#endif
/** @} */
#endif /* defined(PORT_DOES_NOT_PROVIDE_TYPES) */
#endif
#if (CH_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
/**

1
os/oslib/src/chobjcaches.c
View File

@ -200,7 +200,6 @@ static oc_object_t *lru_get_last_s(objects_cache_t *ocp) {
return objp;
}
/* Out of critical section.*/
chSysUnlock();

2
os/rt/include/chearly.h
View File

@ -119,7 +119,7 @@ typedef uint8_t ucnt_t; /**< Generic unsigned counter. */
#error "unsupported PORT_ARCH_REGISTERS_WIDTH value"
#endif
/** @} */
#endif /* defined(PORT_DOES_NOT_PROVIDE_TYPES) */
#endif
/**
* @brief Type of a core identifier.

2
os/rt/include/chsys.h
View File

@ -91,7 +91,7 @@
#else
#define currcore (&ch0)
#endif
#endif /* defined(PORT_INSTANCE_ACCESS) */
#endif
/*===========================================================================*/
/* Module macros. */