andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Style-related fixes, mainly white space. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14999 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-11-03 07:01:57 +00:00
parent ba6f180920
commit dcc0824e97
49 changed files with 5870 additions and 5892 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
View File

@ -641,9 +641,9 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adcm->ISR = adcp->adcm->ISR;
/* If a callback is set enable the overflow and analog watch dog interrupts. */
if (grpp->error_cb != NULL) {
adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE
| ADC_IER_AWD2IE
| ADC_IER_AWD3IE;
adcp->adcm->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE |
ADC_IER_AWD2IE |
ADC_IER_AWD3IE;
}
#if STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE
/* Configuration for dual mode ADC12 */
@ -652,9 +652,10 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adcs->ISR = adcp->adcs->ISR;
/* If a callback is set enable the overflow and analog watch dog interrupts. */
if (grpp->error_cb != NULL) {
adcp->adcs->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE
| ADC_IER_AWD2IE
| ADC_IER_AWD3IE;
adcp->adcs->IER = ADC_IER_OVRIE | ADC_IER_AWD1IE |
ADC_IER_AWD2IE |
ADC_IER_AWD3IE;
/* Configuring the CCR register with the user-specified settings
in the conversion group configuration structure, static settings are
preserved.*/

1
os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
View File

@ -254,7 +254,6 @@
#error "ADC DMA stream not defined"
#endif
/* ADC clock source checks.*/
#if STM32_ADC_PRESCALER_VALUE == 2
#define STM32_ADC_PRESC 1U

2
os/hal/ports/STM32/LLD/CRYPv1/hal_crypto_lld.c
View File

@ -1540,7 +1540,7 @@ cryerror_t cry_lld_SHA256_init(CRYDriver *cryp, SHA256Context *sha256ctxp) {
sha256ctxp->last_size = 0U;
/* Initializing operation.*/
HASH->CR = /*HASH_CR_MDMAT |*/ HASH_CR_ALGO_1 | HASH_CR_ALGO_0 |
HASH->CR = /* HASH_CR_MDMAT |*/ HASH_CR_ALGO_1 | HASH_CR_ALGO_0 |
HASH_CR_DATATYPE_1 | HASH_CR_INIT;
return CRY_NOERROR;

3
os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.c
View File

@ -89,7 +89,6 @@
#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TMSA + \
(STM32_FDCAN_TM_NBR * SRAMCAN_TM_SIZE)))
#define TIMEOUT_INIT_MS 250U
#define TIMEOUT_CSA_MS 250U
@ -567,7 +566,7 @@ void can_lld_serve_interrupt(CANDriver *canp) {
}
/* Overflow events.*/
if (((ir & FDCAN_IR_RF0L) != 0U) || ((ir & FDCAN_IR_RF1L) != 0U) ) {
if (((ir & FDCAN_IR_RF0L) != 0U) || ((ir & FDCAN_IR_RF1L) != 0U)) {
_can_error_isr(canp, CAN_OVERFLOW_ERROR);
}

2
os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.h
View File

@ -287,7 +287,6 @@ typedef struct {
};
} CANRxStandardFilter;
/**
* @brief CAN extended filter.
* @note Accessing the frame data as word16 or word32 is not portable
@ -311,7 +310,6 @@ typedef struct {
};
} CANRxExtendedFilter;
/**
* @brief Type of a CAN configuration structure.
*/

4
os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
View File

@ -284,7 +284,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
break;
case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
/* Catches BTF event after the end of transmission.*/
(void)dp->DR; /* clear BTF.*/
(void)dp->DR; /* Clear BTF.*/
if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) {
/* Starts "read after write" operation, LSB = 1 -> receive.*/
i2cp->addr |= 0x01;
@ -306,7 +306,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))
(void)dp->SR2;
/* BERR flag doesn’t happen anymore in event handling */
/* BERR flag doesn<EFBFBD>t happen anymore in event handling */
#if 0
/* Errata 2.4.6 for STM32F40x, Spurious Bus Error detection in Master mode.*/
if (event & I2C_SR1_BERR) {

20
os/hal/ports/STM32/LLD/MACv2/hal_mac_lld.c
View File

@ -279,7 +279,7 @@ OSAL_IRQ_HANDLER(STM32_ETH_HANDLER) {
* @notapi
*/
void mac_lld_init(void) {
unsigned i,j;
unsigned i, j;
macObjectInit(&ETHD1);
ETHD1.link_up = false;
@ -292,7 +292,7 @@ void mac_lld_init(void) {
__eth_rd[i].rdes2 = 0;
__eth_rd[i].rdes3 = STM32_RDES3_OWN | STM32_RDES3_IOC | STM32_RDES3_BUF1V;
for (j = 0; j < BUFFER_SIZE; j++) {
__eth_rb[i][j] = 825373492; /* telltale "1234" */
__eth_rb[i][j] = 825373492; /* Telltale "1234".*/
}
}
for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) {
@ -301,7 +301,7 @@ void mac_lld_init(void) {
__eth_td[i].tdes2 = 0;
__eth_td[i].tdes3 = 0;
for (j = 0; j < BUFFER_SIZE; j++) {
__eth_tb[i][j] = 892745528; /* telltale "5678" */
__eth_tb[i][j] = 892745528; /* Telltale "5678".*/
}
}
@ -426,7 +426,6 @@ void mac_lld_start(MACDriver *macp) {
ETH->DMACSR = ETH_DMACSR_NIS;
ETH->DMACIER = ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE;
/* Check because errata on some devices. There should be no need to
disable flushing because the TXFIFO should be empty on macStart().*/
#if !defined(STM32_MAC_DISABLE_TX_FLUSH)
@ -440,9 +439,8 @@ void mac_lld_start(MACDriver *macp) {
ETH->MTLRQOMR = ETH_MTLRQOMR_DISTCPEF | ETH_MTLRQOMR_RSF;
ETH->MTLTQOMR = ETH_MTLTQOMR_TSF;
ETH->DMACTCR = ETH_DMACTCR_ST | ETH_DMACTCR_TPBL_1PBL;
ETH->DMACRCR = ETH_DMACRCR_SR | ETH_DMACRCR_RPBL_1PBL
| (STM32_MAC_BUFFERS_SIZE << ETH_DMACRCR_RBSZ_Pos
& ETH_DMACRCR_RBSZ);
ETH->DMACRCR = ETH_DMACRCR_SR | ETH_DMACRCR_RPBL_1PBL |
(STM32_MAC_BUFFERS_SIZE << ETH_DMACRCR_RBSZ_Pos & ETH_DMACRCR_RBSZ);
}
/**
@ -503,9 +501,9 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
return MSG_TIMEOUT;
}
tdes->tdes0 = (uint32_t )__eth_tb[macp->tdindex];
/* Marks the current descriptor as locked using a reserved bit.*/
/*tdes->tdes0 |= STM32_TDES0_LOCKED; */
tdes->tdes0 = (uint32_t)__eth_tb[macp->tdindex];
/* Marks the current descriptor as locked using a reserved bit.
tdes->tdes0 |= STM32_TDES0_LOCKED; */
tdes->tdes1++;
/* Next TX descriptor to use.*/
@ -589,7 +587,7 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
&& (rdes->rdes3 & STM32_RDES3_FD) && (rdes->rdes3 & STM32_RDES3_LD)) {
/* Found a valid one.*/
rdp->offset = 0;
rdp->size = (rdes->rdes3 & STM32_RDES3_PL_MASK) -2; /* Lose CRC */
rdp->size = (rdes->rdes3 & STM32_RDES3_PL_MASK) -2; /* Lose CRC.*/
rdp->physdesc = rdes;
/* Reposition in ring.*/
macp->rdindex++;

12
os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
View File

@ -510,12 +510,14 @@ static void otg_isoc_out_failed_handler(USBDriver *usbp) {
for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) &&
((otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) != 0)) {
/* Endpoint enabled -> ISOC OUT transfer failed */
/* Disable endpoint */
#if 0
/* Endpoint enabled -> ISOC OUT transfer failed.*/
/* Disable endpoint.*/
/* CHTODO:: Core stucks here */
/*otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK);
otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK);
while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA)
;*/
;
#endif
/* Prepare transfer for next frame.*/
_usb_isr_invoke_out_cb(usbp, ep);
}
@ -1148,7 +1150,7 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
usbp->epc[ep]->out_maxsize;
rxsize = (pcnt * usbp->epc[ep]->out_maxsize + 3U) & 0xFFFFFFFCU;
/*Setting up transaction parameters in DOEPTSIZ.*/
/* Setting up transaction parameters in DOEPTSIZ.*/
usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) |
DOEPTSIZ_XFRSIZ(rxsize);

708
os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h
View File

File diff suppressed because it is too large Load Diff

1
os/hal/ports/STM32/LLD/RTCv3/hal_rtc_lld.h
View File

@ -249,7 +249,6 @@ typedef struct hal_rtc_wakeup {
/* Pointer to TAMPER registers block. */ \
TAMP_TypeDef *tamp
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/

1
os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.h
View File

@ -319,7 +319,6 @@
#error "invalid DMA stream associated to SPI3 TX"
#endif
#endif /* STM32_ADVANCED_DMA && !STM32_DMA_SUPPORTS_DMAMUX */
#if !defined(STM32_DMA_REQUIRED)

2
os/hal/ports/STM32/LLD/SPIv2/hal_spi_v2_lld.c
View File

@ -277,7 +277,7 @@ static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
* @return The operation status.
*/
static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream,
uint32_t txstream, uint32_t priority){
uint32_t txstream, uint32_t priority) {
spip->dmarx = dmaStreamAllocI(rxstream, priority,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,

4
os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c
View File

@ -396,7 +396,7 @@ static void spi_lld_serve_interrupt(SPIDriver *spip) {
* @return The operation status.
*/
static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream,
uint32_t txstream, uint32_t priority){
uint32_t txstream, uint32_t priority) {
spip->rx.dma = dmaStreamAllocI(rxstream, priority,
(stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
@ -428,7 +428,7 @@ static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream,
* @return The operation status.
*/
static msg_t spi_lld_get_bdma(SPIDriver *spip, uint32_t rxstream,
uint32_t txstream, uint32_t priority){
uint32_t txstream, uint32_t priority) {
spip->rx.bdma = bdmaStreamAllocI(rxstream, priority,
(stm32_bdmaisr_t)spi_lld_serve_bdma_rx_interrupt,

4
os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.h
View File

@ -137,7 +137,7 @@
#if !defined(STM32_HAS_TIM22)
#define STM32_HAS_TIM22 FALSE
#endif
/**/
/* End of checks to be removed.*/
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
@ -684,7 +684,6 @@ extern "C" {
/* Driver inline functions. */
/*===========================================================================*/
#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
/**
@ -786,7 +785,6 @@ static inline bool st_lld_is_alarm_active(void) {
*/
static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) {
STM32_ST_TIM->CCR[alarm] = (uint32_t)abstime;
STM32_ST_TIM->SR = 0;
STM32_ST_TIM->DIER |= (STM32_TIM_DIER_CC1IE << alarm);

2
os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.c
View File

@ -117,7 +117,7 @@ void st_lld_init(void) {
/* Wait for shadow reg. update.*/
while ((RTC->ICSR & RTC_ICSR_RSF) == 0U) {
// wait RSF flag
/* Wait RSF flag.*/
}
/* Compare all Sub Seconds 32 bits for RTC Alarm A.*/

2
os/hal/ports/STM32/LLD/SYSTICKv2/hal_st_lld.h
View File

@ -84,7 +84,6 @@
#error "RTC does not support binary mode"
#endif
#if (OSAL_ST_RESOLUTION != 32)
#error "ST based on RTC requires 32bits resolution. Set CH_CFG_ST_RESOLUTION to 32."
#endif
@ -177,7 +176,6 @@ static inline void st_lld_set_alarm(systime_t abstime) {
st_lld_start_alarm(abstime);
}
/**
* @brief Determines if the alarm is active.
*

2
os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c
View File

@ -377,7 +377,6 @@ msg_t sio_lld_start(SIODriver *siop) {
siop->sync_rx = NULL;
siop->sync_tx = NULL;
siop->sync_txend = NULL;
// siop->events = 0U;
#endif
}
@ -387,7 +386,6 @@ msg_t sio_lld_start(SIODriver *siop) {
return HAL_RET_SUCCESS;
}
/**
* @brief Deactivates the SIO peripheral.
*

2
os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c
View File

@ -385,7 +385,6 @@ msg_t sio_lld_start(SIODriver *siop) {
siop->sync_rx = NULL;
siop->sync_tx = NULL;
siop->sync_txend = NULL;
// siop->events = 0U;
#endif
}
@ -395,7 +394,6 @@ msg_t sio_lld_start(SIODriver *siop) {
return HAL_RET_SUCCESS;
}
/**
* @brief Deactivates the SIO peripheral.
*

4
os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c
View File

@ -539,8 +539,8 @@ void usb_lld_reset(USBDriver *usbp) {
STM32_USB->BTABLE = BTABLE_ADDR;
STM32_USB->ISTR = 0;
STM32_USB->DADDR = DADDR_EF;
cntr = /*CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM |
CNTR_WKUPM | /*CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM;
cntr = /* CNTR_ESOFM | */ CNTR_RESETM | CNTR_SUSPM |
CNTR_WKUPM | /* CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM;
/* The SOF interrupt is only enabled if a callback is defined for
this service because it is an high rate source.*/
if (usbp->config->sof_cb != NULL)

4
os/hal/ports/STM32/STM32F4xx/hal_efl_lld.c
View File

@ -65,8 +65,8 @@ EFlashDriver EFLD1;
/* Driver local variables and types. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || defined(STM32F40_41xxx) \
|| defined(__DOXYGEN__)
#if defined(STM32F413xx) || defined(STM32F412xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
/* Sector table for 1.5M device. */
static const flash_sector_descriptor_t efl_lld_sect1[STM32_FLASH1_SECTORS_TOTAL] = {

4
os/hal/ports/STM32/STM32F4xx/hal_efl_lld.h
View File

@ -51,8 +51,8 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(STM32F413xx) || defined(STM32F412xx) || defined(STM32F40_41xxx) \
|| defined(__DOXYGEN__)
#if defined(STM32F413xx) || defined(STM32F412xx) || \
defined(STM32F40_41xxx) || defined(__DOXYGEN__)
/* Flash size register. */
#define STM32_FLASH_SIZE_REGISTER 0x1FFF7A22

12
os/hal/ports/STM32/STM32G0xx/hal_lld.c
View File

@ -354,7 +354,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
/* PLL VCO frequency.*/
pllvcoclk = (pllselclk / (halfreq_t)pllmdiv) * (halfreq_t)pllndiv;
if((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) {
if ((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) {
return true;
}
@ -363,7 +363,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLPEN) != 0U) {
pllpclk = pllvcoclk / pllpdiv;
if((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) {
if ((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) {
return true;
}
}
@ -373,7 +373,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLQEN) != 0U) {
pllqclk = pllvcoclk / pllqdiv;
if((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) {
if ((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) {
return true;
}
}
@ -383,14 +383,14 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLREN) != 0U) {
pllrclk = pllvcoclk / pllrdiv;
if((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) {
if ((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) {
return true;
}
}
}
/* SYSCLK frequency.*/
switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case RCC_CFGR_SW_HSI:
sysclk = hsisysclk;
break;
@ -427,7 +427,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* MCO clock.*/
switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
case STM32_MCOSEL_NOCLOCK:
mcoclk = 0U;
break;

2
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -288,7 +288,6 @@
#define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */
/** @} */
/**
* @name RCC_CCIPR2 register bits definitions
* @{
@ -1569,7 +1568,6 @@
#elif STM32_RNGSEL == STM32_RNGSEL_PLLQCLK
#define STM32_RNGCLK (hal_lld_get_clock_point(CLK_PLLQCLK) / STM32_RNGDIV_VALUE)
#else
#error "invalid source selected for RNG clock"
#endif

1
os/hal/ports/STM32/STM32G0xx/stm32_registry.h
View File

@ -95,7 +95,6 @@
#define STM32_RCC_HAS_PLL TRUE
#define STM32_RCC_PLL_HAS_P TRUE
/*#define STM32_RCC_PLL_HAS_Q TRUE*/ /* Varies, see below.*/
#define STM32_RCC_PLL_HAS_R TRUE
#define STM32_RCC_HAS_PLLSAI1 FALSE

12
os/hal/ports/STM32/STM32G4xx/hal_lld.c
View File

@ -364,7 +364,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
/* PLL VCO frequency.*/
pllvcoclk = (pllselclk / (halfreq_t)pllmdiv) * (halfreq_t)pllndiv;
if((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) {
if ((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) {
return true;
}
@ -384,7 +384,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLPEN) != 0U) {
pllpclk = pllvcoclk / pllpdiv;
if((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) {
if ((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) {
return true;
}
}
@ -394,7 +394,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLQEN) != 0U) {
pllqclk = pllvcoclk / pllqdiv;
if((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) {
if ((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) {
return true;
}
}
@ -404,14 +404,14 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLREN) != 0U) {
pllrclk = pllvcoclk / pllrdiv;
if((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) {
if ((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) {
return true;
}
}
}
/* SYSCLK frequency.*/
switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case RCC_CFGR_SW_HSI:
sysclk = hsi16clk;
break;
@ -451,7 +451,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* MCO clock.*/
switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
case STM32_MCOSEL_NOCLOCK:
mcoclk = 0U;
break;

3
os/hal/ports/STM32/STM32G4xx/stm32_registry.h
View File

@ -166,7 +166,6 @@
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
@ -381,7 +380,6 @@
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
@ -596,7 +594,6 @@
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2

16
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -1296,35 +1296,35 @@
#error "Using a wrong mcuconf.h file, STM32H7xx_MCUCONF not defined"
#endif
#if defined(STM32H750xx)&& !defined(STM32H750_MCUCONF)
#if defined(STM32H750xx) && !defined(STM32H750_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H750_MCUCONF not defined"
#endif
#if defined(STM32H742xx)&& !defined(STM32H742_MCUCONF)
#if defined(STM32H742xx) && !defined(STM32H742_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H742_MCUCONF not defined"
#endif
#if defined(STM32H743xx)&& !defined(STM32H743_MCUCONF)
#if defined(STM32H743xx) && !defined(STM32H743_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H743_MCUCONF not defined"
#endif
#if defined(STM32H753xx)&& !defined(STM32H753_MCUCONF)
#if defined(STM32H753xx) && !defined(STM32H753_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H753_MCUCONF not defined"
#endif
#if defined(STM32H745xx)&& !defined(STM32H745_MCUCONF)
#if defined(STM32H745xx) && !defined(STM32H745_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H745_MCUCONF not defined"
#endif
#if defined(STM32H755xx)&& !defined(STM32H755_MCUCONF)
#if defined(STM32H755xx) && !defined(STM32H755_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H755_MCUCONF not defined"
#endif
#if defined(STM32H747xx)&& !defined(STM32H747_MCUCONF)
#if defined(STM32H747xx) && !defined(STM32H747_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H747_MCUCONF not defined"
#endif
#if defined(STM32H757xx)&& !defined(STM32H757_MCUCONF)
#if defined(STM32H757xx) && !defined(STM32H757_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32H757_MCUCONF not defined"
#endif

1
os/hal/ports/STM32/STM32L0xx/stm32_registry.h
View File

@ -574,7 +574,6 @@
#define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE
/*===========================================================================*/
/* STM32L052xx, STM32L062xx, STM32L053xx, STM32L063xx. */
/*===========================================================================*/

12
os/hal/ports/STM32/STM32L4xx+/hal_lld.c
View File

@ -348,7 +348,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
/* PLL VCO frequency.*/
vcoclk = (selclk / (halfreq_t)mdiv) * (halfreq_t)ndiv;
if((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) {
if ((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) {
return true;
}
@ -368,7 +368,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLPEN) != 0U) {
pclk = vcoclk / pdiv;
if((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) {
if ((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) {
return true;
}
}
@ -378,7 +378,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLQEN) != 0U) {
qclk = vcoclk / qdiv;
if((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) {
if ((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) {
return true;
}
}
@ -388,7 +388,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLREN) != 0U) {
rclk = vcoclk / rdiv;
if((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) {
if ((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) {
return true;
}
}
@ -502,7 +502,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* SYSCLK frequency.*/
switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case RCC_CFGR_SW_MSI:
sysclk = msiclk;
break;
@ -545,7 +545,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* MCO clock.*/
switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
case STM32_MCOSEL_NOCLOCK:
mcoclk = 0U;
break;

1
os/hal/ports/STM32/STM32L4xx+/stm32_isr.h
View File

@ -160,7 +160,6 @@
#define STM32_I2C4_ERROR_NUMBER 83
#define STM32_I2C4_EVENT_NUMBER 84
/*
* OCTOSPI unit.
*/

2
os/hal/ports/STM32/STM32L5xx/stm32_rcc.h
View File

@ -525,7 +525,7 @@
*
* @api
*/
#define rccResetGTZC() /*rccResetAHB1(RCC_AHB1RST_GTZCRST)*/
#define rccResetGTZC() /* Disabled rccResetAHB1(RCC_AHB1RST_GTZCRST) */
/** @} */
/**

1
os/hal/ports/STM32/STM32MP1xx/hal_lld.h
View File

@ -238,7 +238,6 @@
#define STM32_HSI_ENABLED TRUE
#endif
/**
* @brief HSI divider setting.
* @note This initialization is performed only if TZEN=0 or MCKPROT=0

1
os/hal/ports/STM32/STM32WBxx/hal_lld.h
View File

@ -1251,7 +1251,6 @@
#define STM32_ACTIVATE_PLL FALSE
#endif
/**
* @brief STM32_PLLPEN field.
*/

17
os/hal/ports/STM32/STM32WLxx/hal_lld.c
View File

@ -279,7 +279,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
/* PLL VCO frequency.*/
vcoclk = (selclk / (halfreq_t)mdiv) * (halfreq_t)ndiv;
if((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) {
if ((vcoclk < slp->pllvco_min) || (vcoclk > slp->pllvco_max)) {
return true;
}
@ -291,9 +291,9 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
}
if ((cfgr & RCC_PLLCFGR_PLLPEN) != 0U) {
pclk = vcoclk / pdiv ;
pclk = vcoclk / pdiv;
if((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) {
if ((pclk < slp->pllp_min) || (pclk > slp->pllp_max)) {
return true;
}
}
@ -308,7 +308,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLQEN) != 0U) {
qclk = vcoclk / qdiv;
if((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) {
if ((qclk < slp->pllq_min) || (qclk > slp->pllq_max)) {
return true;
}
}
@ -323,7 +323,7 @@ static bool hal_lld_check_pll(const system_limits_t *slp,
if ((cfgr & RCC_PLLCFGR_PLLREN) != 0U) {
rclk = vcoclk / rdiv;
if((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) {
if ((rclk < slp->pllr_min) || (rclk > slp->pllr_max)) {
return true;
}
}
@ -415,7 +415,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* SYSCLK frequency.*/
switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case STM32_SW_HSI16:
sysclk = hsi16clk;
break;
@ -437,7 +437,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* LPRUN sysclk check.*/
if (((ccp->pwr_cr1 & PWR_CR1_LPR_Msk) != 0U) && (sysclk > STM32_LPRUN_SYSCLK_MAX) ) {
if (((ccp->pwr_cr1 & PWR_CR1_LPR_Msk) != 0U) && (sysclk > STM32_LPRUN_SYSCLK_MAX)) {
return true;
}
@ -469,7 +469,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
hclk3 = sysclk / hprediv[(ccp->rcc_extcfgr & RCC_EXTCFGR_SHDHPRE_Msk) >> RCC_EXTCFGR_SHDHPRE_Pos];
/* MCO clock.*/
switch(ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
case STM32_MCOSEL_NOCLOCK:
mcoclk = 0U;
break;
@ -662,7 +662,6 @@ void hal_lld_init(void) {
irqInit();
}
/**
* @brief STM32WLxx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.

1
os/hal/ports/STM32/STM32WLxx/hal_lld.h
View File

@ -473,7 +473,6 @@
#define STM32_LSI_ENABLED TRUE
#endif
/**
* @brief LSI prescaler value.
*/

2
os/nil/include/ch.h
View File

@ -418,7 +418,7 @@ typedef uint8_t ucnt_t; /**< Generic unsigned counter. */
#error "unsupported PORT_ARCH_REGISTERS_WIDTH value"
#endif
/** @} */
#endif /* defined(PORT_DOES_NOT_PROVIDE_TYPES) */
#endif
#if (CH_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
/**

1
os/oslib/src/chobjcaches.c
View File

@ -200,7 +200,6 @@ static oc_object_t *lru_get_last_s(objects_cache_t *ocp) {
return objp;
}
/* Out of critical section.*/
chSysUnlock();

2
os/rt/include/chearly.h
View File

@ -119,7 +119,7 @@ typedef uint8_t ucnt_t; /**< Generic unsigned counter. */
#error "unsupported PORT_ARCH_REGISTERS_WIDTH value"
#endif
/** @} */
#endif /* defined(PORT_DOES_NOT_PROVIDE_TYPES) */
#endif
/**
* @brief Type of a core identifier.

2
os/rt/include/chsys.h
View File

@ -91,7 +91,7 @@
#else
#define currcore (&ch0)
#endif
#endif /* defined(PORT_INSTANCE_ACCESS) */
#endif
/*===========================================================================*/
/* Module macros. */