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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3811 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2012-01-15 09:37:27 +00:00
parent 17f9264b09
commit e2448aac99
13 changed files with 25 additions and 22 deletions
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6
os/hal/platforms/STM32/i2c_lld.c
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@ -153,8 +153,6 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) {
/* Stops the associated DMA streams.*/ /* Stops the associated DMA streams.*/
dmaStreamDisable(i2cp->dmatx); dmaStreamDisable(i2cp->dmatx);
dmaStreamDisable(i2cp->dmarx); dmaStreamDisable(i2cp->dmarx);
dmaStreamClearInterrupt(i2cp->dmatx);
dmaStreamClearInterrupt(i2cp->dmarx);
} }
/** /**
@ -362,7 +360,6 @@ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
#endif #endif
dmaStreamDisable(i2cp->dmarx); dmaStreamDisable(i2cp->dmarx);
dmaStreamClearInterrupt(i2cp->dmarx);
dp->CR2 &= ~I2C_CR2_LAST; dp->CR2 &= ~I2C_CR2_LAST;
dp->CR1 &= ~I2C_CR1_ACK; dp->CR1 &= ~I2C_CR1_ACK;
@ -390,7 +387,6 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
#endif #endif
dmaStreamDisable(i2cp->dmatx); dmaStreamDisable(i2cp->dmatx);
dmaStreamClearInterrupt(i2cp->dmatx);
/* Enables interrupts to catch BTF event meaning transmission part complete. /* Enables interrupts to catch BTF event meaning transmission part complete.
Interrupt handler will decide to generate STOP or to begin receiving part Interrupt handler will decide to generate STOP or to begin receiving part
of R/W transaction itself.*/ of R/W transaction itself.*/
@ -412,8 +408,6 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp) {
chSysLockFromIsr(); chSysLockFromIsr();
dmaStreamDisable(i2cp->dmatx); dmaStreamDisable(i2cp->dmatx);
dmaStreamDisable(i2cp->dmarx); dmaStreamDisable(i2cp->dmarx);
dmaStreamClearInterrupt(i2cp->dmatx);
dmaStreamClearInterrupt(i2cp->dmarx);
chSysUnlockFromIsr(); chSysUnlockFromIsr();
errors = I2CD_NO_ERROR; errors = I2CD_NO_ERROR;

4
os/hal/platforms/STM32/spi_lld.c
View File

@ -106,11 +106,9 @@ static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
(void)flags; (void)flags;
#endif #endif
/* Stop everything. The status of the TX DMA is cleared here because its /* Stop everything.*/
handler is only invoked in case of error.*/
dmaStreamDisable(spip->dmatx); dmaStreamDisable(spip->dmatx);
dmaStreamDisable(spip->dmarx); dmaStreamDisable(spip->dmarx);
dmaStreamClearInterrupt(spip->dmatx);
/* Portable SPI ISR code defined in the high level driver, note, it is /* Portable SPI ISR code defined in the high level driver, note, it is
a macro.*/ a macro.*/

5
os/hal/platforms/STM32/uart_lld.c
View File

@ -139,9 +139,7 @@ static void usart_stop(UARTDriver *uartp) {
/* Stops RX and TX DMA channels.*/ /* Stops RX and TX DMA channels.*/
dmaStreamDisable(uartp->dmarx); dmaStreamDisable(uartp->dmarx);
dmaStreamClearInterrupt(uartp->dmarx);
dmaStreamDisable(uartp->dmatx); dmaStreamDisable(uartp->dmatx);
dmaStreamClearInterrupt(uartp->dmatx);
/* Stops USART operations.*/ /* Stops USART operations.*/
uartp->usart->CR1 = 0; uartp->usart->CR1 = 0;
@ -534,7 +532,6 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
size_t uart_lld_stop_send(UARTDriver *uartp) { size_t uart_lld_stop_send(UARTDriver *uartp) {
dmaStreamDisable(uartp->dmatx); dmaStreamDisable(uartp->dmatx);
dmaStreamClearInterrupt(uartp->dmatx);
return dmaStreamGetTransactionSize(uartp->dmatx); return dmaStreamGetTransactionSize(uartp->dmatx);
} }
@ -553,7 +550,6 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
/* Stopping previous activity (idle state).*/ /* Stopping previous activity (idle state).*/
dmaStreamDisable(uartp->dmarx); dmaStreamDisable(uartp->dmarx);
dmaStreamClearInterrupt(uartp->dmarx);
/* RX DMA channel preparation and start.*/ /* RX DMA channel preparation and start.*/
dmaStreamSetMemory0(uartp->dmarx, rxbuf); dmaStreamSetMemory0(uartp->dmarx, rxbuf);
@ -578,7 +574,6 @@ size_t uart_lld_stop_receive(UARTDriver *uartp) {
size_t n; size_t n;
dmaStreamDisable(uartp->dmarx); dmaStreamDisable(uartp->dmarx);
dmaStreamClearInterrupt(uartp->dmarx);
n = dmaStreamGetTransactionSize(uartp->dmarx); n = dmaStreamGetTransactionSize(uartp->dmarx);
set_rx_idle_loop(uartp); set_rx_idle_loop(uartp);
return n; return n;

2
os/hal/platforms/STM32F1xx/hal_lld_f100.h
View File

@ -169,12 +169,12 @@
#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ #define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ #define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ #define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ #define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as #define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
RTC clock. */ RTC clock. */
#define STM32_RTCSEL_MSK (3 << 8) /**< RTC clock source mask. */
/** @} */ /** @} */
/*===========================================================================*/ /*===========================================================================*/

2
os/hal/platforms/STM32F1xx/hal_lld_f103.h
View File

@ -179,12 +179,12 @@
#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ #define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ #define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ #define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ #define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as #define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
RTC clock. */ RTC clock. */
#define STM32_RTCSEL_MSK (3 << 8) /**< RTC clock source mask. */
/** @} */ /** @} */
/*===========================================================================*/ /*===========================================================================*/

2
os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
View File

@ -189,12 +189,12 @@
#define STM32_MCOSEL_XT1 (10 << 24) /**< XT1 clock on MCO pin. */ #define STM32_MCOSEL_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
#define STM32_MCOSEL_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */ #define STM32_MCOSEL_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */ #define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */ #define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ #define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as #define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
RTC clock. */ RTC clock. */
#define STM32_RTCSEL_MSK (3 << 8) /**< RTC clock source mask. */
/** @} */ /** @} */
/** /**

5
os/hal/platforms/STM32F1xx/stm32_dma.h
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@ -299,6 +299,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/** /**
* @brief DMA stream disable. * @brief DMA stream disable.
* @details The function disables the specified stream and then clears any
* pending interrupt.
* @note This function can be invoked in both ISR or thread context. * @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate(). * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease(). * @post After use the stream can be released using @p dmaStreamRelease().
@ -308,7 +310,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @special * @special
*/ */
#define dmaStreamDisable(dmastp) { \ #define dmaStreamDisable(dmastp) { \
(dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \ (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \
dmaStreamClearInterrupt(dmastp); \
} }
/** /**

2
os/hal/platforms/STM32F2xx/hal_lld.c
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@ -50,7 +50,7 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0; RCC->BDCR = 0;

5
os/hal/platforms/STM32F2xx/stm32_dma.h
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@ -352,6 +352,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/** /**
* @brief DMA stream disable. * @brief DMA stream disable.
* @details The function disables the specified stream, waits for the disable
* operation to complete and then clears any pending interrupt.
* @note This function can be invoked in both ISR or thread context. * @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate(). * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease(). * @post After use the stream can be released using @p dmaStreamRelease().
@ -362,6 +364,9 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
*/ */
#define dmaStreamDisable(dmastp) { \ #define dmaStreamDisable(dmastp) { \
(dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \ (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \
while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \
; \
dmaStreamClearInterrupt(dmastp); \
} }
/** /**

2
os/hal/platforms/STM32F4xx/hal_lld.c
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@ -50,7 +50,7 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0; RCC->BDCR = 0;

5
os/hal/platforms/STM32F4xx/stm32_dma.h
View File

@ -352,6 +352,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/** /**
* @brief DMA stream disable. * @brief DMA stream disable.
* @details The function disables the specified stream, waits for the disable
* operation to complete and then clears any pending interrupt.
* @note This function can be invoked in both ISR or thread context. * @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate(). * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease(). * @post After use the stream can be released using @p dmaStreamRelease().
@ -362,6 +364,9 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
*/ */
#define dmaStreamDisable(dmastp) { \ #define dmaStreamDisable(dmastp) { \
(dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \ (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \
while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \
; \
dmaStreamClearInterrupt(dmastp); \
} }
/** /**

2
os/hal/platforms/STM32L1xx/hal_lld.c
View File

@ -50,7 +50,7 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->CSR & STM32_RTCSEL_MSK) != STM32_RTCSEL){ if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->CSR |= RCC_CSR_RTCRST; RCC->CSR |= RCC_CSR_RTCRST;
RCC->CSR &= ~RCC_CSR_RTCRST; RCC->CSR &= ~RCC_CSR_RTCRST;

5
os/hal/platforms/STM32L1xx/stm32_dma.h
View File

@ -290,6 +290,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/** /**
* @brief DMA stream disable. * @brief DMA stream disable.
* @details The function disables the specified stream and then clears any
* pending interrupt.
* @note This function can be invoked in both ISR or thread context. * @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate(). * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease(). * @post After use the stream can be released using @p dmaStreamRelease().
@ -299,7 +301,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @special * @special
*/ */
#define dmaStreamDisable(dmastp) { \ #define dmaStreamDisable(dmastp) { \
(dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \ (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \
dmaStreamClearInterrupt(dmastp); \
} }
/** /**