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ChibiOS
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Test suite passed. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16385 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2023-09-03 10:46:53 +00:00
parent 304755712b
commit e5866d5023
7 changed files with 103 additions and 19 deletions
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2
demos/STM32/RT-STM32H563ZI-NUCLEO144/Makefile
View File

@ -5,7 +5,7 @@
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).

16
demos/STM32/RT-STM32H563ZI-NUCLEO144/main.c
View File

@ -28,10 +28,18 @@ static THD_FUNCTION(Thread1, arg) {
(void)arg;
chRegSetThreadName("blinker");
while (true) {
palClearLine(LINE_LED_GREEN);
chThdSleepMilliseconds(500);
palSetLine(LINE_LED_GREEN);
chThdSleepMilliseconds(500);
palSetLine(LINE_LED1);
chThdSleepMilliseconds(50);
palSetLine(LINE_LED2);
chThdSleepMilliseconds(50);
palSetLine(LINE_LED3);
chThdSleepMilliseconds(200);
palClearLine(LINE_LED1);
chThdSleepMilliseconds(50);
palClearLine(LINE_LED2);
chThdSleepMilliseconds(50);
palClearLine(LINE_LED3);
chThdSleepMilliseconds(200);
}
}

4
os/hal/boards/ST_NUCLEO144_H563ZI/board.c
View File

@ -155,8 +155,8 @@ static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB4(STM32_GPIO_EN_MASK);
rccEnableAHB4(STM32_GPIO_EN_MASK, true);
rccResetAHB2(STM32_GPIO_EN_MASK);
rccEnableAHB2(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA

20
os/hal/ports/STM32/STM32H5xx/stm32_rcc.h
View File

@ -233,10 +233,10 @@
#define rccEnableAHB1(mask, lp) { \
RCC->AHB1ENR |= (mask); \
if (lp) \
RCC->AHB1SMENR |= (mask); \
RCC->AHB1LPENR |= (mask); \
else \
RCC->AHB1SMENR &= ~(mask); \
(void)RCC->AHB1SMENR; \
RCC->AHB1LPENR &= ~(mask); \
(void)RCC->AHB1LPENR; \
}
/**
@ -248,8 +248,8 @@
*/
#define rccDisableAHB1(mask) { \
RCC->AHB1ENR &= ~(mask); \
RCC->AHB1SMENR &= ~(mask); \
(void)RCC->AHB1SMENR; \
RCC->AHB1LPENR &= ~(mask); \
(void)RCC->AHB1LPENR; \
}
/**
@ -276,10 +276,10 @@
#define rccEnableAHB2(mask, lp) { \
RCC->AHB2ENR |= (mask); \
if (lp) \
RCC->AHB2SMENR |= (mask); \
RCC->AHB2LPENR |= (mask); \
else \
RCC->AHB2SMENR &= ~(mask); \
(void)RCC->AHB2SMENR; \
RCC->AHB2LPENR &= ~(mask); \
(void)RCC->AHB2LPENR; \
}
/**
@ -291,8 +291,8 @@
*/
#define rccDisableAHB2(mask) { \
RCC->AHB2ENR &= ~(mask); \
RCC->AHB2SMENR &= ~(mask); \
(void)RCC->AHB2SMENR; \
RCC->AHB2LPENR &= ~(mask); \
(void)RCC->AHB2LPENR; \
}
/**

74
os/xhal/ports/vio/hal_spi_lld.c
View File

@ -80,6 +80,47 @@ static inline uint32_t __spi_vspi_setcfg(uint32_t nvuart, uint32_t ncfg) {
return (uint32_t)r0;
}
/**
* @brief Shared end-of-rx service routine.
*
* @param[in] spip pointer to the @p SPIDriver object
*/
static void sio_lld_serve_interrupt(SPIDriver *spip) {
/* DMA errors handling.*/
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
#if defined(STM32_SPI_DMA_ERROR_HOOK)
/* Hook first, if defined.*/
STM32_SPI_DMA_ERROR_HOOK(spip);
#endif
/* Stopping DMAs.*/
dmaStreamDisable(spip->dmatx);
dmaStreamDisable(spip->dmarx);
/* Reporting the failure.*/
spip->sts |= SPI_STS_FAILED | SPI_STS_RXDMA_FAIL;
__spi_isr_error_code(spip, HAL_RET_HW_FAILURE);
}
else if ((__spi_getfield(spip, mode) & SPI_MODE_CIRCULAR) != 0U) {
if ((flags & STM32_DMA_ISR_HTIF) != 0U) {
/* Half buffer interrupt.*/
__spi_isr_half_code(spip);
}
if ((flags & STM32_DMA_ISR_TCIF) != 0U) {
/* End buffer interrupt.*/
__spi_isr_full_code(spip);
}
}
else {
/* Stopping DMAs.*/
dmaStreamDisable(spip->dmatx);
dmaStreamDisable(spip->dmarx);
/* Operation finished interrupt.*/
__spi_isr_complete_code(spip);
}
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@ -124,11 +165,13 @@ void spi_lld_init(void) {
/* Driver instances initialization.*/
#if SB_SPI_USE_VSPI1 == TRUE
sioObjectInit(&SPID1);
SPID1.sts = 0U;
SPID1.nvuart = 0U;
__sb_vrq_seten(1U << VIO_VSPI1_IRQ);
#endif
#if SB_SPI_USE_VSPI2 == TRUE
sioObjectInit(&SPID2);
SPID2.sts = 0U;
SPID2.nvuart = 1U;
__sb_vrq_seten(1U << VIO_VSPI2_IRQ);
#endif
@ -162,6 +205,9 @@ msg_t spi_lld_start(SPIDriver *spip) {
osalDbgAssert(false, "invalid SPI instance");
}
/* Status cleared.*/
spip->sts = (drv_status_t)0;
/* Configures the peripheral.*/
spi_lld_configure(spip, &default_config);
@ -222,6 +268,10 @@ const hal_spi_config_t *spi_lld_configure(hal_spi_driver_c *spip,
*/
drv_status_t spi_lld_get_status(hal_spi_driver_c *spip) {
__syscall1r(98, VIO_CALL(SB_VSPI_GETSTS, siop->nvuart));
osalDbgAssert(r0 != (uint32_t)-1, "unexpected failure");
return (sioevents_t)r0;
}
/**
@ -235,6 +285,10 @@ drv_status_t spi_lld_get_status(hal_spi_driver_c *spip) {
drv_status_t spi_lld_get_clear_status(hal_spi_driver_c *spip,
drv_status_t mask) {
__syscall2r(226, VIO_CALL(SB_VSPI_GETCLRSTS, spip->nvspi), mask);
osalDbgAssert(r0 != (uint32_t)-1, "unexpected failure");
return (sioevents_t)r0;
}
#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__)
@ -279,6 +333,10 @@ void spi_lld_unselect(SPIDriver *spip) {
*/
msg_t spi_lld_ignore(SPIDriver *spip, size_t n) {
__syscall2r(226, VIO_CALL(SB_VSPI_PULSES, spip->nvspi), n);
osalDbgAssert(r0 != (uint32_t)-1, "unexpected failure");
return (sioevents_t)r0;
}
/**
@ -300,6 +358,10 @@ msg_t spi_lld_ignore(SPIDriver *spip, size_t n) {
msg_t spi_lld_exchange(SPIDriver *spip, size_t n,
const void *txbuf, void *rxbuf) {
__syscall4r(226, VIO_CALL(SB_VSPI_EXCHANGE, spip->nvspi), n, txbuf, rxbuf);
osalDbgAssert(r0 != (uint32_t)-1, "unexpected failure");
return (sioevents_t)r0;
}
/**
@ -318,6 +380,10 @@ msg_t spi_lld_exchange(SPIDriver *spip, size_t n,
*/
msg_t spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
__syscall3r(226, VIO_CALL(SB_VSPI_SEND, spip->nvspi), n, txbuf);
osalDbgAssert(r0 != (uint32_t)-1, "unexpected failure");
return (sioevents_t)r0;
}
/**
@ -336,6 +402,10 @@ msg_t spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
*/
msg_t spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
__syscall3r(226, VIO_CALL(SB_VSPI_RECEIVE, spip->nvspi), n, rxbuf);
osalDbgAssert(r0 != (uint32_t)-1, "unexpected failure");
return (sioevents_t)r0;
}
/**
@ -350,6 +420,10 @@ msg_t spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
*/
msg_t spi_lld_stop_transfer(SPIDriver *spip, size_t *sizep) {
__syscall2r(226, VIO_CALL(SB_VSPI_STOP, spip->nvspi), sizep);
osalDbgAssert(r0 != (uint32_t)-1, "unexpected failure");
return (sioevents_t)r0;
}
/**

2
os/xhal/ports/vio/hal_spi_lld.h
View File

@ -88,6 +88,8 @@
* @brief Low level fields of the SPI driver structure.
*/
#define spi_lld_driver_fields \
/* Driver status.*/ \
drv_status_t sts; \
/* Number of the associated VSPI.*/ \
uint32_t nvspi

4
tools/ftl/processors/boards/stm32h5xx/templates/board.c.ftl
View File

@ -169,8 +169,8 @@ static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB4(STM32_GPIO_EN_MASK);
rccEnableAHB4(STM32_GPIO_EN_MASK, true);
rccResetAHB2(STM32_GPIO_EN_MASK);
rccEnableAHB2(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA