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Experimental clock tree generator. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14924 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-10-20 14:38:35 +00:00
parent 30ec4bd812
commit e703a98d9e
3 changed files with 258 additions and 0 deletions
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104
os/hal/ports/STM32/STM32G4xx/cfg/clocktree.xml Normal file
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<clocktree>
<settings>
<prefixes name="CLK_" />
<postfixes values="_VALUE" clocks="_FREQ" choices="_SEL" bits="_BITS" switches="_ENABLE" />
<constants false="FALSE" true="TRUE" />
</settings>
<clocks>
<clock name="NONE">
<description>no clock</description>
<expr frequency="0U" />
</clock>
<clock name="HSI16">
<description>16MHz high speed internal oscillator</description>
<expr frequency="16000000U" optional="yes" />
</clock>
<clock name="HSI48">
<description>48MHz high speed internal oscillator</description>
<expr frequency="48000000U" optional="yes" />
</clock>
<clock name="HSE">
<description>high frequency external oscillator</description>
<expr frequency="STM32_HSECLK" optional="yes" />
</clock>
<clock name="LSE">
<description>low frequency external oscillator</description>
<expr frequency="STM32_LSECLK" optional="yes" />
</clock>
<clock name="LSI">
<description>low frequency internal oscillator</description>
<expr frequency="32768U" optional="yes" />
</clock>
<clock name="PLLIN">
<description>PLL input</description>
<mux name="PLLSRC">
<input ref="NONE" bits="(0U &lt;&lt; 4)" />
<input ref="NONE" bits="(1U &lt;&lt; 4)" />
<input ref="HSI16" bits="(2U &lt;&lt; 4)" />
<input ref="HSE" bits="(3U &lt;&lt; 4)" />
</mux>
</clock>
<clock name="PLLREF">
<description>PLL reference</description>
<divide_range name="PLLM" min="1" max="16" bits="((%PLLM% - 1U) &lt;&lt; 4)" />
</clock>
<clock name="PLLVCO">
<description>PLL VCO</description>
<multiply_value name="PLLN" min="8" max="127" bits="(%PLLN% &lt;&lt; 8)" />
</clock>
<clock name="PLLP" optional="yes">
<description>PLL P output</description>
<divide_range name="PLLP" min="2" max="31" bits="(%PLLP% &lt;&lt; 27)"/>
</clock>
<clock name="PLLQ" optional="yes">
<description>PLL Q output</description>
<divide_set name="PLLQ" allowed="2U 4U 6U 8U" bits="(((%PLLQ% / 2U) - 1U) &lt;&lt; 21)" />
</clock>
<clock name="PLLR" optional="yes">
<description>PLL R output</description>
<divide_set name="PLLR" allowed="2U 4U 6U 8U" bits="(((%PLLR% / 2U) - 1U) &lt;&lt; 25)" />
</clock>
<clock name="SYSCLK">
<description>system clock</description>
<mux name="SW">
<input ref="HSI16" bits="(1U &lt;&lt; 0)" />
<input ref="HSE" bits="(2U &lt;&lt; 0)" />
<input ref="PLLR" bits="(3U &lt;&lt; 0)" />
</mux>
</clock>
<clock name="HCLK">
<description>AHB</description>
<divide_choices name="HPRE">
<choice name="DIV1" value="1U" bits="(1U &lt;&lt; 4)" />
<choice name="DIV2" value="2U" bits="(8U &lt;&lt; 4)" />
<choice name="DIV4" value="4U" bits="(9U &lt;&lt; 4)" />
<choice name="DIV8" value="8U" bits="(10U &lt;&lt; 4)" />
<choice name="DIV16" value="16U" bits="(11U &lt;&lt; 4)" />
<choice name="DIV64" value="64U" bits="(12U &lt;&lt; 4)" />
<choice name="DIV128" value="128U" bits="(13U &lt;&lt; 4)" />
<choice name="DIV256" value="256U" bits="(14U &lt;&lt; 4)" />
<choice name="DIV512" value="512U" bits="(15U &lt;&lt; 4)" />
</divide_choices>
</clock>
<clock name="PCLK1">
<description>APB1</description>
<divide_choices name="PPRE1">
<choice name="DIV1" value="1U" bits="(1U &lt;&lt; 8)" />
<choice name="DIV2" value="2U" bits="(4U &lt;&lt; 8)" />
<choice name="DIV4" value="4U" bits="(5U &lt;&lt; 8)" />
<choice name="DIV8" value="8U" bits="(6U &lt;&lt; 8)" />
<choice name="DIV16" value="16U" bits="(7U &lt;&lt; 8)" />
</divide_choices>
</clock>
<clock name="PCLK2">
<description>APB2</description>
<divide_choices name="PPRE2">
<choice name="DIV1" value="1U" bits="(1U &lt;&lt; 11)" />
<choice name="DIV2" value="2U" bits="(4U &lt;&lt; 11)" />
<choice name="DIV4" value="4U" bits="(5U &lt;&lt; 11)" />
<choice name="DIV8" value="8U" bits="(6U &lt;&lt; 11)" />
<choice name="DIV16" value="16U" bits="(7U &lt;&lt; 11)" />
</divide_choices>
</clock>
</clocks>
</clocktree>

15
os/hal/ports/STM32/STM32G4xx/cfg/config.fmpp Normal file
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sourceRoot: ../../../../../../tools/ftl/processors/clocktree
outputRoot: ..
dataRoot: .
freemarkerLinks: {
lib: ../../../../../../tools/ftl/libs
}
data : {
doc1:xml (
clocktree.xml
{
}
)
}

139
tools/ftl/processors/clocktree/clocktree.h.ftl Normal file
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[#ftl]
[#--
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio.
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--]
[@pp.dropOutputFile /]
[#import "/@lib/libutils.ftl" as utils /]
[#import "/@lib/liblicense.ftl" as license /]
[@pp.changeOutputFile name="clocktree.h" /]
[#-- Getting various constants.--]
[#assign prename = doc1.clocktree.settings.prefixes.@name[0]?string /]
[#assign postvalues = doc1.clocktree.settings.postfixes.@values[0]?string /]
[#assign postclocks = doc1.clocktree.settings.postfixes.@clocks[0]?string /]
[#assign postchoices = doc1.clocktree.settings.postfixes.@choices[0]?string /]
[#assign postbits = doc1.clocktree.settings.postfixes.@bits[0]?string /]
[#assign postswitches = doc1.clocktree.settings.postfixes.@switches[0]?string /]
[#assign constfalse = doc1.clocktree.settings.constants.@false[0]?string /]
[#assign consttrue = doc1.clocktree.settings.constants.@true[0]?string /]
[#-- Sequence of the calculated clock points.--]
[#assign clocks_expr = [] /]
[#-- Sequence of the muxed clock points.--]
[#assign clocks_mux = [] /]
[#-- Scanning clock points, gathering data.--]
[#list doc1.clocktree.clocks.clock as clock]
[#assign clockname = clock.@name[0] /]
[#if clock.description[0]??]
[#assign clockdescr = clock.description[0]?string?word_list?join(" ") /]
[#else /]
[#assign clockdescr = "no description" /]
[/#if]
[#-- Determining the type of the clock point by looking at the child element.--]
[#if clock.expr[0]??]
[#-- It is a calculated clock.--]
[#assign clockfreq = clock.expr[0].@frequency[0]?string /]
[#assign clocks_expr = clocks_expr + [{"description":clockdescr,
"name":clockname,
"frequency":clockfreq}] /]
[#elseif clock.mux[0]??]
[#-- It is a muxed clock.--]
[#assign muxname = clock.mux[0].@name[0] /]
[#assign inputs = [] /]
[#list clock.mux.input as input]
[#assign inputref = input.@ref[0] /]
[#assign inputbits = input.@bits[0]!"" /]
[#assign inputs = inputs + [{"name":inputref, "bits":inputbits}] /]
[/#list]
[#assign clocks_mux = clocks_mux + [{"name":clockname,
"muxname":muxname,
"inputs":inputs}] /]
[/#if]
[/#list]
/*
[@license.EmitLicenseAsText /]
*/
/**
* @file clocktree.h
* @brief Generated clock tree description header.
*
* @addtogroup CLOCKTREE
* @{
*/
#ifndef CLOCKTREE_H
#define CLOCKTREE_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Mux configurations
* @{
*/
[#list clocks_mux as mux]
[#assign name = prename + mux["name"] + postchoices/]
#if !defined(name) || defined(__DOXYGEN__)
${("#define " + name)?right_pad(44) + prename + mux["name"] + "_" + mux["inputs"][0]["name"]}
#endif
[/#list]
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Calculated or fixed clocks
* @{
*/
[#list clocks_expr as clock]
/**
* @brief ${clock["description"]?cap_first} clock point.
*/
${("#define " + prename + clock["name"] + postclocks)?right_pad(44) + clock["frequency"]}
[/#list]
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* CLOCKTREE_H */
/** @} */