andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

#1117 #4. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13781 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-07-24 08:49:43 +00:00
parent 7fd2a32106
commit fcb6bb7085
2 changed files with 38 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
View File

@ -350,7 +350,42 @@
#error "Invalid IRQ priority assigned to ADC3" #error "Invalid IRQ priority assigned to ADC3"
#endif #endif
#if !defined(STM32_ENFORCE_H7_REV_XY)
/* ADC clock source checks.*/ /* ADC clock source checks.*/
#if (STM32_D1HPRE == STM32_D1HPRE_DIV1)
#define STM32_ADC_SCLK STM32_SYSCLK
#else
#define STM32_ADC_SCLK (STM32_SYSCLK / 2)
#endif
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
/* CHTODO: also check ADC_CCR_PRESC.*/
#define STM32_ADC12_CLOCK (STM32_ADCCLK / 2)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC12_CLOCK (STM32_ADC_SCLK / 1 / 2)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC12_CLOCK (STM32_ADC_SCLK / 2 / 2)
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC12_CLOCK (STM32_ADC_SCLK / 4 / 2)
#else
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
#endif
#if STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
/* CHTODO: also check ADC_CCR_PRESC.*/
#define STM32_ADC3_CLOCK (STM32_ADCCLK / 2)
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC3_CLOCK (STM32_ADC_SCLK / 1 / 2)
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC3_CLOCK (STM32_ADC_SCLK / 2 / 2)
#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC3_CLOCK (STM32_ADC_SCLK / 4 / 2)
#else
#error "invalid clock mode selected for STM32_ADC_ADC3_CLOCK_MODE"
#endif
#else /* defined(STM32_ENFORCE_H7_REV_XY) */
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK #if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
#define STM32_ADC12_CLOCK STM32_ADCCLK #define STM32_ADC12_CLOCK STM32_ADCCLK
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 #elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
@ -375,6 +410,8 @@
#error "invalid clock mode selected for STM32_ADC_ADC3_CLOCK_MODE" #error "invalid clock mode selected for STM32_ADC_ADC3_CLOCK_MODE"
#endif #endif
#endif /* defined(STM32_ENFORCE_H7_REV_XY) */
#if STM32_ADC12_CLOCK > STM32_ADCCLK_MAX #if STM32_ADC12_CLOCK > STM32_ADCCLK_MAX
#error "STM32_ADC12_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)" #error "STM32_ADC12_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
#endif #endif

2
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -212,7 +212,7 @@
/** /**
* @brief Maximum ADC clock frequency. * @brief Maximum ADC clock frequency.
*/ */
#define STM32_ADCCLK_MAX 100000000 #define STM32_ADCCLK_MAX 50000000
/** @} */ /** @} */
#else /* defined(STM32_ENFORCE_H7_REV_XY) */ #else /* defined(STM32_ENFORCE_H7_REV_XY) */