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rusefi
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build tweaks for size (#4661) 

* don't align on non-cached mcu

* lua decimal point

* no snprintf

* sort sections by alignment

* unit tests
This commit is contained in:
Matthew Kennedy 2022-10-13 17:30:30 -07:00 committed by GitHub
parent fab95bd890
commit 1ae642e7a7
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 12 additions and 4 deletions
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4
firmware/Makefile
View File

@ -58,7 +58,7 @@ endif
# yes we have two kinds of EXTRA_*PARAMS so that we can define those in two different places independently
#
ifeq ($(USE_OPT),)
USE_OPT = $(EXTRA_PARAMS) $(EXTRA_2_PARAMS) $(DEBUG_LEVEL_OPT) $(RFLAGS) -fomit-frame-pointer -falign-functions=16 -fsingle-precision-constant -fno-inline-functions
USE_OPT = $(EXTRA_PARAMS) $(EXTRA_2_PARAMS) $(DEBUG_LEVEL_OPT) $(RFLAGS) -fomit-frame-pointer -fsingle-precision-constant -fno-inline-functions
endif
# EFI_UNIT_TEST determines if we are running in a unit test (hide things from hw/sim)
@ -368,7 +368,7 @@ UINCDIR =
ULIBDIR =
# List all user libraries here
ULIBS = -lm --specs=nano.specs
ULIBS = -lm --specs=nano.specs -Wl,--sort-section=alignment
#
# End of user defines

2
firmware/controllers/algo/engine_configuration.cpp
View File

@ -344,7 +344,7 @@ void setDefaultGppwmParameters() {
// Same config for all channels
for (size_t i = 0; i < efi::size(engineConfiguration->gppwm); i++) {
auto& cfg = engineConfiguration->gppwm[i];
snprintf(engineConfiguration->gpPwmNote[i], sizeof(engineConfiguration->gpPwmNote[0]), "GPPWM%d", i);
chsnprintf(engineConfiguration->gpPwmNote[i], sizeof(engineConfiguration->gpPwmNote[0]), "GPPWM%d", i);
cfg.pin = Gpio::Unassigned;
cfg.dutyIfError = 0;

2
firmware/controllers/lua/luaconf.h
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@ -447,7 +447,7 @@ float strtof_rusefi(const char*, char**);
** macro must include the header 'locale.h'.)
*/
#if !defined(lua_getlocaledecpoint)
#define lua_getlocaledecpoint() (localeconv()->decimal_point[0])
#define lua_getlocaledecpoint() '.'
#endif

3
firmware/hw_layer/ports/stm32/stm32f7/hw_ports.mk
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@ -6,6 +6,9 @@ HW_LAYER_EMS += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/stm32f7xx_hal_flash.
HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/mpu_util.cpp \
$(PROJECT_DIR)/hw_layer/ports/stm32/stm32_adc_v2.cpp \
# This MCU has a cache, align functions to a cache line for maximum cache efficiency
USE_OPT += -falign-functions=16
DDEFS += -DSTM32F767xx
MCU = cortex-m7
LDSCRIPT = $(PROJECT_DIR)/hw_layer/ports/stm32/stm32f7/STM32F7.ld

3
firmware/hw_layer/ports/stm32/stm32h7/hw_ports.mk
View File

@ -6,6 +6,9 @@ HW_LAYER_EMS += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/stm32h7xx_hal_flash.
HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/mpu_util.cpp \
$(PROJECT_DIR)/hw_layer/ports/stm32/stm32_adc_v4.cpp \
# This MCU has a cache, align functions to a cache line for maximum cache efficiency
USE_OPT += -falign-functions=16
DDEFS += -DSTM32H743xx
MCU = cortex-m7
LDSCRIPT = $(PROJECT_DIR)/hw_layer/ports/stm32/stm32h7/STM32H743xI.ld

2
unit_tests/global.h
View File

@ -75,3 +75,5 @@ namespace chibios_rt {
#endif
#define UNIT_TEST_BUSY_WAIT_CALLBACK() { timeNowUs++; }
#define chsnprintf snprintf