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AT32F435_437_Firmware_Library
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update version to v2.1.0

This commit is contained in:
Artery-MCU 2022-08-26 14:56:40 +08:00
parent 60161fc869
commit 861b32d397
3367 changed files with 38082 additions and 11153 deletions
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document/AT32F435_437固件库BSP&Pack应用指南.pdf
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document/ReleaseNotes_AT32F435_437_Firmware_Library.pdf
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libraries/cmsis/cm4/device_support/at32f435_437.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 header file
**************************************************************************
* Copyright notice & Disclaimer
@ -99,8 +99,8 @@ extern "C" {
* @brief at32f435_437 standard peripheral library version number
*/
#define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x09) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x00) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \

4
libraries/cmsis/cm4/device_support/at32f435_437_conf_template.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_conf.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 config header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/cmsis/cm4/device_support/startup/gcc/startup_at32f435_437.s
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@ -1,8 +1,8 @@
/**
******************************************************************************
* @file startup_at32f435_437.s
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 devices vector table for gcc toolchain.
* this module performs:
* - set the initial sp

4
libraries/cmsis/cm4/device_support/startup/iar/startup_at32f435_437.s
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@ -1,7 +1,7 @@
;**************************************************************************
;* @file startup_at32f435_437.s
;* @version v2.0.9
;* @date 2022-06-28
;* @version v2.1.0
;* @date 2022-08-16
;* @brief at32f435_437 startup file for IAR Systems
;**************************************************************************
;

5
libraries/cmsis/cm4/device_support/startup/mdk/startup_at32f435_437.s
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@ -1,8 +1,9 @@
;**************************************************************************
;* @file startup_at32f435_437.s
;* @version v2.0.9
;* @date 2022-06-28
;* @version v2.1.0
;* @date 2022-08-16
;* @brief at32f435_437 startup file for keil
;* <<< Use Configuration Wizard in Context Menu >>>
;**************************************************************************
;

4
libraries/cmsis/cm4/device_support/system_at32f435_437.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file system_at32f435_437.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for cmsis cortex-m4 system source file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/cmsis/cm4/device_support/system_at32f435_437.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file system_at32f435_437.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief cmsis cortex-m4 system header file.
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/cmsis/dsp/PrivateInclude/arm_sorting.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_sorting.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief Private header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/cmsis/dsp/PrivateInclude/arm_vec_fft.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_vec_fft.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief Private header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/cmsis/dsp/PrivateInclude/arm_vec_filtering.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_vec_filtering.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief Private header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/cmsis/dsp/include/arm_math.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_math.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief Public header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/cmsis/dsp/include/arm_vec_math.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_vec_math.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief Public header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/drivers/inc/at32f435_437_acc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_acc.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 acc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_adc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_adc.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 adc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_can.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_can.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 can header file
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/inc/at32f435_437_crc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crc.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 crc header file
**************************************************************************
* Copyright notice & Disclaimer
@ -148,7 +148,7 @@ uint32_t crc_one_word_calculate(uint32_t data);
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
uint32_t crc_data_get(void);
void crc_common_data_set(uint8_t cdt_value);
uint8_t crc_common_date_get(void);
uint8_t crc_common_data_get(void);
void crc_init_data_set(uint32_t value);
void crc_reverse_input_data_set(crc_reverse_input_type value);
void crc_reverse_output_data_set(crc_reverse_output_type value);

10
libraries/drivers/inc/at32f435_437_crm.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crm.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 crm header file
**************************************************************************
* Copyright notice & Disclaimer
@ -398,6 +398,9 @@ typedef enum
CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */
CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */
CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */
CRM_FLASH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 15), /*!< flash sleep mode periph clock */
CRM_SRAM1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 16), /*!< sram1 sleep mode periph clock */
CRM_SRAM2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 17), /*!< sram2 sleep mode periph clock */
CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
@ -470,6 +473,9 @@ typedef enum
CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */
CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */
CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */
CRM_FLASH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 15), /*!< flash sleep mode periph clock */
CRM_SRAM1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 16), /*!< sram1 sleep mode periph clock */
CRM_SRAM2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 17), /*!< sram2 sleep mode periph clock */
CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */

4
libraries/drivers/inc/at32f435_437_dac.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dac.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 dac header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_debug.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_mcudbg.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 mcudbg header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_def.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_def.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 macros header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_dma.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dma.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 dma header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_dvp.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dvp.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 dvp header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_edma.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_edma.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 edma header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_emac.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_emac.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 eth header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_ertc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_ertc.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 ertc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_exint.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_exint.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 exint header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_flash.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_flash.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 flash header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_gpio.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_gpio.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 gpio header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_i2c.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_i2c.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 i2c header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_misc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_misc.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 misc header file
**************************************************************************
* Copyright notice & Disclaimer

16
libraries/drivers/inc/at32f435_437_pwc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_pwc.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 pwr header file
**************************************************************************
* Copyright notice & Disclaimer
@ -67,10 +67,12 @@ extern "C" {
* @brief select ldo output voltage.
* @param val: set the ldo output voltage.
* this parameter can be one of the following values:
* - PWC_LDO_OUTPUT_1V2
* - PWC_LDO_OUTPUT_1V3
* - PWC_LDO_OUTPUT_1V1
* - PWC_LDO_OUTPUT_1V0
* - PWC_LDO_OUTPUT_1V3: system clock up to 288MHz.
* - PWC_LDO_OUTPUT_1V2: system clock up to 240MHz.
* - PWC_LDO_OUTPUT_1V1: system clock up to 192MHz.
* - PWC_LDO_OUTPUT_1V0: system clock up to 144MHz.
* @note useage limited.
* PWC_LDO_OUTPUT_1V3: operation temperature range -40~85 degree, VDD must over 3.0V.
*/
#define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val)
@ -97,8 +99,8 @@ typedef enum
*/
typedef enum
{
PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */
PWC_LDO_OUTPUT_1V3 = 0x01, /*!< ldo output voltage is 1.3v */
PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */
PWC_LDO_OUTPUT_1V1 = 0x04, /*!< ldo output voltage is 1.1v */
PWC_LDO_OUTPUT_1V0 = 0x05, /*!< ldo output voltage is 1.0v */
} pwc_ldo_output_voltage_type;

4
libraries/drivers/inc/at32f435_437_qspi.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_qspi.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 qspi header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_scfg.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_scfg.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 system config header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_sdio.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_sdio.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 sdio header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_spi.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_spi.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 spi header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_tmr.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_tmr.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 tmr header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_usart.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usart.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 usart header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_usb.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usb.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 usb header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_wdt.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wdt.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 wdt header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_wwdt.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wwdt.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_xmc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_xmc.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief at32f435_437 xmc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_acc.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_acc.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the acc firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_adc.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_adc.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the adc firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_can.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_can.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the can firmware library
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/src/at32f435_437_crc.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crc.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the crc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -106,7 +106,7 @@ void crc_common_data_set(uint8_t cdt_value)
* @param none
* @retval 8-bit value of the common data register
*/
uint8_t crc_common_date_get(void)
uint8_t crc_common_data_get(void)
{
return (CRC->cdt_bit.cdt);
}

5
libraries/drivers/src/at32f435_437_crm.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crm.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the crm firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -282,6 +282,7 @@ void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
* - CRM_USART6_PERIPH_LOWPOWER - CRM_ADC1_PERIPH_LOWPOWER - CRM_ADC2_PERIPH_LOWPOWER - CRM_ADC3_PERIPH_LOWPOWER
* - CRM_SPI1_PERIPH_LOWPOWER - CRM_SPI4_PERIPH_LOWPOWER - CRM_SCFG_PERIPH_LOWPOWER - CRM_TMR9_PERIPH_LOWPOWER
* - CRM_TMR10_PERIPH_LOWPOWER - CRM_TMR11_PERIPH_LOWPOWER - CRM_TMR20_PERIPH_LOWPOWER - CRM_ACC_PERIPH_LOWPOWER
* - CRM_FLASH_PERIPH_LOWPOWER - CRM_SRAM1_PERIPH_LOWPOWER - CRM_SRAM2_PERIPH_LOWPOWER
* @param new_state (TRUE or FALSE)
* @retval none
*/

4
libraries/drivers/src/at32f435_437_dac.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dac.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the dac firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_debug.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_mcudbg.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the mcudbg firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_dma.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dma.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the dma firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_dvp.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dvp.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the dvp firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_edma.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_edma.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the edma firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_emac.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_emac.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the emac firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_ertc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_ertc.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the ertc firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_exint.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_exint.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the exint firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_flash.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_flash.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the flash firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_gpio.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_gpio.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the gpio firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_i2c.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_i2c.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the i2c firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_misc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_misc.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the misc firmware library
**************************************************************************
* Copyright notice & Disclaimer

9
libraries/drivers/src/at32f435_437_pwc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_pwc.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the pwc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -229,7 +229,10 @@ void pwc_standby_mode_enter(void)
#if defined (__CC_ARM)
__force_stores();
#endif
__WFI();
while(1)
{
__WFI();
}
}
/**

4
libraries/drivers/src/at32f435_437_qspi.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_qspi.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contain all the functions for qspi firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_scfg.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_scfg.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the system config firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_sdio.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_sdio.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the sdio firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_spi.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_spi.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the spi firmware library
**************************************************************************
* Copyright notice & Disclaimer

66
libraries/drivers/src/at32f435_437_tmr.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_tmr.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the tmr firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -265,11 +265,7 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir)
void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value)
{
/* set the repetition counter value */
if((tmr_x == TMR1) || (tmr_x == TMR8))
{
tmr_x->rpr_bit.rpr = tmr_rpr_value;
}
tmr_x->rpr_bit.rpr = tmr_rpr_value;
}
/**
@ -350,23 +346,23 @@ uint32_t tmr_div_value_get(tmr_type *tmr_x)
void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_output_config_type *tmr_output_struct)
{
uint16_t channel_index = 0, channel_c_index = 0, channel = 0;
uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset;
chx_offset = (8 + tmr_channel);
chcx_offset = (9 + tmr_channel);
/* get channel idle state bit position in ctrl2 register */
channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel));
channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset);
/* get channel complementary idle state bit position in ctrl2 register */
channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel));
channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset);
if((tmr_x == TMR1) || (tmr_x == TMR8))
{
/* set output channel complementary idle state */
tmr_x->ctrl2 &= ~channel_c_index;
tmr_x->ctrl2 |= channel_c_index;
}
/* set output channel complementary idle state */
tmr_x->ctrl2 &= ~(1<<chcx_offset);
tmr_x->ctrl2 |= channel_c_index;
/* set output channel idle state */
tmr_x->ctrl2 &= ~channel_index;
tmr_x->ctrl2 &= ~(1<<chx_offset);
tmr_x->ctrl2 |= channel_index;
/* set channel output mode */
@ -398,38 +394,38 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan
break;
}
chx_offset = ((tmr_channel * 2) + 1);
chcx_offset = ((tmr_channel * 2) + 3);
/* get channel polarity bit position in cctrl register */
channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1));
channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset);
/* get channel complementary polarity bit position in cctrl register */
channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3));
channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset);
if((tmr_x == TMR1) || (tmr_x == TMR8))
{
/* set output channel complementary polarity */
tmr_x->cctrl &= ~channel_c_index;
tmr_x->cctrl |= channel_c_index;
}
/* set output channel complementary polarity */
tmr_x->cctrl &= ~(1<<chcx_offset);
tmr_x->cctrl |= channel_c_index;
/* set output channel polarity */
tmr_x->cctrl &= ~channel_index;
tmr_x->cctrl &= ~(1<<chx_offset);
tmr_x->cctrl |= channel_index;
chx_offset = (tmr_channel * 2);
chcx_offset = ((tmr_channel * 2) + 2);
/* get channel enable bit position in cctrl register */
channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2));
/* get channel complementary enable bit position in cctrl register */
channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2));
if((tmr_x == TMR1) || (tmr_x == TMR8))
{
/* set output channel complementary enable bit */
tmr_x->cctrl &= ~channel_c_index;
tmr_x->cctrl |= channel_c_index;
}
/* set output channel complementary enable bit */
tmr_x->cctrl &= ~(1<<chcx_offset);
tmr_x->cctrl |= channel_c_index;
/* set output channel enable bit */
tmr_x->cctrl &= ~channel_index;
tmr_x->cctrl &= ~(1<<chx_offset);
tmr_x->cctrl |= channel_index;
}
@ -880,6 +876,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct
switch(channel)
{
case TMR_SELECT_CHANNEL_1:
tmr_x->cctrl_bit.c1en = FALSE;
tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select;
tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1;
tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select;
@ -889,6 +886,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct
break;
case TMR_SELECT_CHANNEL_2:
tmr_x->cctrl_bit.c2en = FALSE;
tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select;
tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1;
tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select;
@ -898,6 +896,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct
break;
case TMR_SELECT_CHANNEL_3:
tmr_x->cctrl_bit.c3en = FALSE;
tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select;
tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1;
tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select;
@ -907,6 +906,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct
break;
case TMR_SELECT_CHANNEL_4:
tmr_x->cctrl_bit.c4en = FALSE;
tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select;
tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select;
tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value;

4
libraries/drivers/src/at32f435_437_usart.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usart.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the usart firmware library
**************************************************************************
* Copyright notice & Disclaimer

10
libraries/drivers/src/at32f435_437_usb.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usb.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the usb firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -1020,11 +1020,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
usb_chh->hcchar_bit.eptype == EPT_BULK_TYPE)
{
usb_chh->hcchar_bit.chdis = TRUE;
if((usbx->gnptxsts & 0xFFFF) == 0)
if((usbx->gnptxsts_bit.nptxqspcavail) == 0)
{
usb_chh->hcchar_bit.chena = FALSE;
usb_chh->hcchar_bit.chena = TRUE;
usb_chh->hcchar_bit.eptdir = 0;
do
{
if(count ++ > 1000)
@ -1039,11 +1038,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
else
{
usb_chh->hcchar_bit.chdis = TRUE;
if((usb_host->hptxsts & 0xFFFF) == 0)
if((usb_host->hptxsts_bit.ptxqspcavil) == 0)
{
usb_chh->hcchar_bit.chena = FALSE;
usb_chh->hcchar_bit.chena = TRUE;
usb_chh->hcchar_bit.eptdir = 0;
do
{
if(count ++ > 1000)

4
libraries/drivers/src/at32f435_437_wdt.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wdt.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the wdt firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_wwdt.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wwdt.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the wwdt firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_xmc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_xmc.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief contains all the functions for the xmc firmware library
**************************************************************************
* Copyright notice & Disclaimer

12
middlewares/3rd_party/lwip_2.1.2/port/ethernetif.c vendored
View File

@ -83,8 +83,8 @@ struct ethernetif
/* Forward declarations. */
err_t ethernetif_input(struct netif *netif);
#define EMAC_RXBUFNB 4
#define EMAC_TXBUFNB 2
#define EMAC_RXBUFNB 6
#define EMAC_TXBUFNB 6
uint8_t MACaddr[6];
emac_dma_desc_type DMARxDscrTab[EMAC_RXBUFNB], DMATxDscrTab[EMAC_TXBUFNB];/* Ethernet Rx & Tx DMA Descriptors */
@ -162,6 +162,12 @@ low_level_init(struct netif *netif)
{
emac_dma_rx_desc_interrupt_config(&DMARxDscrTab[i], TRUE);
}
#ifdef CHECKSUM_BY_HARDWARE
for(i=0; i < EMAC_TXBUFNB; i++)
{
DMATxDscrTab[i].status |= EMAC_DMATXDESC_CIC_TUI_FULL;
}
#endif
}
/* Enable MAC and DMA transmission and reception */
@ -245,7 +251,7 @@ low_level_input(struct netif *netif)
/* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
frame.descriptor->status = EMAC_DMARXDESC_OWN;
frame.descriptor->status |= EMAC_DMARXDESC_OWN;
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
if(emac_dma_flag_get(EMAC_DMA_RBU_FLAG))

357
middlewares/i2c_application_library/i2c_application.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file i2c_application.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief the driver library of the i2c peripheral
**************************************************************************
* Copyright notice & Disclaimer
@ -26,6 +26,10 @@
#include "i2c_application.h"
/** @addtogroup AT32F435_437_middlewares_i2c_application_library
* @{
*/
/**
* @brief get the dma transfer direction flag through the channel
*/
@ -991,9 +995,54 @@ i2c_status_type i2c_slave_transmit_dma(i2c_handle_type* hi2c, uint8_t* pdata, ui
return I2C_OK;
}
/**
* @brief send memory address.
* @param hi2c: the handle points to the operation information.
* @param mem_address_width: memory address width.
* this parameter can be one of the following values:
* - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
* - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
* @param address: memory device address.
* @param mem_address: memory address.
* @param timeout: maximum waiting time.
* @retval i2c status.
*/
i2c_status_type i2c_memory_address_send(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t mem_address, int32_t timeout)
{
i2c_status_type err_code;
if(mem_address_width == I2C_MEM_ADDR_WIDIH_8)
{
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address & 0xFF);
}
else
{
/* send memory address */
i2c_data_send(hi2c->i2cx, (mem_address >> 8) & 0xFF);
/* wait for the tdis flag to be set */
err_code = i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout);
if(err_code != I2C_OK)
{
return err_code;
}
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address & 0xFF);
}
return I2C_OK;
}
/**
* @brief write data to the memory device through polling mode.
* @param hi2c: the handle points to the operation information.
* @param mem_address_width: memory address width.
* this parameter can be one of the following values:
* - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
* - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
* @param address: memory device address.
* @param mem_address: memory address.
* @param pdata: data buffer.
@ -1001,11 +1050,11 @@ i2c_status_type i2c_slave_transmit_dma(i2c_handle_type* hi2c, uint8_t* pdata, ui
* @param timeout: maximum waiting time.
* @retval i2c status.
*/
i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
{
/* initialization parameters */
hi2c->pbuff = pdata;
hi2c->pcount = size + 1;
hi2c->pcount = size + mem_address_width;
hi2c->error_code = I2C_OK;
@ -1025,17 +1074,20 @@ i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, uint16_t address, uint16
}
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
hi2c->psize--;
hi2c->pcount--;
hi2c->psize -= mem_address_width;
hi2c->pcount -= mem_address_width;
while (hi2c->pcount > 0)
{
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
return I2C_ERR_STEP_4;
}
/* send data */
@ -1047,92 +1099,6 @@ i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, uint16_t address, uint16
{
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_4;
}
/* continue transfer */
i2c_start_transfer(hi2c, address, I2C_WITHOUT_START);
}
}
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_5;
}
/* clear stop flag */
i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
/* reset ctrl2 register */
i2c_reset_ctrl2_register(hi2c);
return I2C_OK;
}
/**
* @brief read data from memory device through polling mode.
* @param hi2c: the handle points to the operation information.
* @param address: memory device address.
* @param mem_address: memory address.
* @param pdata: data buffer.
* @param size: data size.
* @param timeout: maximum waiting time.
* @retval i2c status.
*/
i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
{
/* initialization parameters */
hi2c->pbuff = pdata;
hi2c->pcount = size;
hi2c->error_code = I2C_OK;
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
/* start transfer */
i2c_transmit_set(hi2c->i2cx, address, 1, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
/* wait for the tdc flag to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
/* start transfer */
i2c_start_transfer(hi2c, address, I2C_GEN_START_READ);
while (hi2c->pcount > 0)
{
/* wait for the rdbf flag to be set */
if (i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_4;
}
/* read data */
(*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
hi2c->pcount--;
hi2c->psize--;
if ((hi2c->psize == 0) && (hi2c->pcount != 0))
{
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_5;
}
@ -1143,7 +1109,7 @@ i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_
}
/* wait for the stop flag to be set */
if (i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_6;
}
@ -1158,8 +1124,12 @@ i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_
}
/**
* @brief write data to the memory device through interrupt mode.
* @brief read data from memory device through polling mode.
* @param hi2c: the handle points to the operation information.
* @param mem_address_width: memory address width.
* this parameter can be one of the following values:
* - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
* - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
* @param address: memory device address.
* @param mem_address: memory address.
* @param pdata: data buffer.
@ -1167,14 +1137,107 @@ i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_
* @param timeout: maximum waiting time.
* @retval i2c status.
*/
i2c_status_type i2c_memory_write_int(i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
{
/* initialization parameters */
hi2c->pbuff = pdata;
hi2c->pcount = size;
hi2c->error_code = I2C_OK;
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
/* start transfer */
i2c_transmit_set(hi2c->i2cx, address, mem_address_width, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
/* send memory address */
if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
/* wait for the tdc flag to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_4;
}
/* start transfer */
i2c_start_transfer(hi2c, address, I2C_GEN_START_READ);
while (hi2c->pcount > 0)
{
/* wait for the rdbf flag to be set */
if (i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_5;
}
/* read data */
(*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
hi2c->pcount--;
hi2c->psize--;
if ((hi2c->psize == 0) && (hi2c->pcount != 0))
{
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_6;
}
/* continue transfer */
i2c_start_transfer(hi2c, address, I2C_WITHOUT_START);
}
}
/* wait for the stop flag to be set */
if (i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_7;
}
/* clear stop flag */
i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
/* reset ctrl2 register */
i2c_reset_ctrl2_register(hi2c);
return I2C_OK;
}
/**
* @brief write data to the memory device through interrupt mode.
* @param hi2c: the handle points to the operation information.
* @param mem_address_width: memory address width.
* this parameter can be one of the following values:
* - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
* - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
* @param address: memory device address.
* @param mem_address: memory address.
* @param pdata: data buffer.
* @param size: data size.
* @param timeout: maximum waiting time.
* @retval i2c status.
*/
i2c_status_type i2c_memory_write_int(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
{
/* initialization parameters */
hi2c->mode = I2C_INT_MA_TX;
hi2c->status = I2C_START;
hi2c->pbuff = pdata;
hi2c->pcount = size + 1;
hi2c->pcount = size + mem_address_width;
hi2c->error_code = I2C_OK;
@ -1194,7 +1257,11 @@ i2c_status_type i2c_memory_write_int(i2c_handle_type* hi2c, uint16_t address, ui
}
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
hi2c->psize--;
hi2c->pcount--;
@ -1207,6 +1274,10 @@ i2c_status_type i2c_memory_write_int(i2c_handle_type* hi2c, uint16_t address, ui
/**
* @brief read data from memory device through interrupt mode.
* @param hi2c: the handle points to the operation information.
* @param mem_address_width: memory address width.
* this parameter can be one of the following values:
* - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
* - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
* @param address: memory device address.
* @param mem_address: memory address.
* @param pdata: data buffer.
@ -1214,7 +1285,7 @@ i2c_status_type i2c_memory_write_int(i2c_handle_type* hi2c, uint16_t address, ui
* @param timeout: maximum waiting time.
* @retval i2c status.
*/
i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
{
/* initialization parameters */
hi2c->mode = I2C_INT_MA_RX;
@ -1232,7 +1303,7 @@ i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, uint16_t address, uin
}
/* start transfer */
i2c_transmit_set(hi2c->i2cx, address, 1, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
i2c_transmit_set(hi2c->i2cx, address, mem_address_width, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
@ -1241,12 +1312,15 @@ i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, uint16_t address, uin
}
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
/* wait for the tdc flag to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
return I2C_ERR_STEP_4;
}
/* start transfer */
@ -1261,6 +1335,10 @@ i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, uint16_t address, uin
/**
* @brief write data to the memory device through dma mode.
* @param hi2c: the handle points to the operation information.
* @param mem_address_width: memory address width.
* this parameter can be one of the following values:
* - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
* - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
* @param address: memory device address.
* @param mem_address: memory address.
* @param pdata: data buffer.
@ -1268,7 +1346,7 @@ i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, uint16_t address, uin
* @param timeout: maximum waiting time.
* @retval i2c status.
*/
i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
{
/* initialization parameters */
hi2c->mode = I2C_DMA_MA_TX;
@ -1289,7 +1367,7 @@ i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, uint16_t address, ui
}
/* transfer config */
i2c_transmit_set(hi2c->i2cx, address, 1, I2C_RELOAD_MODE, I2C_GEN_START_WRITE);
i2c_transmit_set(hi2c->i2cx, address, mem_address_width, I2C_RELOAD_MODE, I2C_GEN_START_WRITE);
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
@ -1298,12 +1376,15 @@ i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, uint16_t address, ui
}
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
return I2C_ERR_STEP_4;
}
/* start transfer */
@ -1321,6 +1402,10 @@ i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, uint16_t address, ui
/**
* @brief read data from memory device through polling mode.
* @param hi2c: the handle points to the operation information.
* @param mem_address_width: memory address width.
* this parameter can be one of the following values:
* - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
* - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
* @param address: memory device address.
* @param mem_address: memory address.
* @param pdata: data buffer.
@ -1328,7 +1413,7 @@ i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, uint16_t address, ui
* @param timeout: maximum waiting time.
* @retval i2c status.
*/
i2c_status_type i2c_memory_read_dma(i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
i2c_status_type i2c_memory_read_dma(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
{
/* initialization parameters */
hi2c->mode = I2C_DMA_MA_RX;
@ -1346,7 +1431,7 @@ i2c_status_type i2c_memory_read_dma(i2c_handle_type* hi2c, uint16_t address, uin
}
/* start transfer */
i2c_transmit_set(hi2c->i2cx, address, 1, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
i2c_transmit_set(hi2c->i2cx, address, mem_address_width, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
@ -1355,12 +1440,15 @@ i2c_status_type i2c_memory_read_dma(i2c_handle_type* hi2c, uint16_t address, uin
}
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
/* wait for the tdc flag to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
return I2C_ERR_STEP_4;
}
/* disable dma request */
@ -2172,46 +2260,81 @@ void i2c_evt_irq_handler(i2c_handle_type* hi2c)
* @retval none.
*/
void i2c_err_irq_handler(i2c_handle_type* hi2c)
{
hi2c->error_code = I2C_ERR_INTERRUPT;
{
/* buserr */
if (i2c_flag_get(hi2c->i2cx, I2C_BUSERR_FLAG) != RESET)
{
hi2c->error_code = I2C_ERR_INTERRUPT;
/* clear flag */
i2c_flag_clear(hi2c->i2cx, I2C_BUSERR_FLAG);
/* disable interrupts */
i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
}
/* arlost */
if (i2c_flag_get(hi2c->i2cx, I2C_ARLOST_FLAG) != RESET)
{
hi2c->error_code = I2C_ERR_INTERRUPT;
/* clear flag */
i2c_flag_clear(hi2c->i2cx, I2C_ARLOST_FLAG);
/* disable interrupts */
i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
}
/* ouf */
if (i2c_flag_get(hi2c->i2cx, I2C_OUF_FLAG) != RESET)
{
hi2c->error_code = I2C_ERR_INTERRUPT;
/* clear flag */
i2c_flag_clear(hi2c->i2cx, I2C_OUF_FLAG);
/* disable interrupts */
i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
}
/* pecerr */
if (i2c_flag_get(hi2c->i2cx, I2C_PECERR_FLAG) != RESET)
{
hi2c->error_code = I2C_ERR_INTERRUPT;
/* clear flag */
i2c_flag_clear(hi2c->i2cx, I2C_PECERR_FLAG);
/* disable interrupts */
i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
}
/* timeout */
if (i2c_flag_get(hi2c->i2cx, I2C_TMOUT_FLAG) != RESET)
{
hi2c->error_code = I2C_ERR_INTERRUPT;
/* clear flag */
i2c_flag_clear(hi2c->i2cx, I2C_TMOUT_FLAG);
/* disable interrupts */
i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
}
/* alertf */
if (i2c_flag_get(hi2c->i2cx, I2C_ALERTF_FLAG) != RESET)
{
hi2c->error_code = I2C_ERR_INTERRUPT;
/* clear flag */
i2c_flag_clear(hi2c->i2cx, I2C_ALERTF_FLAG);
/* disable interrupts */
i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
}
/* disable interrupts */
i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
}
/**
* @}
*/

30
middlewares/i2c_application_library/i2c_application.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file i2c_application.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief i2c application libray header file
**************************************************************************
* Copyright notice & Disclaimer
@ -48,6 +48,20 @@ extern "C" {
#define I2C_EVENT_CHECK_ACKFAIL ((uint32_t)0x00000001) /*!< check flag ackfail */
#define I2C_EVENT_CHECK_STOP ((uint32_t)0x00000002) /*!< check flag stop */
/**
* @}
*/
/** @defgroup I2C_library_memory_address_width_mode
* @{
*/
typedef enum
{
I2C_MEM_ADDR_WIDIH_8 = 0x01, /*!< memory address is 8 bit */
I2C_MEM_ADDR_WIDIH_16 = 0x02, /*!< memory address is 16 bit */
} i2c_mem_address_width_type;
/**
* @}
*/
@ -156,12 +170,12 @@ i2c_status_type i2c_smbus_master_receive (i2c_handle_type* hi2c, uint16_t addre
i2c_status_type i2c_smbus_slave_transmit (i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_smbus_slave_receive (i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_write (i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_write_int (i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_write_dma (i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_read (i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_read_int (i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_read_dma (i2c_handle_type* hi2c, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_write (i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_write_int (i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_write_dma (i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_read (i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_read_int (i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_memory_read_dma (i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout);
void i2c_evt_irq_handler (i2c_handle_type* hi2c);
void i2c_err_irq_handler (i2c_handle_type* hi2c);

4
middlewares/usb_drivers/inc/usb_core.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_core.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb core header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usb_std.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_std.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb standard header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbd_core.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_core.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb device core header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbd_int.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_int.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb interrupt header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbd_sdr.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_sdr.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbh_core.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_core.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb host core header file
**************************************************************************
* Copyright notice & Disclaimer

8
middlewares/usb_drivers/inc/usbh_ctrl.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_ctrl.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb header file
**************************************************************************
* Copyright notice & Disclaimer
@ -51,9 +51,9 @@ extern "C" {
usb_sts_type usbh_ctrl_send_setup(usbh_core_type *uhost, uint8_t *buffer, uint8_t hc_num);
usb_sts_type usbh_ctrl_recv_data(usbh_core_type *uhost, uint8_t *buffer,
uint8_t length, uint16_t hc_num);
uint16_t length, uint16_t hc_num);
usb_sts_type usbh_ctrl_send_data(usbh_core_type *uhost, uint8_t *buffer,
uint8_t length, uint16_t hc_num);
uint16_t length, uint16_t hc_num);
usb_sts_type usbh_ctrl_setup_handler(usbh_core_type *uhost);
usb_sts_type usbh_ctrl_setup_wait_handler(usbh_core_type *uhost, uint32_t *timeout);
usb_sts_type usbh_ctrl_data_in_handler(usbh_core_type *uhost);

4
middlewares/usb_drivers/inc/usbh_int.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_int.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usb_core.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_core.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb driver
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbd_core.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_core.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb device driver
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbd_int.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_int.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb interrupt request
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbd_sdr.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_sdr.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb standard device request
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbh_core.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_core.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb host driver
**************************************************************************
* Copyright notice & Disclaimer

8
middlewares/usb_drivers/src/usbh_ctrl.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_ctrl.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb host control request
**************************************************************************
* Copyright notice & Disclaimer
@ -69,7 +69,7 @@ usb_sts_type usbh_ctrl_send_setup(usbh_core_type *uhost, uint8_t *buffer, uint8_
* @retval status: usb_sts_type status
*/
usb_sts_type usbh_ctrl_recv_data(usbh_core_type *uhost, uint8_t *buffer,
uint8_t length, uint16_t hc_num)
uint16_t length, uint16_t hc_num)
{
uhost->hch[hc_num].dir = 1;
uhost->hch[hc_num].data_pid = HCH_PID_DATA1;
@ -88,7 +88,7 @@ usb_sts_type usbh_ctrl_recv_data(usbh_core_type *uhost, uint8_t *buffer,
* @retval status: usb_sts_type status
*/
usb_sts_type usbh_ctrl_send_data(usbh_core_type *uhost, uint8_t *buffer,
uint8_t length, uint16_t hc_num)
uint16_t length, uint16_t hc_num)
{
uhost->hch[hc_num].dir = 0;
uhost->hch[hc_num].trans_buf = buffer;

9
middlewares/usb_drivers/src/usbh_int.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_int.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb host interrupt request
**************************************************************************
* Copyright notice & Disclaimer
@ -71,7 +71,7 @@ void usbh_irq_handler(otg_core_type *otgdev)
usbh_wakeup_handler(uhost);
usb_global_clear_interrupt(usbx, USB_OTG_WKUP_FLAG);
}
if(intsts & USB_OTG_RXFLVL_FLAG)
while(usbx->gintsts & USB_OTG_RXFLVL_FLAG)
{
usbh_rx_qlvl_handler(uhost);
usb_global_clear_interrupt(usbx, USB_OTG_RXFLVL_FLAG);
@ -264,8 +264,7 @@ void usbh_hch_in_handler(usbh_core_type *uhost, uint8_t chn)
{
uhost->err_cnt[chn] = 0;
usb_chh->hcintmsk_bit.chhltdmsk = TRUE;
usb_chh->hcchar_bit.chdis = FALSE;
usb_chh->hcchar_bit.chena = TRUE;
usb_hch_halt(usbx, chn);
}
uhost->hch[chn].state = HCH_NAK;
usb_chh->hcint = USB_OTG_HC_NAK_FLAG;

4
middlewares/usbd_class/audio/audio_class.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio class type
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio/audio_class.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio class file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio/audio_conf.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_conf.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio config
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio/audio_desc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio device descriptor
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio/audio_desc.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio descriptor header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_conf.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_conf.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio config
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_hid_class.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio class type
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_hid_class.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio class file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_hid_desc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio device descriptor
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_hid_desc.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.h
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb audio descriptor header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/cdc/cdc_class.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file cdc_class.c
* @version v2.0.9
* @date 2022-06-28
* @version v2.1.0
* @date 2022-08-16
* @brief usb cdc class type
**************************************************************************
* Copyright notice & Disclaimer

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