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AT32F435_437_Firmware_Library
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update version to v2.0.9

This commit is contained in:
Artery-MCU 2022-06-30 17:28:51 +08:00
parent 34875e6c6f
commit 60161fc869
3348 changed files with 146230 additions and 9064 deletions
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AT32F435_437_periph_lib_V2.0.8.chm → AT32F435_437_periph_lib_V2.0.9.chm
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document/AT32F435_437固件库BSP&Pack应用指南.pdf
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document/ReleaseNotes_AT32F435_437_Firmware_Library.pdf
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6
libraries/cmsis/cm4/device_support/at32f435_437.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 header file
**************************************************************************
* Copyright notice & Disclaimer
@ -100,7 +100,7 @@ extern "C" {
*/
#define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x08) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x09) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \

4
libraries/cmsis/cm4/device_support/at32f435_437_conf_template.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_conf.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 config header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/cmsis/cm4/device_support/startup/gcc/startup_at32f435_437.s
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@ -1,8 +1,8 @@
/**
******************************************************************************
* @file startup_at32f435_437.s
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 devices vector table for gcc toolchain.
* this module performs:
* - set the initial sp

4
libraries/cmsis/cm4/device_support/startup/iar/startup_at32f435_437.s
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@ -1,7 +1,7 @@
;**************************************************************************
;* @file startup_at32f435_437.s
;* @version v2.0.8
;* @date 2022-04-25
;* @version v2.0.9
;* @date 2022-06-28
;* @brief at32f435_437 startup file for IAR Systems
;**************************************************************************
;

4
libraries/cmsis/cm4/device_support/startup/mdk/startup_at32f435_437.s
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@ -1,7 +1,7 @@
;**************************************************************************
;* @file startup_at32f435_437.s
;* @version v2.0.8
;* @date 2022-04-25
;* @version v2.0.9
;* @date 2022-06-28
;* @brief at32f435_437 startup file for keil
;**************************************************************************
;

10
libraries/cmsis/cm4/device_support/system_at32f435_437.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file system_at32f435_437.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for cmsis cortex-m4 system source file
**************************************************************************
* Copyright notice & Disclaimer
@ -81,12 +81,12 @@ void SystemInit (void)
/* wait sclk switch status */
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
CRM->cfg = 0;
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
CRM->cfg = 0;
/* reset pllms pllns pllfr pllrcs bits */
CRM->pllcfg = 0x00033002U;

6
libraries/cmsis/cm4/device_support/system_at32f435_437.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file system_at32f435_437.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief cmsis cortex-m4 system header file.
**************************************************************************
* Copyright notice & Disclaimer
@ -39,6 +39,8 @@ extern "C" {
* @{
*/
#define SystemCoreClock system_core_clock
/** @defgroup AT32F435_437_system_exported_variables
* @{
*/

4
libraries/cmsis/dsp/PrivateInclude/arm_sorting.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_sorting.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief Private header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/cmsis/dsp/PrivateInclude/arm_vec_fft.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_vec_fft.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief Private header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/cmsis/dsp/PrivateInclude/arm_vec_filtering.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_vec_filtering.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief Private header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/cmsis/dsp/include/arm_math.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_math.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief Public header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/cmsis/dsp/include/arm_vec_math.h
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@ -1,7 +1,7 @@
/******************************************************************************
* @file arm_vec_math.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief Public header file for CMSIS DSP Library
******************************************************************************/
/*

4
libraries/drivers/inc/at32f435_437_acc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_acc.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 acc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_adc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_adc.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 adc header file
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/inc/at32f435_437_can.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_can.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 can header file
**************************************************************************
* Copyright notice & Disclaimer
@ -352,7 +352,7 @@ typedef struct
*/
typedef struct
{
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/
can_rsaw_type rsaw_size; /*!< resynchronization adjust width */

4
libraries/drivers/inc/at32f435_437_crc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crc.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 crc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_crm.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crm.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 crm header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_dac.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dac.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 dac header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_debug.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_mcudbg.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 mcudbg header file
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/inc/at32f435_437_def.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_def.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 macros header file
**************************************************************************
* Copyright notice & Disclaimer
@ -62,6 +62,8 @@ extern "C" {
#endif
#endif
#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */
#ifdef __cplusplus
}
#endif

4
libraries/drivers/inc/at32f435_437_dma.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dma.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 dma header file
**************************************************************************
* Copyright notice & Disclaimer

66
libraries/drivers/inc/at32f435_437_dvp.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dvp.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 dvp header file
**************************************************************************
* Copyright notice & Disclaimer
@ -204,17 +204,17 @@ typedef enum
{
DVP_STATUS_HSYN = 0x00,
DVP_STATUS_VSYN = 0x01,
DVP_STATUS_OFS = 0x02
DVP_STATUS_OFNE = 0x02
} dvp_status_basic_type;
/**
* @brief dvp pcdse type
* @brief dvp pcdes type
*/
typedef enum
{
DVP_PCDSE_CAP_FIRST = 0x00,
DVP_PCDSE_DROP_FIRST = 0x01
} dvp_pcdse_type;
DVP_PCDES_CAP_FIRST = 0x00,
DVP_PCDES_DROP_FIRST = 0x01
} dvp_pcdes_type;
/**
* @brief dvp efdf type
@ -224,18 +224,18 @@ typedef enum
DVP_EFDF_BYPASS = 0x00,
DVP_EFDF_YUV422_UYVY = 0x04,
DVP_EFDF_YUV422_YUYV = 0x05,
DVP_EFDF_YUV444 = 0x06,
DVP_EFDF_RGB565_555 = 0x06,
DVP_EFDF_Y8 = 0x07
} dvp_efdf_type;
/**
* @brief dvp iduc type
* @brief dvp idus type
*/
typedef enum
{
DVP_IDUC_MSB = 0x00,
DVP_IDUC_LSB = 0x01
} dvp_iduc_type;
DVP_IDUS_MSB = 0x00,
DVP_IDUS_LSB = 0x01
} dvp_idus_type;
/**
* @brief dvp dmabt type
@ -247,22 +247,22 @@ typedef enum
} dvp_dmabt_type;
/**
* @brief dvp hseis type
* @brief dvp hseid type
*/
typedef enum
{
DVP_HSEIS_LINE_END = 0x00,
DVP_HSEIS_LINE_START = 0x01
} dvp_hseis_type;
DVP_HSEID_LINE_END = 0x00,
DVP_HSEID_LINE_START = 0x01
} dvp_hseid_type;
/**
* @brief dvp vseis type
* @brief dvp vseid type
*/
typedef enum
{
DVP_VSEIS_FRAME_END = 0x00,
DVP_VSEIS_FRMAE_START = 0x01
} dvp_vseis_type;
DVP_VSEID_FRAME_END = 0x00,
DVP_VSEID_FRMAE_START = 0x01
} dvp_vseid_type;
/**
* @brief dvp idun type
*/
@ -315,7 +315,7 @@ typedef struct
{
__IO uint32_t hsyn : 1; /* [0] */
__IO uint32_t vsyn : 1; /* [1] */
__IO uint32_t ofs : 1; /* [2] */
__IO uint32_t ofne : 1; /* [2] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} sts_bit;
};
@ -479,18 +479,18 @@ typedef struct
__IO uint32_t eisre : 1; /* [0] */
__IO uint32_t efrce : 1; /* [1] */
__IO uint32_t mibe : 1; /* [2] */
__IO uint32_t pcdse : 1; /* [3] */
__IO uint32_t pcdes : 1; /* [3] */
__IO uint32_t efdf : 3; /* [6:4] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t idun : 2; /* [9:8] */
__IO uint32_t iduc : 1; /* [10] */
__IO uint32_t idus : 1; /* [10] */
__IO uint32_t reserved2 : 1; /* [11] */
__IO uint32_t dmabt : 1; /* [12] */
__IO uint32_t reserved3 : 1; /* [13] */
__IO uint32_t reserved4 : 1; /* [14] */
__IO uint32_t reserved5 : 1; /* [15] */
__IO uint32_t hseis : 1; /* [16] */
__IO uint32_t vseis : 1; /* [17] */
__IO uint32_t hseid : 1; /* [16] */
__IO uint32_t vseid : 1; /* [17] */
__IO uint32_t reserved6 : 1; /* [18] */
__IO uint32_t reserved7 : 2; /* [20:19] */
__IO uint32_t reserved8 : 11;/* [31:21] */
@ -540,9 +540,9 @@ typedef struct
__IO uint32_t frf;
struct
{
__IO uint32_t efrcfm : 5; /* [4:0] */
__IO uint32_t efrcsf : 5; /* [4:0] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t efrcfn : 5; /* [12:8] */
__IO uint32_t efrctf : 5; /* [12:8] */
__IO uint32_t reserved2 : 19;/* [31:13] */
} frf_bit;
};
@ -572,10 +572,12 @@ typedef struct
* @{
*/
void dvp_reset(void);
void dvp_capture_enable(confirm_state new_state);
void dvp_capture_enable(confirm_state new_state);
void dvp_capture_mode_set(dvp_cfm_type cap_mode);
void dvp_window_crop_enable(confirm_state new_state);
void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h);
void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes);
void dvp_jpeg_enable(confirm_state new_state);
void dvp_sync_mode_set(dvp_sm_type sync_mode);
void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec);
@ -586,7 +588,7 @@ void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol);
void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc);
void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl);
void dvp_enable(confirm_state new_state);
void dvp_zoomout_select(dvp_pcdse_type dvp_pcdse);
void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes);
void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds);
flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic);
void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state);
@ -594,12 +596,12 @@ flag_status dvp_flag_get(uint32_t flag);
void dvp_flag_clear(uint32_t flag);
void dvp_enhanced_scaling_resize_enable(confirm_state new_state);
void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h);
void dvp_enhanced_framerate_set(uint16_t efrcfm, uint16_t efrcfn, confirm_state new_state);
void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state);
void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state);
void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf);
void dvp_input_data_unused_set(dvp_iduc_type dvp_iduc, dvp_idun_type dvp_idun);
void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun);
void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt);
void dvp_sync_event_interrupt_set(dvp_hseis_type dvp_hseis, dvp_vseis_type dvp_vseis);
void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid);
/**
* @}

4
libraries/drivers/inc/at32f435_437_edma.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_edma.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 edma header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_emac.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_emac.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 eth header file
**************************************************************************
* Copyright notice & Disclaimer

18
libraries/drivers/inc/at32f435_437_ertc.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_ertc.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 ertc header file
**************************************************************************
* Copyright notice & Disclaimer
@ -90,6 +90,16 @@ extern "C" {
#define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */
#define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */
/**
* @}
*/
/**
* @brief compatible with older versions
*/
#define ERTC_WAT_CLK_CK_A_16BITS ERTC_WAT_CLK_CK_B_16BITS
#define ERTC_WAT_CLK_CK_A_17BITS ERTC_WAT_CLK_CK_B_17BITS
/**
* @}
*/
@ -167,8 +177,8 @@ typedef enum
ERTC_WAT_CLK_ERTCCLK_DIV8 = 0x01, /*!< the wake up timer clock is ERTC_CLK / 8 */
ERTC_WAT_CLK_ERTCCLK_DIV4 = 0x02, /*!< the wake up timer clock is ERTC_CLK / 4 */
ERTC_WAT_CLK_ERTCCLK_DIV2 = 0x03, /*!< the wake up timer clock is ERTC_CLK / 2 */
ERTC_WAT_CLK_CK_A_16BITS = 0x04, /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT */
ERTC_WAT_CLK_CK_A_17BITS = 0x06 /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT + 65535 */
ERTC_WAT_CLK_CK_B_16BITS = 0x04, /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT */
ERTC_WAT_CLK_CK_B_17BITS = 0x06 /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT + 65535 */
} ertc_wakeup_clock_type;
/**

4
libraries/drivers/inc/at32f435_437_exint.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_exint.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 exint header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_flash.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_flash.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 flash header file
**************************************************************************
* Copyright notice & Disclaimer

6
libraries/drivers/inc/at32f435_437_gpio.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_gpio.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 gpio header file
**************************************************************************
* Copyright notice & Disclaimer
@ -541,7 +541,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x);
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value);
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);

10
libraries/drivers/inc/at32f435_437_i2c.h
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_i2c.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 i2c header file
**************************************************************************
* Copyright notice & Disclaimer
@ -176,14 +176,14 @@ typedef enum
} i2c_reload_stop_mode_type;
/**
* @brief i2c start stop mode
* @brief i2c start mode
*/
typedef enum
{
I2C_WITHOUT_START = 0x00000000, /*!< transfer data without start condition */
I2C_GEN_START_READ = 0x00002400, /*!< read data and generate start */
I2C_GEN_START_WRITE = 0x00002000 /*!< send data and generate start */
} i2c_start_stop_mode_type;
} i2c_start_mode_type;
/**
* @brief type define i2c register all
@ -452,7 +452,7 @@ void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state);
flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source);
void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state);
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop);
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start);
void i2c_start_generate(i2c_type *i2c_x);
void i2c_stop_generate(i2c_type *i2c_x);
void i2c_data_send(i2c_type *i2c_x, uint8_t data);

8
libraries/drivers/inc/at32f435_437_misc.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_misc.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 misc header file
**************************************************************************
* Copyright notice & Disclaimer
@ -76,9 +76,9 @@ typedef enum
*/
typedef enum
{
NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */
NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */
NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
} nvic_lowpower_mode_type;
/**

4
libraries/drivers/inc/at32f435_437_pwc.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_pwc.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 pwr header file
**************************************************************************
* Copyright notice & Disclaimer

8
libraries/drivers/inc/at32f435_437_qspi.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_qspi.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 qspi header file
**************************************************************************
* Copyright notice & Disclaimer
@ -517,12 +517,12 @@ typedef struct
*/
void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode);
void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode);
void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag);
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag);
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);

10
libraries/drivers/inc/at32f435_437_scfg.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_scfg.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 system config header file
**************************************************************************
* Copyright notice & Disclaimer
@ -57,9 +57,9 @@ extern "C" {
typedef enum
{
SCFG_XMC_SWAP_NONE = 0x00, /* no swap */
SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram nor psram sram nand2 swap */
SCFG_XMC_SWAP_MODE2 = 0x02, /* nand3 qspi2 swap */
SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram nor psram sram nand2 nand3 qspi2 swap */
SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000 */
SCFG_XMC_SWAP_MODE2 = 0x02, /* qspi2 0x80000000, nand3 0xB0000000 */
SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000, qspi2 0x80000000, nand3 0xB0000000 */
} scfg_xmc_swap_type;
/**

6
libraries/drivers/inc/at32f435_437_sdio.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_sdio.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 sdio header file
**************************************************************************
* Copyright notice & Disclaimer
@ -578,7 +578,7 @@ typedef struct
void sdio_reset(sdio_type *sdio_x);
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
flag_status sdio_power_status_get(sdio_type *sdio_x);
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);

4
libraries/drivers/inc/at32f435_437_spi.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_spi.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 spi header file
**************************************************************************
* Copyright notice & Disclaimer

19
libraries/drivers/inc/at32f435_437_tmr.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_tmr.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 tmr header file
**************************************************************************
* Copyright notice & Disclaimer
@ -54,6 +54,7 @@ extern "C" {
#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
#define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */
#define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */
#define TMR_C5_FLAG ((uint32_t)0x010000) /*!< tmr flag channel 5 */
#define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */
#define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */
#define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */
@ -291,17 +292,6 @@ typedef enum
TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */
}tmr_event_trigger_type;
/**
* @brief tmr channel output fast type
*/
typedef enum
{
TMR_CHANNEL1_OUTPUT_FAST = MAKE_VALUE(0x18, 2), /*!< tmr channel 1 output fast mode */
TMR_CHANNEL2_OUTPUT_FAST = MAKE_VALUE(0x18, 10), /*!< tmr channel 2 output fast mode */
TMR_CHANNEL3_OUTPUT_FAST = MAKE_VALUE(0x1c, 2), /*!< tmr channel 3 output fast mode */
TMR_CHANNEL4_OUTPUT_FAST = MAKE_VALUE(0x1c, 10) /*!< tmr channel 4 output fast mode */
}tmr_channel_output_fast_type;
/**
* @brief tmr polarity active type
*/
@ -962,7 +952,7 @@ void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_c
uint16_t filter_value);
void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
tmr_channel_input_divider_type divider_factor);
void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect);
void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect);
void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_channel_input_divider_type divider_factor);
void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
@ -980,7 +970,6 @@ void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_internal_clock_set(tmr_type *tmr_x);
void tmr_output_channel_fast_set(tmr_type *tmr_x, tmr_channel_output_fast_type oc_fast);
void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_polarity_active_type oc_polarity);
void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \

4
libraries/drivers/inc/at32f435_437_usart.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usart.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 usart header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_usb.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usb.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 usb header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_wdt.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wdt.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 wdt header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_wwdt.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wwdt.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/inc/at32f435_437_xmc.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_xmc.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief at32f435_437 xmc header file
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_acc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_acc.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the acc firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_adc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_adc.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the adc firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_can.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_can.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the can firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_crc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crc.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the crc firmware library
**************************************************************************
* Copyright notice & Disclaimer

11
libraries/drivers/src/at32f435_437_crm.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_crm.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the crm firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -61,12 +61,12 @@ void crm_reset(void)
/* wait sclk switch status */
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
CRM->cfg = 0;
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
CRM->cfg = 0;
/* reset pllms pllns pllfr pllrcs bits */
CRM->pllcfg = 0x00033002U;
@ -367,6 +367,7 @@ void crm_flag_clear(uint32_t flag)
case CRM_LOWPOWER_RESET_FLAG:
case CRM_ALL_RESET_FLAG:
CRM->ctrlsts_bit.rstfc = TRUE;
while(CRM->ctrlsts_bit.rstfc == TRUE);
break;
case CRM_LICK_READY_INT_FLAG:
CRM->clkint_bit.lickstblfc = TRUE;

4
libraries/drivers/src/at32f435_437_dac.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dac.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the dac firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_debug.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_mcudbg.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the mcudbg firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_dma.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dma.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the dma firmware library
**************************************************************************
* Copyright notice & Disclaimer

83
libraries/drivers/src/at32f435_437_dvp.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_dvp.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the dvp firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -41,6 +41,17 @@
* @{
*/
/**
* @brief reset the dvp register
* @param none
* @retval none
*/
void dvp_reset(void)
{
crm_periph_reset(CRM_DVP_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_DVP_PERIPH_RESET, FALSE);
}
/**
* @brief enable or disable dvp capture
* @param new_state (TRUE or FALSE)
@ -76,16 +87,18 @@ void dvp_window_crop_enable(confirm_state new_state)
/**
* @brief set dvp cropping window configuration
* @param crop_x(0x0000~0x3FFF): cropping window horizontal start pixel
* @param crop_y(0x0000~0x1FFF): cropping window vertical start pixel
* @param crop_w(0x0001~0x3FFF): cropping window horizontal pixel number
* @param crop_h(0x0001~0x3FFF): cropping window vertical pixel number
* @param crop_x: cropping window horizontal start pixel
* @param crop_y: cropping window vertical start line
* @param crop_w: cropping window horizontal pixel number
* @param crop_h: cropping window vertical line number
* @param bytes: the number of bytes corresponding to one pixel
* eg. y8:bytes = 1, rgb565:bytes = 2
* @retval none
*/
void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h)
void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes)
{
DVP->cwst = ((crop_x * 2) | (crop_y << 16));
DVP->cwsz = ((crop_w * 2 - 1) | ((crop_h - 1) << 16));
DVP->cwst = ((crop_x * bytes) | (crop_y << 16));
DVP->cwsz = ((crop_w * bytes - 1) | ((crop_h - 1) << 16));
}
/**
@ -218,15 +231,15 @@ void dvp_enable(confirm_state new_state)
/**
* @brief set dvp zoomout select
* @param dvp_pcdse: pixel capture/drop selection extension (Only work when pcdc = 2)
* @param dvp_pcdes: pixel capture/drop selection extension (Only work when pcdc = 2)
* this parameter can be one of the following values:
* - DVP_PCDSE_CAP_FIRST
* - DVP_PCDSE_DROP_FIRST
* - DVP_PCDES_CAP_FIRST
* - DVP_PCDES_DROP_FIRST
* @retval none
*/
void dvp_zoomout_select(dvp_pcdse_type dvp_pcdse)
void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes)
{
DVP->actrl_bit.pcdse = dvp_pcdse;
DVP->actrl_bit.pcdes = dvp_pcdes;
}
/**
@ -265,7 +278,7 @@ void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_ty
* this parameter can be one of the following values:
* - DVP_STATUS_HSYN
* - DVP_STATUS_VSYN
* - DVP_STATUS_OFS
* - DVP_STATUS_OFNE
* @retval flag_status (SET or RESET)
*/
flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic)
@ -406,16 +419,16 @@ void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t sr
/**
* @brief set enhanced frame rate control configuration
* @param efrcfm(0x00~0x1F): original frame rate contorl factor
* @param efrcfn(0x00~0x1F): enhanced frame rate contorl factor
* @param efrcsf(0x00~0x1F): original frame rate contorl factor
* @param efrctf(0x00~0x1F): enhanced frame rate contorl factor
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dvp_enhanced_framerate_set(uint16_t efrcfm, uint16_t efrcfn, confirm_state new_state)
void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state)
{
if((!DVP->ctrl_bit.cfm) && (!DVP->ctrl_bit.bfrc) && (efrcfn <= efrcfm))
if((!DVP->ctrl_bit.cfm) && (!DVP->ctrl_bit.bfrc) && (efrctf <= efrcsf))
{
DVP->frf = (efrcfm | (efrcfn << 8));
DVP->frf = (efrcsf | (efrctf << 8));
}
DVP->actrl_bit.efrce = new_state;
@ -440,7 +453,7 @@ void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_sta
* - DVP_EFDF_BYPASS
* - DVP_EFDF_YUV422_UYVY
* - DVP_EFDF_YUV422_YUYV
* - DVP_EFDF_YUV444
* - DVP_EFDF_RGB565_555
* - DVP_EFDF_Y8
* @retval none
*/
@ -451,10 +464,10 @@ void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf)
/**
* @brief set dvp input data un-used condition/number configuration
* @param dvp_iduc: input data un-used condition
* @param dvp_idus: input data un-used condition
* this parameter can be one of the following values:
* - DVP_IDUC_MSB
* - DVP_IDUC_LSB
* - DVP_IDUS_MSB
* - DVP_IDUS_LSB
* @param dvp_idun: input data un-used number
* this parameter can be one of the following values:
* - DVP_IDUN_0
@ -463,9 +476,9 @@ void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf)
* - DVP_IDUN_6
* @retval none
*/
void dvp_input_data_unused_set(dvp_iduc_type dvp_iduc, dvp_idun_type dvp_idun)
void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun)
{
DVP->actrl_bit.iduc = dvp_iduc;
DVP->actrl_bit.idus = dvp_idus;
DVP->actrl_bit.idun = dvp_idun;
}
@ -484,20 +497,20 @@ void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt)
/**
* @brief set dvp hsync/vsync event interrupt strategy configuration
* @param dvp_hseis: hsync event interrupt strategy
* @param dvp_hseid: hsync event interrupt strategy
* this parameter can be one of the following values:
* - DVP_HSEIS_LINE_END
* - DVP_HSEIS_LINE_START
* @param dvp_vseis: vsync event interrupt strategy
* - DVP_HSEID_LINE_END
* - DVP_HSEID_LINE_START
* @param dvp_vseid: vsync event interrupt strategy
* this parameter can be one of the following values:
* - DVP_VSEIS_FRAME_END
* - DVP_VSEIS_FRMAE_START
* - DVP_VSEID_FRAME_END
* - DVP_VSEID_FRMAE_START
* @retval none
*/
void dvp_sync_event_interrupt_set(dvp_hseis_type dvp_hseis, dvp_vseis_type dvp_vseis)
void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid)
{
DVP->actrl_bit.hseis = dvp_hseis;
DVP->actrl_bit.vseis = dvp_vseis;
DVP->actrl_bit.hseid = dvp_hseid;
DVP->actrl_bit.vseid = dvp_vseid;
}
/**

4
libraries/drivers/src/at32f435_437_edma.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_edma.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the edma firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_emac.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_emac.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the emac firmware library
**************************************************************************
* Copyright notice & Disclaimer

10
libraries/drivers/src/at32f435_437_ertc.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_ertc.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the ertc firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -406,7 +406,7 @@ void ertc_calendar_get(ertc_time_type* time)
ertc_reg_time_type reg_tm;
ertc_reg_date_type reg_dt;
(void) (ERTC->sts);
UNUSED(ERTC->sts);
reg_tm.time = ERTC->time;
reg_dt.date = ERTC->date;
@ -724,8 +724,8 @@ uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x)
* - ERTC_WAT_CLK_ERTCCLK_DIV8: ERTC_CLK / 8.
* - ERTC_WAT_CLK_ERTCCLK_DIV4: ERTC_CLK / 4.
* - ERTC_WAT_CLK_ERTCCLK_DIV2: ERTC_CLK / 2.
* - ERTC_WAT_CLK_CK_A_16BITS: CK_A, wakeup counter = ERTC_WAT
* - ERTC_WAT_CLK_CK_A_17BITS: CK_A, wakeup counter = ERTC_WAT + 65535.
* - ERTC_WAT_CLK_CK_B_16BITS: CK_B, wakeup counter = ERTC_WAT
* - ERTC_WAT_CLK_CK_B_17BITS: CK_B, wakeup counter = ERTC_WAT + 65535.
* @retval none.
*/
void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock)

4
libraries/drivers/src/at32f435_437_exint.c
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@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_exint.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the exint firmware library
**************************************************************************
* Copyright notice & Disclaimer

579
libraries/drivers/src/at32f435_437_flash.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_flash.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the flash firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -359,41 +359,27 @@ flash_status_type flash_sector_erase(uint32_t sector_address)
flash_status_type status = FLASH_OPERATE_DONE;
if((sector_address >= FLASH_BANK1_START_ADDR) && (sector_address <= FLASH_BANK1_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl_bit.secers = TRUE;
FLASH->addr = sector_address;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* if the previous operation is completed, continue to erase the sector */
FLASH->ctrl_bit.secers = TRUE;
FLASH->addr = sector_address;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
/* disable the secers bit */
FLASH->ctrl_bit.secers = FALSE;
}
/* disable the secers bit */
FLASH->ctrl_bit.secers = FALSE;
}
else if((sector_address >= FLASH_BANK2_START_ADDR) && (sector_address <= FLASH_BANK2_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl2_bit.secers = TRUE;
FLASH->addr2 = sector_address;
FLASH->ctrl2_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* if the previous operation is completed, continue to erase the sector */
FLASH->ctrl2_bit.secers = TRUE;
FLASH->addr2 = sector_address;
FLASH->ctrl2_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
/* disable the secers bit */
FLASH->ctrl2_bit.secers = FALSE;
}
/* disable the secers bit */
FLASH->ctrl2_bit.secers = FALSE;
}
/* return the erase status */
@ -411,41 +397,27 @@ flash_status_type flash_block_erase(uint32_t block_address)
flash_status_type status = FLASH_OPERATE_DONE;
if((block_address >= FLASH_BANK1_START_ADDR) && (block_address <= FLASH_BANK1_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl_bit.blkers = TRUE;
FLASH->addr = block_address;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* if the previous operation is completed, continue to erase the blkers */
FLASH->ctrl_bit.blkers = TRUE;
FLASH->addr = block_address;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
/* disable the blkers bit */
FLASH->ctrl_bit.blkers = FALSE;
}
/* disable the blkers bit */
FLASH->ctrl_bit.blkers = FALSE;
}
else if((block_address >= FLASH_BANK2_START_ADDR) && (block_address <= FLASH_BANK2_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl2_bit.blkers = TRUE;
FLASH->addr2 = block_address;
FLASH->ctrl2_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* if the previous operation is completed, continue to erase the blkers */
FLASH->ctrl2_bit.blkers = TRUE;
FLASH->addr2 = block_address;
FLASH->ctrl2_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
/* disable the blkers bit */
FLASH->ctrl2_bit.blkers = FALSE;
}
/* disable the blkers bit */
FLASH->ctrl2_bit.blkers = FALSE;
}
/* return the erase status */
@ -461,21 +433,16 @@ flash_status_type flash_block_erase(uint32_t block_address)
flash_status_type flash_internal_all_erase(void)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* wait for last operation to be completed */
FLASH->ctrl_bit.bankers = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* if the previous operation is completed, continue to erase bank1 */
FLASH->ctrl_bit.bankers = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* disable the bankers bit */
FLASH->ctrl_bit.bankers = FALSE;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
/* disable the bankers bit */
FLASH->ctrl_bit.bankers = FALSE;
}
if(status == FLASH_OPERATE_DONE)
{
/* if the previous operation is completed, continue to erase bank2 */
@ -501,21 +468,16 @@ flash_status_type flash_internal_all_erase(void)
flash_status_type flash_bank1_erase(void)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* wait for last operation to be completed */
FLASH->ctrl_bit.bankers = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* if the previous operation is completed, continue to erase bank1 */
FLASH->ctrl_bit.bankers = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* disable the bankers bit */
FLASH->ctrl_bit.bankers = FALSE;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
/* disable the bankers bit */
FLASH->ctrl_bit.bankers = FALSE;
}
/* return the erase status */
return status;
}
@ -529,21 +491,16 @@ flash_status_type flash_bank1_erase(void)
flash_status_type flash_bank2_erase(void)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* wait for last operation to be completed */
FLASH->ctrl2_bit.bankers = TRUE;
FLASH->ctrl2_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* if the previous operation is completed, continue to erase bank2 */
FLASH->ctrl2_bit.bankers = TRUE;
FLASH->ctrl2_bit.erstr = TRUE;
/* disable the bankers bit */
FLASH->ctrl2_bit.bankers = FALSE;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
/* disable the bankers bit */
FLASH->ctrl2_bit.bankers = FALSE;
}
/* return the erase status */
return status;
}
@ -566,41 +523,36 @@ flash_status_type flash_user_system_data_erase(void)
fap_val = 0x0000;
}
/* wait for last operation to be completed */
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* erase the user system data */
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
/* erase the user system data */
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY))
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
/* restore the last flash access protection value */
USD->fap = (uint16_t)fap_val;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY))
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
/* restore the last flash access protection value */
USD->fap = (uint16_t)fap_val;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/*disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
/*disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
/* return the status */
return status;
}
@ -625,28 +577,23 @@ flash_status_type flash_eopb0_config(flash_usd_eopb0_type data)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* wait for last operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
if(status == FLASH_OPERATE_DONE)
{
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
/* restore the default eopb0 value */
USD->eopb0 = (uint16_t)data;
/* restore the default eopb0 value */
USD->eopb0 = (uint16_t)data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/*disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/*disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
/* return the status */
return status;
}
@ -663,35 +610,23 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data)
flash_status_type status = FLASH_OPERATE_DONE;
if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint32_t*)address = data;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint32_t*)address = data;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
}
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
}
else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl2_bit.fprgm = TRUE;
*(__IO uint32_t*)address = data;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->ctrl2_bit.fprgm = TRUE;
*(__IO uint32_t*)address = data;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl2_bit.fprgm = FALSE;
}
/* disable the fprgm bit */
FLASH->ctrl2_bit.fprgm = FALSE;
}
/* return the program status */
@ -710,35 +645,23 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data)
flash_status_type status = FLASH_OPERATE_DONE;
if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
}
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
}
else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl2_bit.fprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->ctrl2_bit.fprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl2_bit.fprgm = FALSE;
}
/* disable the fprgm bit */
FLASH->ctrl2_bit.fprgm = FALSE;
}
/* return the program status */
@ -758,35 +681,23 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data)
flash_status_type status = FLASH_OPERATE_DONE;
if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint8_t*)address = data;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint8_t*)address = data;
/* wait for operation to be completed */
status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
}
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
}
else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR))
{
/* wait for last operation to be completed */
FLASH->ctrl2_bit.fprgm = TRUE;
*(__IO uint8_t*)address = data;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->ctrl2_bit.fprgm = TRUE;
*(__IO uint8_t*)address = data;
/* wait for operation to be completed */
status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl2_bit.fprgm = FALSE;
}
/* disable the fprgm bit */
FLASH->ctrl2_bit.fprgm = FALSE;
}
/* return the program status */
return status;
@ -802,24 +713,28 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data)
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
if(address == USD_BASE)
{
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
if(data != 0xA5)
return FLASH_OPERATE_DONE;
}
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/* return the user system data program status */
return status;
}
@ -842,73 +757,69 @@ flash_status_type flash_epp_set(uint32_t *sector_bits)
epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF);
epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF);
epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF);
/* wait for last operation to be completed */
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
FLASH->ctrl_bit.usdprgm = TRUE;
USD->epp0 = epp_data[0];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
FLASH->ctrl_bit.usdprgm = TRUE;
USD->epp0 = epp_data[0];
USD->epp1 = epp_data[1];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
USD->epp1 = epp_data[1];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp2 = epp_data[2];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp3 = epp_data[3];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
sector_bits[1] = (uint32_t)(~sector_bits[1]);
epp_data[0] = (uint16_t)((sector_bits[1] >> 0) & 0xFF);
epp_data[1] = (uint16_t)((sector_bits[1] >> 8) & 0xFF);
epp_data[2] = (uint16_t)((sector_bits[1] >> 16) & 0xFF);
epp_data[3] = (uint16_t)((sector_bits[1] >> 24) & 0xFF);
if(status == FLASH_OPERATE_DONE)
{
USD->epp4 = epp_data[0];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp5 = epp_data[1];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp6 = epp_data[2];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp7 = epp_data[3];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp2 = epp_data[2];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp3 = epp_data[3];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
sector_bits[1] = (uint32_t)(~sector_bits[1]);
epp_data[0] = (uint16_t)((sector_bits[1] >> 0) & 0xFF);
epp_data[1] = (uint16_t)((sector_bits[1] >> 8) & 0xFF);
epp_data[2] = (uint16_t)((sector_bits[1] >> 16) & 0xFF);
epp_data[3] = (uint16_t)((sector_bits[1] >> 24) & 0xFF);
if(status == FLASH_OPERATE_DONE)
{
USD->epp4 = epp_data[0];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp5 = epp_data[1];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp6 = epp_data[2];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp7 = epp_data[3];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/* return the erase/program protection operation status */
return status;
}
@ -937,43 +848,41 @@ void flash_epp_status_get(uint32_t *sector_bits)
flash_status_type flash_fap_enable(confirm_state new_state)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if(status == FLASH_OPERATE_DONE)
{
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
/* restore the default eopb0 value */
USD->eopb0 = (uint16_t)0x0002;
/* Wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if(status == FLASH_OPERATE_DONE)
if(new_state == FALSE)
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
/* restore the default eopb0 value */
USD->eopb0 = (uint16_t)0x0002;
USD->fap = FAP_RELIEVE_KEY;
/* Wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
if(new_state == FALSE)
{
USD->fap = FAP_RELIEVE_KEY;
/* Wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
}
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
/* return the flash access protection operation status */
return status;
}
@ -1022,26 +931,22 @@ flag_status flash_fap_status_get(void)
flash_status_type flash_ssb_set(uint8_t usd_ssb)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* wait for last operation to be completed */
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->ssb = usd_ssb;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->ssb = usd_ssb;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
/* return the user system data program status */
return status;
}
@ -1097,30 +1002,32 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_
{
uint32_t slib_range;
flash_status_type status = FLASH_OPERATE_DONE;
/* wait for last operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/*check range param limits*/
if((start_sector>=inst_start_sector) || ((inst_start_sector > end_sector) && \
(inst_start_sector != 0xFFFF)) || (start_sector > end_sector))
return FLASH_PROGRAM_ERROR;
/* unlock slib cfg register */
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
/* configure slib, set pwd and range */
FLASH->slib_set_pwd = pwd;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
/* unlock slib cfg register */
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
/* configure slib, set pwd and range */
FLASH->slib_set_pwd = pwd;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
slib_range = ((uint32_t)(end_sector << 16) & FLASH_SLIB_END_SECTOR) | (start_sector & FLASH_SLIB_START_SECTOR);
FLASH->slib_set_range0 = slib_range;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
slib_range = (inst_start_sector & FLASH_SLIB_INST_START_SECTOR) | 0x80000000;
FLASH->slib_set_range1 = slib_range;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
slib_range = (inst_start_sector & FLASH_SLIB_INST_START_SECTOR) | 0x80000000;
FLASH->slib_set_range1 = slib_range;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
}
return status;
}

6
libraries/drivers/src/at32f435_437_gpio.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_gpio.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the gpio firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -357,7 +357,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
* @param port_value: specifies the value to be written to the port output data register.
* @retval none
*/
void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value)
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value)
{
gpio_x->odt = port_value;
}

16
libraries/drivers/src/at32f435_437_i2c.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_i2c.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the i2c firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -271,11 +271,13 @@ void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction)
}
/**
* @brief get the i2c slave received direction.
* @brief slave get the i2c transfer direction.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @retval the value of the received direction.
* @retval the value of the slave direction
* - I2C_DIR_TRANSMIT: master request a write transfer, slave enters receiver mode.
* - I2C_DIR_RECEIVE: master request a read transfer, slave enters transmitter mode.
*/
i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x)
{
@ -595,14 +597,14 @@ void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state
* - I2C_AUTO_STOP_MODE: auto generate stop mode.
* - I2C_SOFT_STOP_MODE: soft generate stop mode.
* - I2C_RELOAD_MODE: reload mode.
* @param start_stop: config gen start condition mode.
* @param start: config gen start condition mode.
* this parameter can be one of the following values:
* - I2C_WITHOUT_START: transfer data without start condition.
* - I2C_GEN_START_READ: read data and generate start.
* - I2C_GEN_START_WRITE: send data and generate start.
* @retval none
*/
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop)
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start)
{
uint32_t temp;
@ -613,7 +615,7 @@ void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload
temp &= ~0x03FF67FF;
/* transfer mode and address set */
temp |= address | rld_stop | start_stop;
temp |= address | rld_stop | start;
/* transfer counter set */
temp |= (uint32_t)cnt << 16;

4
libraries/drivers/src/at32f435_437_misc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_misc.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the misc firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_pwc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_pwc.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the pwc firmware library
**************************************************************************
* Copyright notice & Disclaimer

8
libraries/drivers/src/at32f435_437_qspi.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_qspi.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contain all the functions for qspi firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -67,7 +67,7 @@ void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state)
* - QSPI_SCK_MODE_3
* @retval none
*/
void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode)
void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode)
{
qspi_x->ctrl_bit.sckmode = new_mode;
}
@ -165,7 +165,7 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
* - QSPI_CMDSTS_FLAG
* @retval none
*/
void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag)
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag)
{
qspi_x->cmdsts = QSPI_CMDSTS_FLAG;
}

4
libraries/drivers/src/at32f435_437_scfg.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_scfg.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the system config firmware library
**************************************************************************
* Copyright notice & Disclaimer

21
libraries/drivers/src/at32f435_437_sdio.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_sdio.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the sdio firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -82,22 +82,11 @@ void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state)
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval flag_status (SET or RESET)
* @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF)
*/
flag_status sdio_power_status_get(sdio_type *sdio_x)
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x)
{
flag_status flag = RESET;
if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON)
{
flag = SET;
}
else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF)
{
flag = RESET;
}
return flag;
return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps);
}
/**

18
libraries/drivers/src/at32f435_437_spi.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_spi.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the spi firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -615,25 +615,23 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
*/
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
{
volatile uint32_t temp = 0;
temp = temp;
if(spi_i2s_flag == SPI_CCERR_FLAG)
spi_x->sts = ~SPI_CCERR_FLAG;
else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
temp = REG32(&spi_x->dt);
UNUSED(spi_x->dt);
else if(spi_i2s_flag == I2S_TUERR_FLAG)
temp = REG32(&spi_x->sts);
UNUSED(spi_x->sts);
else if(spi_i2s_flag == SPI_CSPAS_FLAG)
temp = REG32(&spi_x->sts);
UNUSED(spi_x->sts);
else if(spi_i2s_flag == SPI_MMERR_FLAG)
{
temp = REG32(&spi_x->sts);
UNUSED(spi_x->sts);
spi_x->ctrl1 = spi_x->ctrl1;
}
else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG)
{
temp = REG32(&spi_x->dt);
temp = REG32(&spi_x->sts);
UNUSED(spi_x->dt);
UNUSED(spi_x->sts);
}
}

31
libraries/drivers/src/at32f435_437_tmr.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_tmr.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the tmr firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -1141,15 +1141,15 @@ void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct,
* @param tmr_x: select the tmr peripheral.
* this parameter can be one of the following values:
* TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR20
* @param ti1_connect
* @param ch1_connect
* this parameter can be one of the following values:
* - TMR_CHANEL1_CONNECTED_C1IRAW
* - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR
* @retval none
*/
void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect)
void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect)
{
tmr_x->ctrl2_bit.c1insel = ti1_connect;
tmr_x->ctrl2_bit.c1insel = ch1_connect;
}
/**
@ -1411,6 +1411,7 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state
* - TMR_C2_FLAG
* - TMR_C3_FLAG
* - TMR_C4_FLAG
* - TMR_C5_FLAG
* - TMR_HALL_FLAG
* - TMR_TRIGGER_FLAG
* - TMR_BRK_FLAG
@ -1449,6 +1450,7 @@ flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
* - TMR_C2_FLAG
* - TMR_C3_FLAG
* - TMR_C4_FLAG
* - TMR_C5_FLAG
* - TMR_HALL_FLAG
* - TMR_TRIGGER_FLAG
* - TMR_BRK_FLAG
@ -1511,25 +1513,6 @@ void tmr_internal_clock_set(tmr_type *tmr_x)
tmr_x->stctrl_bit.smsel = TMR_SUB_MODE_DIABLE;
}
/**
* @brief set tmr output channel fast
* @param tmr_x: select the tmr peripheral.
* this parameter can be one of the following values:
* TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
* TMR11, TMR12, TMR13, TMR14, TMR20
* @param oc_fast
* this parameter can be one of the following values:
* - TMR_CHANNEL1_OUTPUT_FAST
* - TMR_CHANNEL2_OUTPUT_FAST
* - TMR_CHANNEL3_OUTPUT_FAST
* - TMR_CHANNEL4_OUTPUT_FAST
* @retval none
*/
void tmr_output_channel_fast_set(tmr_type *tmr_x, tmr_channel_output_fast_type oc_fast)
{
PERIPH_REG((uint32_t)(tmr_x), oc_fast) |= PERIPH_REG_BIT(oc_fast);
}
/**
* @brief set tmr output channel polarity
* @param tmr_x: select the tmr peripheral.

19
libraries/drivers/src/at32f435_437_usart.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usart.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the usart firmware library
**************************************************************************
* Copyright notice & Disclaimer
@ -618,6 +618,11 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
* - USART_BFF_FLAG:
* - USART_TDC_FLAG:
* - USART_RDBF_FLAG:
* - USART_PERR_FLAG:
* - USART_FERR_FLAG:
* - USART_NERR_FLAG:
* - USART_ROERR_FLAG:
* - USART_IDLEF_FLAG:
* @note
* - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software
* sequence: a read operation to usart sts register (usart_flag_get())
@ -630,7 +635,15 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
*/
void usart_flag_clear(usart_type* usart_x, uint32_t flag)
{
usart_x->sts = ~flag;
if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG))
{
UNUSED(usart_x->sts);
UNUSED(usart_x->dt);
}
else
{
usart_x->sts = ~flag;
}
}
/**

4
libraries/drivers/src/at32f435_437_usb.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_usb.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the usb firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_wdt.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wdt.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the wdt firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_wwdt.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_wwdt.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the wwdt firmware library
**************************************************************************
* Copyright notice & Disclaimer

4
libraries/drivers/src/at32f435_437_xmc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file at32f435_437_xmc.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief contains all the functions for the xmc firmware library
**************************************************************************
* Copyright notice & Disclaimer

421
middlewares/i2c_application_library/i2c_application.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file i2c_application.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief the driver library of the i2c peripheral
**************************************************************************
* Copyright notice & Disclaimer
@ -182,11 +182,28 @@ i2c_status_type i2c_wait_end(i2c_handle_type* hi2c, uint32_t timeout)
}
/**
* @brief wait for the flag.
* @brief wait for the flag to be set or reset, only BUSYF flag
* is waiting to be reset, and other flags are waiting to be set
* @param hi2c: the handle points to the operation information.
* @param flag: flag to wait.
* @param status: status to wait.
* @param event_check: flag to check while waiting for the flag.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - I2C_TDBE_FLAG: transmit data buffer empty flag.
* - I2C_TDIS_FLAG: send interrupt status.
* - I2C_RDBF_FLAG: receive data buffer full flag.
* - I2C_ADDRF_FLAG: 0~7 bit address match flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_TDC_FLAG: transmit data complete flag.
* - I2C_TCRLD_FLAG: transmission is complete, waiting to load data.
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* - I2C_BUSYF_FLAG: bus busy flag transmission mode.
* - I2C_SDIR_FLAG: slave data transmit direction.
* @param event_check: check other error flags while waiting for the flag.
* parameter as following values:
* - I2C_EVENT_CHECK_NONE
* - I2C_EVENT_CHECK_ACKFAIL
@ -194,46 +211,62 @@ i2c_status_type i2c_wait_end(i2c_handle_type* hi2c, uint32_t timeout)
* @param timeout: maximum waiting time.
* @retval i2c status.
*/
i2c_status_type i2c_wait_flag(i2c_handle_type* hi2c, uint32_t flag, flag_status status, uint32_t event_check, uint32_t timeout)
i2c_status_type i2c_wait_flag(i2c_handle_type* hi2c, uint32_t flag, uint32_t event_check, uint32_t timeout)
{
while(i2c_flag_get(hi2c->i2cx, flag) == status)
if(flag == I2C_BUSYF_FLAG)
{
/* check the ack fail flag */
if(event_check & I2C_EVENT_CHECK_ACKFAIL)
while(i2c_flag_get(hi2c->i2cx, flag) != RESET)
{
if(hi2c->i2cx->sts & I2C_ACKFAIL_FLAG)
/* check timeout */
if((timeout--) == 0)
{
/* clear ack fail flag */
i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
hi2c->error_code = I2C_ERR_TIMEOUT;
hi2c->error_code = I2C_ERR_ACKFAIL;
return I2C_ERR_ACKFAIL;
return I2C_ERR_TIMEOUT;
}
}
/* check the stop flag */
if(event_check & I2C_EVENT_CHECK_STOP)
}
else
{
while(i2c_flag_get(hi2c->i2cx, flag) == RESET)
{
if(hi2c->i2cx->sts & I2C_STOPF_FLAG)
/* check the ack fail flag */
if(event_check & I2C_EVENT_CHECK_ACKFAIL)
{
/* clear stop flag */
i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
if(i2c_flag_get(hi2c->i2cx, I2C_ACKFAIL_FLAG) != RESET)
{
/* clear ack fail flag */
i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
i2c_reset_ctrl2_register(hi2c);
hi2c->error_code = I2C_ERR_ACKFAIL;
hi2c->error_code = I2C_ERR_STOP;
return I2C_ERR_STOP;
return I2C_ERR_ACKFAIL;
}
}
}
/* check timeout */
if((timeout--) == 0)
{
hi2c->error_code = I2C_ERR_TIMEOUT;
/* check the stop flag */
if(event_check & I2C_EVENT_CHECK_STOP)
{
if(i2c_flag_get(hi2c->i2cx, I2C_STOPF_FLAG) != RESET)
{
/* clear stop flag */
i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
return I2C_ERR_TIMEOUT;
i2c_reset_ctrl2_register(hi2c);
hi2c->error_code = I2C_ERR_STOP;
return I2C_ERR_STOP;
}
}
/* check timeout */
if((timeout--) == 0)
{
hi2c->error_code = I2C_ERR_TIMEOUT;
return I2C_ERR_TIMEOUT;
}
}
}
@ -274,26 +307,26 @@ void i2c_dma_config(i2c_handle_type* hi2c, dma_channel_type* dma_channel, uint8_
* @brief start transfer in poll mode or interrupt mode.
* @param hi2c: the handle points to the operation information.
* @param address: slave address.
* @param start_stop: config gen start condition mode.
* @param start: config gen start condition mode.
* parameter as following values:
* - I2C_WITHOUT_START: transfer data without start condition.
* - I2C_GEN_START_READ: read data and generate start.
* - I2C_GEN_START_WRITE: send data and generate start.
* @retval i2c status.
*/
void i2c_start_transfer(i2c_handle_type* hi2c, uint16_t address, i2c_start_stop_mode_type start_stop)
void i2c_start_transfer(i2c_handle_type* hi2c, uint16_t address, i2c_start_mode_type start)
{
if (hi2c->pcount > MAX_TRANSFER_CNT)
{
hi2c->psize = MAX_TRANSFER_CNT;
i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_RELOAD_MODE, start_stop);
i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_RELOAD_MODE, start);
}
else
{
hi2c->psize = hi2c->pcount;
i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_AUTO_STOP_MODE, start_stop);
i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_AUTO_STOP_MODE, start);
}
}
@ -301,14 +334,14 @@ void i2c_start_transfer(i2c_handle_type* hi2c, uint16_t address, i2c_start_stop_
* @brief start transfer in dma mode.
* @param hi2c: the handle points to the operation information.
* @param address: slave address.
* @param start_stop: config gen start condition mode.
* @param start: config gen start condition mode.
* parameter as following values:
* - I2C_WITHOUT_START: transfer data without start condition.
* - I2C_GEN_START_READ: read data and generate start.
* - I2C_GEN_START_WRITE: send data and generate start.
* @retval i2c status.
*/
void i2c_start_transfer_dma(i2c_handle_type* hi2c, dma_channel_type* dma_channelx, uint16_t address, i2c_start_stop_mode_type start_stop)
void i2c_start_transfer_dma(i2c_handle_type* hi2c, dma_channel_type* dma_channelx, uint16_t address, i2c_start_mode_type start)
{
if (hi2c->pcount > MAX_TRANSFER_CNT)
{
@ -317,7 +350,7 @@ void i2c_start_transfer_dma(i2c_handle_type* hi2c, dma_channel_type* dma_channel
/* config dma */
i2c_dma_config(hi2c, dma_channelx, hi2c->pbuff, hi2c->psize);
i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_RELOAD_MODE, start_stop);
i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_RELOAD_MODE, start);
}
else
{
@ -326,7 +359,7 @@ void i2c_start_transfer_dma(i2c_handle_type* hi2c, dma_channel_type* dma_channel
/* config dma */
i2c_dma_config(hi2c, dma_channelx, hi2c->pbuff, hi2c->psize);
i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_AUTO_STOP_MODE, start_stop);
i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_AUTO_STOP_MODE, start);
}
}
@ -347,8 +380,8 @@ i2c_status_type i2c_master_transmit(i2c_handle_type* hi2c, uint16_t address, uin
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -358,8 +391,8 @@ i2c_status_type i2c_master_transmit(i2c_handle_type* hi2c, uint16_t address, uin
while (hi2c->pcount > 0)
{
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -371,8 +404,8 @@ i2c_status_type i2c_master_transmit(i2c_handle_type* hi2c, uint16_t address, uin
if ((hi2c->psize == 0) && (hi2c->pcount != 0))
{
/* wait for the tcrld falg to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
@ -382,8 +415,8 @@ i2c_status_type i2c_master_transmit(i2c_handle_type* hi2c, uint16_t address, uin
}
}
/* wait for the stop falg to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_4;
}
@ -413,8 +446,8 @@ i2c_status_type i2c_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, uint16_
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -422,8 +455,8 @@ i2c_status_type i2c_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, uint16_
/* enable acknowledge */
i2c_ack_enable(hi2c->i2cx, TRUE);
/* wait for the addr falg to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the addr flag to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -431,19 +464,10 @@ i2c_status_type i2c_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, uint16_
/* clear addr flag */
i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
/* wait for the dir falg to be reset */
if (i2c_wait_flag(hi2c, I2C_SDIR_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
return I2C_ERR_STEP_3;
}
while (hi2c->pcount > 0)
{
/* wait for the rdbf falg to be set */
if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, RESET, I2C_EVENT_CHECK_STOP, timeout) != I2C_OK)
/* wait for the rdbf flag to be set */
if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_STOP, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -464,8 +488,8 @@ i2c_status_type i2c_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, uint16_
hi2c->pcount--;
}
/* wait for the stop falg to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -476,8 +500,8 @@ i2c_status_type i2c_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, uint16_
/* clear stop flag */
i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -505,8 +529,8 @@ i2c_status_type i2c_master_receive(i2c_handle_type* hi2c, uint16_t address, uint
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -516,8 +540,8 @@ i2c_status_type i2c_master_receive(i2c_handle_type* hi2c, uint16_t address, uint
while (hi2c->pcount > 0)
{
/* wait for the rdbf falg to be set */
if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the rdbf flag to be set */
if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -529,8 +553,8 @@ i2c_status_type i2c_master_receive(i2c_handle_type* hi2c, uint16_t address, uint
if ((hi2c->psize == 0) && (hi2c->pcount != 0))
{
/* wait for the tcrld falg to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
@ -540,8 +564,8 @@ i2c_status_type i2c_master_receive(i2c_handle_type* hi2c, uint16_t address, uint
}
}
/* wait for the stop falg to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_4;
}
@ -571,8 +595,8 @@ i2c_status_type i2c_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata, uint16
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -580,8 +604,8 @@ i2c_status_type i2c_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata, uint16
/* enable acknowledge */
i2c_ack_enable(hi2c->i2cx, TRUE);
/* wait for the addr falg to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the addr flag to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -594,8 +618,8 @@ i2c_status_type i2c_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata, uint16
/* if 10-bit address mode is used */
if (hi2c->i2cx->ctrl2_bit.addr10 != RESET)
{
/* wait for the addr falg to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the addr flag to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -607,19 +631,10 @@ i2c_status_type i2c_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata, uint16
i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
}
/* wait for the dir falg to be set */
if (i2c_wait_flag(hi2c, I2C_SDIR_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
return I2C_ERR_STEP_4;
}
while (hi2c->pcount > 0)
{
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -632,8 +647,8 @@ i2c_status_type i2c_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata, uint16
hi2c->pcount--;
}
/* wait for the ackfail falg to be set */
if(i2c_wait_flag(hi2c, I2C_ACKFAIL_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the ackfail flag to be set */
if(i2c_wait_flag(hi2c, I2C_ACKFAIL_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_6;
}
@ -641,8 +656,8 @@ i2c_status_type i2c_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata, uint16
/* clear ack fail flag */
i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
/* wait for the stop falg to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -653,8 +668,8 @@ i2c_status_type i2c_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata, uint16
/* clear stop flag */
i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -688,8 +703,8 @@ i2c_status_type i2c_master_transmit_int(i2c_handle_type* hi2c, uint16_t address,
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -722,8 +737,8 @@ i2c_status_type i2c_slave_receive_int(i2c_handle_type* hi2c, uint8_t* pdata, uin
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -757,8 +772,8 @@ i2c_status_type i2c_master_receive_int(i2c_handle_type* hi2c, uint16_t address,
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -791,8 +806,8 @@ i2c_status_type i2c_slave_transmit_int(i2c_handle_type* hi2c, uint8_t* pdata, ui
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -828,8 +843,8 @@ i2c_status_type i2c_master_transmit_dma(i2c_handle_type* hi2c, uint16_t address,
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -868,8 +883,8 @@ i2c_status_type i2c_slave_receive_dma(i2c_handle_type* hi2c, uint8_t* pdata, uin
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -912,8 +927,8 @@ i2c_status_type i2c_master_receive_dma(i2c_handle_type* hi2c, uint16_t address,
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -952,8 +967,8 @@ i2c_status_type i2c_slave_transmit_dma(i2c_handle_type* hi2c, uint8_t* pdata, ui
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -994,8 +1009,8 @@ i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, uint16_t address, uint16
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -1003,8 +1018,8 @@ i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, uint16_t address, uint16
/* start transfer */
i2c_start_transfer(hi2c, address, I2C_GEN_START_WRITE);
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -1017,8 +1032,8 @@ i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, uint16_t address, uint16
while (hi2c->pcount > 0)
{
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
@ -1030,8 +1045,8 @@ i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, uint16_t address, uint16
if ((hi2c->psize == 0) && (hi2c->pcount != 0))
{
/* wait for the tcrld falg to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_4;
}
@ -1041,8 +1056,8 @@ i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, uint16_t address, uint16
}
}
/* wait for the stop falg to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_5;
}
@ -1074,8 +1089,8 @@ i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -1083,8 +1098,8 @@ i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_
/* start transfer */
i2c_transmit_set(hi2c->i2cx, address, 1, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -1092,8 +1107,8 @@ i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
/* wait for the tdc falg to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the tdc flag to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
@ -1103,8 +1118,8 @@ i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_
while (hi2c->pcount > 0)
{
/* wait for the rdbf falg to be set */
if (i2c_wait_flag(hi2c, I2C_RDBF_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the rdbf flag to be set */
if (i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_4;
}
@ -1116,8 +1131,8 @@ i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_
if ((hi2c->psize == 0) && (hi2c->pcount != 0))
{
/* wait for the tcrld falg to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_5;
}
@ -1127,8 +1142,8 @@ i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, uint16_t address, uint16_
}
}
/* wait for the stop falg to be set */
if (i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if (i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_6;
}
@ -1163,8 +1178,8 @@ i2c_status_type i2c_memory_write_int(i2c_handle_type* hi2c, uint16_t address, ui
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -1172,8 +1187,8 @@ i2c_status_type i2c_memory_write_int(i2c_handle_type* hi2c, uint16_t address, ui
/* start transfer */
i2c_start_transfer(hi2c, address, I2C_GEN_START_WRITE);
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -1210,8 +1225,8 @@ i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, uint16_t address, uin
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -1219,8 +1234,8 @@ i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, uint16_t address, uin
/* start transfer */
i2c_transmit_set(hi2c->i2cx, address, 1, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -1228,8 +1243,8 @@ i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, uint16_t address, uin
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
/* wait for the tdc falg to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the tdc flag to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
@ -1267,8 +1282,8 @@ i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, uint16_t address, ui
/* disable dma request */
i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_TX, FALSE);
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -1276,8 +1291,8 @@ i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, uint16_t address, ui
/* transfer config */
i2c_transmit_set(hi2c->i2cx, address, 1, I2C_RELOAD_MODE, I2C_GEN_START_WRITE);
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -1285,8 +1300,8 @@ i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, uint16_t address, ui
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
/* wait for the tcrld falg to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
@ -1324,8 +1339,8 @@ i2c_status_type i2c_memory_read_dma(i2c_handle_type* hi2c, uint16_t address, uin
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -1333,8 +1348,8 @@ i2c_status_type i2c_memory_read_dma(i2c_handle_type* hi2c, uint16_t address, uin
/* start transfer */
i2c_transmit_set(hi2c->i2cx, address, 1, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -1342,8 +1357,8 @@ i2c_status_type i2c_memory_read_dma(i2c_handle_type* hi2c, uint16_t address, uin
/* send memory address */
i2c_data_send(hi2c->i2cx, mem_address);
/* wait for the tdc falg to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the tdc flag to be set */
if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
@ -1380,8 +1395,8 @@ i2c_status_type i2c_smbus_master_transmit(i2c_handle_type* hi2c, uint16_t addres
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -1399,8 +1414,8 @@ i2c_status_type i2c_smbus_master_transmit(i2c_handle_type* hi2c, uint16_t addres
while (hi2c->pcount > 0)
{
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -1412,8 +1427,8 @@ i2c_status_type i2c_smbus_master_transmit(i2c_handle_type* hi2c, uint16_t addres
if ((hi2c->psize == 0) && (hi2c->pcount != 0))
{
/* wait for the tcrld falg to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
@ -1423,8 +1438,8 @@ i2c_status_type i2c_smbus_master_transmit(i2c_handle_type* hi2c, uint16_t addres
}
}
/* wait for the stop falg to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_4;
}
@ -1463,8 +1478,8 @@ i2c_status_type i2c_smbus_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, u
/* enable acknowledge */
i2c_ack_enable(hi2c->i2cx, TRUE);
/* wait for the addr falg to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the addr flag to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -1478,19 +1493,10 @@ i2c_status_type i2c_smbus_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, u
/* clear addr flag */
i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
/* wait for the dir falg to be reset */
if (i2c_wait_flag(hi2c, I2C_SDIR_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
return I2C_ERR_STEP_2;
}
while (hi2c->pcount > 0)
{
/* wait for the rdbf falg to be set */
if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, RESET, I2C_EVENT_CHECK_STOP, timeout) != I2C_OK)
/* wait for the rdbf flag to be set */
if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_STOP, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -1511,8 +1517,8 @@ i2c_status_type i2c_smbus_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, u
hi2c->pcount--;
}
/* wait for the stop falg to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -1523,8 +1529,8 @@ i2c_status_type i2c_smbus_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, u
/* clear stop flag */
i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -1555,8 +1561,8 @@ i2c_status_type i2c_smbus_master_receive(i2c_handle_type* hi2c, uint16_t address
hi2c->error_code = I2C_OK;
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_1;
}
@ -1572,8 +1578,8 @@ i2c_status_type i2c_smbus_master_receive(i2c_handle_type* hi2c, uint16_t address
while (hi2c->pcount > 0)
{
/* wait for the rdbf falg to be set */
if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the rdbf flag to be set */
if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_2;
}
@ -1585,8 +1591,8 @@ i2c_status_type i2c_smbus_master_receive(i2c_handle_type* hi2c, uint16_t address
if ((hi2c->psize == 0) && (hi2c->pcount != 0))
{
/* wait for the tcrld falg to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the tcrld flag to be set */
if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_3;
}
@ -1596,8 +1602,8 @@ i2c_status_type i2c_smbus_master_receive(i2c_handle_type* hi2c, uint16_t address
}
}
/* wait for the stop falg to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
return I2C_ERR_STEP_4;
}
@ -1636,8 +1642,8 @@ i2c_status_type i2c_smbus_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata,
/* enable acknowledge */
i2c_ack_enable(hi2c->i2cx, TRUE);
/* wait for the addr falg to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the addr flag to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -1660,8 +1666,8 @@ i2c_status_type i2c_smbus_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata,
/* if 10-bit address mode is used */
if (hi2c->i2cx->ctrl2_bit.addr10 != RESET)
{
/* wait for the addr falg to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the addr flag to be set */
if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -1679,21 +1685,12 @@ i2c_status_type i2c_smbus_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata,
i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
}
/* wait for the dir falg to be set */
if (i2c_wait_flag(hi2c, I2C_SDIR_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
return I2C_ERR_STEP_3;
}
hi2c->pcount--;
while (hi2c->pcount > 0)
{
/* wait for the tdis falg to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, RESET, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
/* wait for the tdis flag to be set */
if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -1706,8 +1703,8 @@ i2c_status_type i2c_smbus_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata,
hi2c->pcount--;
}
/* wait for the ackfail falg to be set */
if(i2c_wait_flag(hi2c, I2C_ACKFAIL_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the ackfail flag to be set */
if(i2c_wait_flag(hi2c, I2C_ACKFAIL_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
return I2C_ERR_STEP_5;
}
@ -1715,8 +1712,8 @@ i2c_status_type i2c_smbus_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata,
/* clear ack fail flag */
i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
/* wait for the stop falg to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, RESET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the stop flag to be set */
if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);
@ -1727,8 +1724,8 @@ i2c_status_type i2c_smbus_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata,
/* clear stop flag */
i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
/* wait for the busy falg to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, SET, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
/* wait for the busy flag to be reset */
if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
{
/* disable acknowledge */
i2c_ack_enable(hi2c->i2cx, FALSE);

6
middlewares/i2c_application_library/i2c_application.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file i2c_application.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief i2c application libray header file
**************************************************************************
* Copyright notice & Disclaimer
@ -134,7 +134,7 @@ void i2c_config (i2c_handle_type* hi2c);
void i2c_lowlevel_init (i2c_handle_type* hi2c);
void i2c_reset_ctrl2_register (i2c_handle_type* hi2c);
i2c_status_type i2c_wait_end (i2c_handle_type* hi2c, uint32_t timeout);
i2c_status_type i2c_wait_flag (i2c_handle_type* hi2c, uint32_t flag, flag_status status, uint32_t event_check, uint32_t timeout);
i2c_status_type i2c_wait_flag (i2c_handle_type* hi2c, uint32_t flag, uint32_t event_check, uint32_t timeout);
i2c_status_type i2c_master_transmit (i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout);
i2c_status_type i2c_master_receive (i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout);

4
middlewares/usb_drivers/inc/usb_core.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_core.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb core header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usb_std.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_std.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb standard header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbd_core.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_core.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb device core header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbd_int.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_int.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb interrupt header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbd_sdr.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_sdr.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbh_core.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_core.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb host core header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbh_ctrl.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_ctrl.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/inc/usbh_int.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_int.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usb_core.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usb_core.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb driver
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbd_core.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_core.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb device driver
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbd_int.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_int.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb interrupt request
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbd_sdr.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbd_sdr.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb standard device request
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbh_core.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_core.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb host driver
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbh_ctrl.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_ctrl.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb host control request
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usb_drivers/src/usbh_int.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file usbh_int.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb host interrupt request
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio/audio_class.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio class type
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio/audio_class.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio class file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio/audio_conf.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_conf.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio config
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio/audio_desc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio device descriptor
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio/audio_desc.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio descriptor header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_conf.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_conf.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio config
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_hid_class.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio class type
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_hid_class.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_class.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio class file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_hid_desc.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio device descriptor
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/audio_hid/audio_hid_desc.h
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file audio_desc.h
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb audio descriptor header file
**************************************************************************
* Copyright notice & Disclaimer

4
middlewares/usbd_class/cdc/cdc_class.c
View File

@ -1,8 +1,8 @@
/**
**************************************************************************
* @file cdc_class.c
* @version v2.0.8
* @date 2022-04-25
* @version v2.0.9
* @date 2022-06-28
* @brief usb cdc class type
**************************************************************************
* Copyright notice & Disclaimer

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