2021-03-19 10:05:24 -07:00
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/*
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2021-04-06 03:55:13 -07:00
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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2021-03-19 10:05:24 -07:00
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file TIM/hal_pwm_lld.h
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2021-04-06 00:11:47 -07:00
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* @brief GD32 PWM subsystem low level driver header.
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*
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* @addtogroup PWM
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* @{
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*/
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#ifndef HAL_PWM_LLD_H
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#define HAL_PWM_LLD_H
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#if HAL_USE_PWM || defined(__DOXYGEN__)
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2021-03-20 12:53:26 -07:00
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#include "gd32_tim.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Number of PWM channels per PWM driver.
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*/
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#define PWM_CHANNELS GD32_TIM_MAX_CHANNELS
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/**
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* @name GD32-specific PWM complementary output mode macros
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* @{
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*/
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/**
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* @brief Complementary output modes mask.
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* @note This is an GD32-specific setting.
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*/
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#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0
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/**
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* @brief Complementary output not driven.
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* @note This is an GD32-specific setting.
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*/
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#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00
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/**
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* @brief Complementary output, active is logic level one.
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* @note This is an GD32-specific setting.
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* @note This setting is only available if the configuration option
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* @p GD32_PWM_USE_ADVANCED is set to TRUE and only for advanced
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* timer TIM0.
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*/
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#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10
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/**
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* @brief Complementary output, active is logic level zero.
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* @note This is an GD32-specific setting.
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* @note This setting is only available if the configuration option
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* @p GD32_PWM_USE_ADVANCED is set to TRUE and only for advanced
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* timer TIM0.
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*/
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#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief If advanced timer features switch.
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* @details If set to @p TRUE the advanced features for TIM0 is
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* enabled.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_ADVANCED FALSE
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#endif
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/**
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* @brief PWMD1 driver enable switch.
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* @details If set to @p TRUE the support for PWMD1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM0) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM0 FALSE
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#endif
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/**
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* @brief PWMD2 driver enable switch.
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* @details If set to @p TRUE the support for PWMD2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM1) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM1 FALSE
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#endif
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/**
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* @brief PWMD3 driver enable switch.
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* @details If set to @p TRUE the support for PWMD3 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM2) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM2 FALSE
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#endif
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/**
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* @brief PWMD4 driver enable switch.
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* @details If set to @p TRUE the support for PWMD4 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM3) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM3 FALSE
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#endif
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/**
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* @brief PWMD5 driver enable switch.
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* @details If set to @p TRUE the support for PWMD5 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM4) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM4 FALSE
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#endif
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/**
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* @brief PWMD1 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM0_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM0_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD2 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM1_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD3 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM2_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD4 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM3_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD5 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM4_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD1 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM0_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/**
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* @brief PWMD2 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM1_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/**
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* @brief PWMD3 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM2_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/**
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* @brief PWMD4 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM3_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/**
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* @brief PWMD5 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM4_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/** @} */
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/*===========================================================================*/
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/* Configuration checks. */
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/*===========================================================================*/
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#if !defined(GD32_HAS_TIM0)
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#define GD32_HAS_TIM0 FALSE
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#endif
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#if !defined(GD32_HAS_TIM1)
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#define GD32_HAS_TIM1 FALSE
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#endif
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#if !defined(GD32_HAS_TIM2)
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#define GD32_HAS_TIM2 FALSE
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#endif
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#if !defined(GD32_HAS_TIM3)
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#define GD32_HAS_TIM3 FALSE
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#endif
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#if !defined(GD32_HAS_TIM4)
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#define GD32_HAS_TIM4 FALSE
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#endif
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#if GD32_PWM_USE_TIM0 && !GD32_HAS_TIM0
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#error "TIM0 not present in the selected device"
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#endif
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#if GD32_PWM_USE_TIM1 && !GD32_HAS_TIM1
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#error "TIM1 not present in the selected device"
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#endif
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#if GD32_PWM_USE_TIM2 && !GD32_HAS_TIM2
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#error "TIM2 not present in the selected device"
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#endif
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#if GD32_PWM_USE_TIM3 && !GD32_HAS_TIM3
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#error "TIM3 not present in the selected device"
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#endif
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#if GD32_PWM_USE_TIM4 && !GD32_HAS_TIM4
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#error "TIM4 not present in the selected device"
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#endif
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2021-03-30 09:39:36 -07:00
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#if !GD32_PWM_USE_TIM0 && !GD32_PWM_USE_TIM1 && \
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!GD32_PWM_USE_TIM2 && !GD32_PWM_USE_TIM3 && \
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!GD32_PWM_USE_TIM4
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#error "PWM driver activated but no TIM peripheral assigned"
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#endif
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#if GD32_PWM_USE_ADVANCED && !GD32_PWM_USE_TIM0
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#error "advanced mode selected but no advanced timer assigned"
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#endif
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/* Checks on allocation of TIMx units.*/
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#if GD32_PWM_USE_TIM0
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#if defined(GD32_TIM0_IS_USED)
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#error "PWMD1 requires TIM0 but the timer is already used"
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#else
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#define GD32_TIM0_IS_USED
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#endif
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#endif
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#if GD32_PWM_USE_TIM1
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#if defined(GD32_TIM1_IS_USED)
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#error "PWMD2 requires TIM1 but the timer is already used"
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#else
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#define GD32_TIM1_IS_USED
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#endif
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#endif
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#if GD32_PWM_USE_TIM2
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#if defined(GD32_TIM2_IS_USED)
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#error "PWMD3 requires TIM2 but the timer is already used"
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#else
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#define GD32_TIM2_IS_USED
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#endif
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#endif
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#if GD32_PWM_USE_TIM3
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#if defined(GD32_TIM3_IS_USED)
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#error "PWMD4 requires TIM3 but the timer is already used"
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#else
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#define GD32_TIM3_IS_USED
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#endif
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#endif
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#if GD32_PWM_USE_TIM4
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#if defined(GD32_TIM4_IS_USED)
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#error "PWMD5 requires TIM4 but the timer is already used"
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#else
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#define GD32_TIM4_IS_USED
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#endif
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#endif
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|
|
|
|
2021-03-30 09:39:36 -07:00
|
|
|
/* IRQ priority checks.*/
|
|
|
|
#if GD32_PWM_USE_TIM0 && !defined(GD32_TIM0_SUPPRESS_ISR) && \
|
|
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM0_IRQ_PRIORITY)
|
|
|
|
#error "Invalid IRQ priority assigned to TIM0"
|
2021-03-19 10:05:24 -07:00
|
|
|
#endif
|
|
|
|
|
2021-03-20 11:47:59 -07:00
|
|
|
#if GD32_PWM_USE_TIM1 && !defined(GD32_TIM1_SUPPRESS_ISR) && \
|
|
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM1_IRQ_PRIORITY)
|
2021-03-19 10:05:24 -07:00
|
|
|
#error "Invalid IRQ priority assigned to TIM1"
|
|
|
|
#endif
|
|
|
|
|
2021-03-20 11:47:59 -07:00
|
|
|
#if GD32_PWM_USE_TIM2 && !defined(GD32_TIM2_SUPPRESS_ISR) && \
|
|
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM2_IRQ_PRIORITY)
|
2021-03-19 10:05:24 -07:00
|
|
|
#error "Invalid IRQ priority assigned to TIM2"
|
|
|
|
#endif
|
|
|
|
|
2021-03-20 11:47:59 -07:00
|
|
|
#if GD32_PWM_USE_TIM3 && !defined(GD32_TIM3_SUPPRESS_ISR) && \
|
|
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM3_IRQ_PRIORITY)
|
2021-03-19 10:05:24 -07:00
|
|
|
#error "Invalid IRQ priority assigned to TIM3"
|
|
|
|
#endif
|
|
|
|
|
2021-03-20 11:47:59 -07:00
|
|
|
#if GD32_PWM_USE_TIM4 && !defined(GD32_TIM4_SUPPRESS_ISR) && \
|
|
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM4_IRQ_PRIORITY)
|
2021-03-19 10:05:24 -07:00
|
|
|
#error "Invalid IRQ priority assigned to TIM4"
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
/* Driver data structures and types. */
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Type of a PWM mode.
|
|
|
|
*/
|
|
|
|
typedef uint32_t pwmmode_t;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Type of a PWM channel.
|
|
|
|
*/
|
|
|
|
typedef uint8_t pwmchannel_t;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Type of a channels mask.
|
|
|
|
*/
|
|
|
|
typedef uint32_t pwmchnmsk_t;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Type of a PWM counter.
|
|
|
|
*/
|
|
|
|
typedef uint32_t pwmcnt_t;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Type of a PWM driver channel configuration structure.
|
|
|
|
*/
|
|
|
|
typedef struct {
|
|
|
|
/**
|
|
|
|
* @brief Channel active logic level.
|
|
|
|
*/
|
|
|
|
pwmmode_t mode;
|
|
|
|
/**
|
|
|
|
* @brief Channel callback pointer.
|
|
|
|
* @note This callback is invoked on the channel compare event. If set to
|
|
|
|
* @p NULL then the callback is disabled.
|
|
|
|
*/
|
|
|
|
pwmcallback_t callback;
|
|
|
|
/* End of the mandatory fields.*/
|
|
|
|
} PWMChannelConfig;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Type of a PWM driver configuration structure.
|
|
|
|
*/
|
|
|
|
typedef struct {
|
|
|
|
/**
|
|
|
|
* @brief Timer clock in Hz.
|
|
|
|
* @note The low level can use assertions in order to catch invalid
|
|
|
|
* frequency specifications.
|
|
|
|
*/
|
|
|
|
uint32_t frequency;
|
|
|
|
/**
|
|
|
|
* @brief PWM period in ticks.
|
|
|
|
* @note The low level can use assertions in order to catch invalid
|
|
|
|
* period specifications.
|
|
|
|
*/
|
|
|
|
pwmcnt_t period;
|
|
|
|
/**
|
|
|
|
* @brief Periodic callback pointer.
|
|
|
|
* @note This callback is invoked on PWM counter reset. If set to
|
|
|
|
* @p NULL then the callback is disabled.
|
|
|
|
*/
|
|
|
|
pwmcallback_t callback;
|
|
|
|
/**
|
|
|
|
* @brief Channels configurations.
|
|
|
|
*/
|
|
|
|
PWMChannelConfig channels[PWM_CHANNELS];
|
|
|
|
/* End of the mandatory fields.*/
|
|
|
|
/**
|
|
|
|
* @brief TIM CR2 register initialization data.
|
|
|
|
* @note The value of this field should normally be equal to zero.
|
|
|
|
*/
|
2021-03-30 02:04:49 -07:00
|
|
|
uint32_t ctl1;
|
2021-03-20 11:47:59 -07:00
|
|
|
#if GD32_PWM_USE_ADVANCED || defined(__DOXYGEN__)
|
2021-03-19 10:05:24 -07:00
|
|
|
/**
|
|
|
|
* @brief TIM BDTR (break & dead-time) register initialization data.
|
|
|
|
* @note The value of this field should normally be equal to zero.
|
|
|
|
*/ \
|
2021-03-30 02:04:49 -07:00
|
|
|
uint32_t cchp;
|
2021-03-19 10:05:24 -07:00
|
|
|
#endif
|
|
|
|
/**
|
|
|
|
* @brief TIM DIER register initialization data.
|
|
|
|
* @note The value of this field should normally be equal to zero.
|
|
|
|
* @note Only the DMA-related bits can be specified in this field.
|
|
|
|
*/
|
2021-03-30 02:04:49 -07:00
|
|
|
uint32_t dmainten;
|
2021-03-19 10:05:24 -07:00
|
|
|
} PWMConfig;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Structure representing a PWM driver.
|
|
|
|
*/
|
|
|
|
struct PWMDriver {
|
|
|
|
/**
|
|
|
|
* @brief Driver state.
|
|
|
|
*/
|
|
|
|
pwmstate_t state;
|
|
|
|
/**
|
|
|
|
* @brief Current driver configuration data.
|
|
|
|
*/
|
|
|
|
const PWMConfig *config;
|
|
|
|
/**
|
|
|
|
* @brief Current PWM period in ticks.
|
|
|
|
*/
|
|
|
|
pwmcnt_t period;
|
|
|
|
/**
|
|
|
|
* @brief Mask of the enabled channels.
|
|
|
|
*/
|
|
|
|
pwmchnmsk_t enabled;
|
|
|
|
/**
|
|
|
|
* @brief Number of channels in this instance.
|
|
|
|
*/
|
|
|
|
pwmchannel_t channels;
|
|
|
|
#if defined(PWM_DRIVER_EXT_FIELDS)
|
|
|
|
PWM_DRIVER_EXT_FIELDS
|
|
|
|
#endif
|
|
|
|
/* End of the mandatory fields.*/
|
|
|
|
/**
|
|
|
|
* @brief Timer base clock.
|
|
|
|
*/
|
|
|
|
uint32_t clock;
|
|
|
|
/**
|
|
|
|
* @brief Pointer to the TIMx registers block.
|
|
|
|
*/
|
2021-03-20 12:53:26 -07:00
|
|
|
gd32_tim_t *tim;
|
2021-03-19 10:05:24 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
/* Driver macros. */
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Changes the period the PWM peripheral.
|
|
|
|
* @details This function changes the period of a PWM unit that has already
|
|
|
|
* been activated using @p pwmStart().
|
|
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
|
|
|
* @post The PWM unit period is changed to the new value.
|
|
|
|
* @note The function has effect at the next cycle start.
|
|
|
|
* @note If a period is specified that is shorter than the pulse width
|
|
|
|
* programmed in one of the channels then the behavior is not
|
|
|
|
* guaranteed.
|
|
|
|
*
|
|
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
|
|
|
* @param[in] period new cycle time in ticks
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
#define pwm_lld_change_period(pwmp, period) \
|
2021-03-30 02:04:49 -07:00
|
|
|
((pwmp)->tim->CAR = ((period) - 1))
|
2021-03-19 10:05:24 -07:00
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
/* External declarations. */
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
2021-03-30 09:39:36 -07:00
|
|
|
#if GD32_PWM_USE_TIM0 && !defined(__DOXYGEN__)
|
2021-03-19 10:05:24 -07:00
|
|
|
extern PWMDriver PWMD1;
|
|
|
|
#endif
|
|
|
|
|
2021-03-30 09:39:36 -07:00
|
|
|
#if GD32_PWM_USE_TIM1 && !defined(__DOXYGEN__)
|
2021-03-19 10:05:24 -07:00
|
|
|
extern PWMDriver PWMD2;
|
|
|
|
#endif
|
|
|
|
|
2021-03-30 09:39:36 -07:00
|
|
|
#if GD32_PWM_USE_TIM2 && !defined(__DOXYGEN__)
|
2021-03-19 10:05:24 -07:00
|
|
|
extern PWMDriver PWMD3;
|
|
|
|
#endif
|
|
|
|
|
2021-03-30 09:39:36 -07:00
|
|
|
#if GD32_PWM_USE_TIM3 && !defined(__DOXYGEN__)
|
2021-03-19 10:05:24 -07:00
|
|
|
extern PWMDriver PWMD4;
|
|
|
|
#endif
|
|
|
|
|
2021-03-30 09:39:36 -07:00
|
|
|
#if GD32_PWM_USE_TIM4 && !defined(__DOXYGEN__)
|
2021-03-19 10:05:24 -07:00
|
|
|
extern PWMDriver PWMD5;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
extern "C" {
|
|
|
|
#endif
|
|
|
|
void pwm_lld_init(void);
|
|
|
|
void pwm_lld_start(PWMDriver *pwmp);
|
|
|
|
void pwm_lld_stop(PWMDriver *pwmp);
|
|
|
|
void pwm_lld_enable_channel(PWMDriver *pwmp,
|
|
|
|
pwmchannel_t channel,
|
|
|
|
pwmcnt_t width);
|
|
|
|
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
|
|
|
|
void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
|
|
|
|
void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
|
|
|
|
void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
|
|
|
|
pwmchannel_t channel);
|
|
|
|
void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
|
|
|
|
pwmchannel_t channel);
|
|
|
|
void pwm_lld_serve_interrupt(PWMDriver *pwmp);
|
|
|
|
#ifdef __cplusplus
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#endif /* HAL_USE_PWM */
|
|
|
|
|
|
|
|
#endif /* HAL_PWM_LLD_H */
|
|
|
|
|
|
|
|
/** @} */
|