531 lines
15 KiB
C
531 lines
15 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file TIM/hal_pwm_lld.h
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* @brief GD32 PWM subsystem low level driver header.
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*
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* @addtogroup PWM
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* @{
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*/
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#ifndef HAL_PWM_LLD_H
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#define HAL_PWM_LLD_H
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#if HAL_USE_PWM || defined(__DOXYGEN__)
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#include "gd32_tim.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Number of PWM channels per PWM driver.
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*/
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#define PWM_CHANNELS GD32_TIM_MAX_CHANNELS
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/**
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* @name GD32-specific PWM complementary output mode macros
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* @{
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*/
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/**
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* @brief Complementary output modes mask.
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* @note This is an GD32-specific setting.
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*/
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#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0
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/**
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* @brief Complementary output not driven.
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* @note This is an GD32-specific setting.
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*/
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#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00
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/**
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* @brief Complementary output, active is logic level one.
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* @note This is an GD32-specific setting.
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* @note This setting is only available if the configuration option
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* @p GD32_PWM_USE_ADVANCED is set to TRUE and only for advanced
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* timer TIM0.
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*/
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#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10
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/**
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* @brief Complementary output, active is logic level zero.
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* @note This is an GD32-specific setting.
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* @note This setting is only available if the configuration option
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* @p GD32_PWM_USE_ADVANCED is set to TRUE and only for advanced
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* timer TIM0.
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*/
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#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief If advanced timer features switch.
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* @details If set to @p TRUE the advanced features for TIM0 is
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* enabled.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_ADVANCED FALSE
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#endif
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/**
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* @brief PWMD1 driver enable switch.
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* @details If set to @p TRUE the support for PWMD1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM0) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM0 FALSE
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#endif
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/**
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* @brief PWMD2 driver enable switch.
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* @details If set to @p TRUE the support for PWMD2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM1) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM1 FALSE
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#endif
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/**
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* @brief PWMD3 driver enable switch.
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* @details If set to @p TRUE the support for PWMD3 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM2) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM2 FALSE
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#endif
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/**
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* @brief PWMD4 driver enable switch.
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* @details If set to @p TRUE the support for PWMD4 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM3) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM3 FALSE
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#endif
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/**
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* @brief PWMD5 driver enable switch.
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* @details If set to @p TRUE the support for PWMD5 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_PWM_USE_TIM4) || defined(__DOXYGEN__)
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#define GD32_PWM_USE_TIM4 FALSE
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#endif
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/**
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* @brief PWMD1 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM0_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM0_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD2 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM1_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD3 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM2_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD4 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM3_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD5 interrupt priority level setting.
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*/
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#if !defined(GD32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM4_IRQ_PRIORITY 7
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#endif
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/**
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* @brief PWMD1 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM0_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/**
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* @brief PWMD2 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM1_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/**
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* @brief PWMD3 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM2_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/**
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* @brief PWMD4 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM3_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/**
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* @brief PWMD5 interrupt trigger setting.
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*/
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#if !defined(GD32_PWM_TIM4_IRQ_TRIGGER) || defined(__DOXYGEN__)
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#define GD32_PWM_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#endif
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/** @} */
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/*===========================================================================*/
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/* Configuration checks. */
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/*===========================================================================*/
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#if !defined(GD32_HAS_TIM0)
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#define GD32_HAS_TIM0 FALSE
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#endif
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#if !defined(GD32_HAS_TIM1)
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#define GD32_HAS_TIM1 FALSE
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#endif
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#if !defined(GD32_HAS_TIM2)
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#define GD32_HAS_TIM2 FALSE
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#endif
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#if !defined(GD32_HAS_TIM3)
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#define GD32_HAS_TIM3 FALSE
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#endif
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#if !defined(GD32_HAS_TIM4)
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#define GD32_HAS_TIM4 FALSE
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#endif
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#if GD32_PWM_USE_TIM0 && !GD32_HAS_TIM0
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#error "TIM0 not present in the selected device"
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#endif
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#if GD32_PWM_USE_TIM1 && !GD32_HAS_TIM1
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#error "TIM1 not present in the selected device"
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#endif
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#if GD32_PWM_USE_TIM2 && !GD32_HAS_TIM2
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#error "TIM2 not present in the selected device"
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#endif
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#if GD32_PWM_USE_TIM3 && !GD32_HAS_TIM3
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#error "TIM3 not present in the selected device"
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#endif
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#if GD32_PWM_USE_TIM4 && !GD32_HAS_TIM4
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#error "TIM4 not present in the selected device"
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#endif
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#if !GD32_PWM_USE_TIM0 && !GD32_PWM_USE_TIM1 && \
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!GD32_PWM_USE_TIM2 && !GD32_PWM_USE_TIM3 && \
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!GD32_PWM_USE_TIM4
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#error "PWM driver activated but no TIM peripheral assigned"
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#endif
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#if GD32_PWM_USE_ADVANCED && !GD32_PWM_USE_TIM0
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#error "advanced mode selected but no advanced timer assigned"
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#endif
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/* Checks on allocation of TIMx units.*/
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#if GD32_PWM_USE_TIM0
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#if defined(GD32_TIM0_IS_USED)
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#error "PWMD1 requires TIM0 but the timer is already used"
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#else
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#define GD32_TIM0_IS_USED
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#endif
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#endif
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#if GD32_PWM_USE_TIM1
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#if defined(GD32_TIM1_IS_USED)
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#error "PWMD2 requires TIM1 but the timer is already used"
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#else
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#define GD32_TIM1_IS_USED
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#endif
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#endif
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#if GD32_PWM_USE_TIM2
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#if defined(GD32_TIM2_IS_USED)
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#error "PWMD3 requires TIM2 but the timer is already used"
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#else
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#define GD32_TIM2_IS_USED
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#endif
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#endif
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#if GD32_PWM_USE_TIM3
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#if defined(GD32_TIM3_IS_USED)
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#error "PWMD4 requires TIM3 but the timer is already used"
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#else
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#define GD32_TIM3_IS_USED
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#endif
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#endif
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#if GD32_PWM_USE_TIM4
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#if defined(GD32_TIM4_IS_USED)
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#error "PWMD5 requires TIM4 but the timer is already used"
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#else
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#define GD32_TIM4_IS_USED
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#endif
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#endif
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/* IRQ priority checks.*/
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#if GD32_PWM_USE_TIM0 && !defined(GD32_TIM0_SUPPRESS_ISR) && \
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!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM0_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM0"
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#endif
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#if GD32_PWM_USE_TIM1 && !defined(GD32_TIM1_SUPPRESS_ISR) && \
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!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM1"
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#endif
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#if GD32_PWM_USE_TIM2 && !defined(GD32_TIM2_SUPPRESS_ISR) && \
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!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM2"
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#endif
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#if GD32_PWM_USE_TIM3 && !defined(GD32_TIM3_SUPPRESS_ISR) && \
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!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM3_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM3"
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#endif
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#if GD32_PWM_USE_TIM4 && !defined(GD32_TIM4_SUPPRESS_ISR) && \
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!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM4_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM4"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type of a PWM mode.
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*/
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typedef uint32_t pwmmode_t;
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/**
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* @brief Type of a PWM channel.
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*/
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typedef uint8_t pwmchannel_t;
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/**
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* @brief Type of a channels mask.
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*/
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typedef uint32_t pwmchnmsk_t;
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/**
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* @brief Type of a PWM counter.
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*/
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typedef uint32_t pwmcnt_t;
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/**
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* @brief Type of a PWM driver channel configuration structure.
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*/
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typedef struct {
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/**
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* @brief Channel active logic level.
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*/
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pwmmode_t mode;
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/**
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* @brief Channel callback pointer.
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* @note This callback is invoked on the channel compare event. If set to
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* @p NULL then the callback is disabled.
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*/
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pwmcallback_t callback;
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/* End of the mandatory fields.*/
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} PWMChannelConfig;
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/**
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* @brief Type of a PWM driver configuration structure.
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*/
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typedef struct {
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/**
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* @brief Timer clock in Hz.
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* @note The low level can use assertions in order to catch invalid
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* frequency specifications.
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*/
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uint32_t frequency;
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/**
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* @brief PWM period in ticks.
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* @note The low level can use assertions in order to catch invalid
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* period specifications.
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*/
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pwmcnt_t period;
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/**
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* @brief Periodic callback pointer.
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* @note This callback is invoked on PWM counter reset. If set to
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* @p NULL then the callback is disabled.
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*/
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pwmcallback_t callback;
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/**
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* @brief Channels configurations.
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*/
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PWMChannelConfig channels[PWM_CHANNELS];
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/* End of the mandatory fields.*/
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/**
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* @brief TIM CR2 register initialization data.
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* @note The value of this field should normally be equal to zero.
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*/
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uint32_t ctl1;
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#if GD32_PWM_USE_ADVANCED || defined(__DOXYGEN__)
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/**
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* @brief TIM BDTR (break & dead-time) register initialization data.
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* @note The value of this field should normally be equal to zero.
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*/ \
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uint32_t cchp;
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#endif
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/**
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* @brief TIM DIER register initialization data.
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* @note The value of this field should normally be equal to zero.
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* @note Only the DMA-related bits can be specified in this field.
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*/
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uint32_t dmainten;
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} PWMConfig;
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/**
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* @brief Structure representing a PWM driver.
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*/
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struct PWMDriver {
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/**
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* @brief Driver state.
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*/
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pwmstate_t state;
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/**
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* @brief Current driver configuration data.
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*/
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const PWMConfig *config;
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/**
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* @brief Current PWM period in ticks.
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*/
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pwmcnt_t period;
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/**
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* @brief Mask of the enabled channels.
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*/
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pwmchnmsk_t enabled;
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/**
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* @brief Number of channels in this instance.
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*/
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pwmchannel_t channels;
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#if defined(PWM_DRIVER_EXT_FIELDS)
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PWM_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Timer base clock.
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*/
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uint32_t clock;
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/**
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* @brief Pointer to the TIMx registers block.
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*/
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gd32_tim_t *tim;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Changes the period the PWM peripheral.
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* @details This function changes the period of a PWM unit that has already
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* been activated using @p pwmStart().
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* @pre The PWM unit must have been activated using @p pwmStart().
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* @post The PWM unit period is changed to the new value.
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* @note The function has effect at the next cycle start.
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* @note If a period is specified that is shorter than the pulse width
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* programmed in one of the channels then the behavior is not
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* guaranteed.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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* @param[in] period new cycle time in ticks
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*
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* @notapi
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*/
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#define pwm_lld_change_period(pwmp, period) \
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((pwmp)->tim->CAR = ((period) - 1))
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if GD32_PWM_USE_TIM0 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD1;
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#endif
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#if GD32_PWM_USE_TIM1 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD2;
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#endif
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#if GD32_PWM_USE_TIM2 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD3;
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#endif
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#if GD32_PWM_USE_TIM3 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD4;
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#endif
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#if GD32_PWM_USE_TIM4 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD5;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void pwm_lld_init(void);
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void pwm_lld_start(PWMDriver *pwmp);
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void pwm_lld_stop(PWMDriver *pwmp);
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void pwm_lld_enable_channel(PWMDriver *pwmp,
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pwmchannel_t channel,
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pwmcnt_t width);
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void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
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void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
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void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
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void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
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pwmchannel_t channel);
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void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
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pwmchannel_t channel);
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void pwm_lld_serve_interrupt(PWMDriver *pwmp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_PWM */
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#endif /* HAL_PWM_LLD_H */
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/** @} */
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