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Fix t0 restore when exiting interrupt 

An oversight when arrangeing the code according to the nucleisys docs,
t0 was overriden with the value of msubm and never actually restored. To
fix the issue we restore the csrs after the general purpose registers.
The offical docs want it the other way around but this should be fine as
well, as the interrupts are still globaly disabled at this point.
This commit is contained in:
Stefan Kerkmann 2021-04-25 13:23:33 +02:00
parent d53c82a884
commit 0a66a0660b
1 changed files with 7 additions and 7 deletions
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14
os/common/ports/RISCV-ECLIC/compilers/GCC/chcoreasm.S
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@ -103,6 +103,13 @@
# registers and status csr registers from stack.
# --------------------------------------------------------------------------
.macro RESTORE_CONTEXT
LOAD t0, 17*REGBYTES(sp)
csrw CSR_MEPC, t0
LOAD t0, 18*REGBYTES(sp)
csrw CSR_MCAUSE, t0
LOAD t0, 19*REGBYTES(sp)
csrw CSR_MSUBM, t0
LOAD ra, 0*REGBYTES(sp)
LOAD tp, 1*REGBYTES(sp)
LOAD t0, 2*REGBYTES(sp)
@ -121,13 +128,6 @@
LOAD t5, 15*REGBYTES(sp)
LOAD t6, 16*REGBYTES(sp)
LOAD t0, 17*REGBYTES(sp)
csrw CSR_MEPC, t0
LOAD t0, 18*REGBYTES(sp)
csrw CSR_MCAUSE, t0
LOAD t0, 19*REGBYTES(sp)
csrw CSR_MSUBM, t0
# De-allocate the stack space
addi sp, sp, 20*REGBYTES
.endm