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USB Host refactor

This commit is contained in:
Fabien Poussin 2021-02-13 20:00:07 +01:00
parent 0a0aa7491d
commit 12faf211a3
No known key found for this signature in database
GPG Key ID: 6166CABA99FC385C
28 changed files with 196 additions and 174 deletions
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4
demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h
View File

@ -90,12 +90,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject
View File

@ -90,12 +90,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

241
os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
View File

@ -21,7 +21,7 @@
#include "usbh/internal.h"
#include <string.h>
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
#if !defined(STM32_OTG_FS_CHANNELS_NUMBER)
#error "STM32_OTG_FS_CHANNELS_NUMBER must be defined"
#endif
@ -38,14 +38,20 @@
#define STM32_OTG_FS_FIFO_MEM_SIZE 320
#endif
#if defined(STM32H7XX)
#define STM32_OTG_FS_NUMBER STM32_OTG2_NUMBER
#define STM32_USB_OTG_FS_IRQ_PRIORITY STM32_USB_OTG2_IRQ_PRIORITY
#define rccEnableOTG_FS(x) rccEnableUSB2_OTG_FS(lp)
#define rccDisableOTG_FS() rccDisableUSB2_OTG_FS()
#define rccResetOTG_FS() rccResetUSB2_OTG_FS()
#define rccEnableOTG1(lp) rccEnableUSB1_OTG_HS(lp)
#define rccDisableOTG1() rccDisableUSB1_OTG_HS()
#define rccResetOTG1() rccResetUSB1_OTG_HS()
#define rccEnableOTG1_HSULPI(lp) rccEnableUSB1_HSULPI(lp)
#define rccDisableOTG1_HSULPI() rccDisableUSB1_HSULPI()
#define rccResetOTG1_HSULPI() rccResetUSB1_HSULPI()
#define OTG1 OTG_HS
#define OTG1_CHANNELS_NUMBER STM32_OTG_HS_CHANNELS_NUMBER
#else
#define STM32_OTG_FS_NUMBER STM32_OTG1_NUMBER
#define STM32_USB_OTG_FS_IRQ_PRIORITY STM32_USB_OTG1_IRQ_PRIORITY
#define rccEnableOTG1(lp) rccEnableUSB1_OTG_FS(lp)
#define rccDisableOTG1() rccDisableUSB1_OTG_FS()
#define rccResetOTG1() rccResetUSB1_OTG_FS()
#define OTG1 OTG_FS
#define OTG1_CHANNELS_NUMBER STM32_OTG_FS_CHANNELS_NUMBER
#endif
#if (STM32_OTG_FS_RXFIFO_SIZE + STM32_OTG_FS_PTXFIFO_SIZE + STM32_OTG_FS_NPTXFIFO_SIZE) > (STM32_OTG_FS_FIFO_MEM_SIZE * 4)
#error "Not enough memory in OTG_FS implementation"
@ -57,7 +63,7 @@
#endif
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
#if !defined(STM32_OTG_HS_CHANNELS_NUMBER)
#error "STM32_OTG_HS_CHANNELS_NUMBER must be defined"
#endif
@ -73,24 +79,24 @@
#if !defined(STM32_OTG_HS_FIFO_MEM_SIZE)
#define STM32_OTG_HS_FIFO_MEM_SIZE 1024
#endif
#if !defined(STM32_USBH_USE_OTG_HS_ULPI)
#define STM32_USBH_USE_OTG_HS_ULPI FALSE
#if !defined(STM32_OTG2_USE_ULPI)
#define STM32_OTG2_USE_ULPI FALSE
#endif
#if defined(STM32H7XX)
#define STM32_OTG_HS_NUMBER STM32_OTG1_NUMBER
#define STM32_USB_OTG_HS_IRQ_PRIORITY STM32_USB_OTG1_IRQ_PRIORITY
#define rccEnableOTG_HS(x) rccEnableUSB1_OTG_HS(x)
#define rccDisableOTG_HS() rccDisableUSB1_OTG_HS()
#define rccResetOTG_HS() rccResetUSB1_OTG_HS()
#define rccEnableOTG_HSULPI(x) rccEnableUSB1_HSULPI(x)
#define rccDisableOTG_HSULPI() rccDisableUSB1_HSULPI()
#define rccResetOTG_HSULPI() rccResetUSB1_HSULPI()
#else
#define STM32_OTG_HS_NUMBER STM32_OTG2_NUMBER
#define STM32_USB_OTG_HS_IRQ_PRIORITY STM32_USB_OTG2_IRQ_PRIORITY
#define rccEnableOTG_HSULPI(x) rccEnableUSB2_HSULPI(x)
#define rccDisableOTG_HSULPI() rccDisableUSB2_HSULPI()
#define rccResetOTG_HSULPI() rccResetUSB2_HSULPI()
#define rccEnableOTG2(lp) rccEnableUSB2_OTG_FS(lp)
#define rccDisableOTG2() rccDisableUSB2_OTG_FS()
#define rccResetOTG2() rccResetUSB2_OTG_FS()
#define OTG2 OTG_FS
#define OTG2_CHANNELS_NUMBER STM32_OTG_FS_CHANNELS_NUMBER
#else
#define rccEnableOTG2(lp) rccEnableUSB2_OTG_HS(lp)
#define rccDisableOTG2() rccDisableUSB2_OTG_HS()
#define rccResetOTG2() rccResetUSB2_OTG_HS()
#define rccEnableOTG2_HSULPI(x) rccEnableUSB2_HSULPI(x)
#define rccDisableOTG2_HSULPI() rccDisableUSB2_HSULPI()
#define rccResetOTG2_HSULPI() rccResetUSB2_HSULPI()
#define OTG2 OTG_HS
#define OTG2_CHANNELS_NUMBER STM32_OTG_HS_CHANNELS_NUMBER
#endif
#if (STM32_OTG_HS_RXFIFO_SIZE + STM32_OTG_HS_PTXFIFO_SIZE + STM32_OTG_HS_NPTXFIFO_SIZE) > (STM32_OTG_HS_FIFO_MEM_SIZE * 4)
#error "Not enough memory in OTG_HS implementation"
@ -102,6 +108,9 @@
#endif
#endif
#define TRDT_VALUE_FS 5
#define TRDT_VALUE_HS 9
#define _USBH_DEBUG_HELPER_ENABLE_TRACE USBH_LLD_DEBUG_ENABLE_TRACE
#define _USBH_DEBUG_HELPER_ENABLE_INFO USBH_LLD_DEBUG_ENABLE_INFO
#define _USBH_DEBUG_HELPER_ENABLE_WARNINGS USBH_LLD_DEBUG_ENABLE_WARNINGS
@ -113,10 +122,10 @@ static void _try_commit_np(USBHDriver *host);
static void otg_rxfifo_flush(USBHDriver *usbp);
static void otg_txfifo_flush(USBHDriver *usbp, uint32_t fifo);
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
USBHDriver USBHD1;
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
USBHDriver USBHD2;
#endif
@ -1247,8 +1256,8 @@ static inline void _hprtint_int(USBHDriver *host) {
/* configure FIFOs */
#define HNPTXFSIZ DIEPTXF0
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG1
#if STM32_USBH_USE_OTG2
if (&USBHD1 == host)
#endif
{
@ -1257,8 +1266,8 @@ static inline void _hprtint_int(USBHDriver *host) {
otg->HPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG_FS_RXFIFO_SIZE / 4) + (STM32_OTG_FS_NPTXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG_FS_PTXFIFO_SIZE / 4);
}
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG2
#if STM32_USBH_USE_OTG1
if (&USBHD2 == host)
#endif
{
@ -1385,7 +1394,7 @@ static void usb_lld_serve_interrupt(USBHDriver *host) {
/* Interrupt handlers. */
/*===========================================================================*/
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
OSAL_IRQ_HANDLER(STM32_OTG_FS_HANDLER) {
OSAL_IRQ_PROLOGUE();
osalSysLockFromISR();
@ -1395,7 +1404,7 @@ OSAL_IRQ_HANDLER(STM32_OTG_FS_HANDLER) {
}
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
OSAL_IRQ_HANDLER(STM32_OTG_HS_HANDLER) {
OSAL_IRQ_PROLOGUE();
osalSysLockFromISR();
@ -1409,33 +1418,27 @@ OSAL_IRQ_HANDLER(STM32_OTG_HS_HANDLER) {
/*===========================================================================*/
/* Initialization functions. */
/*===========================================================================*/
static void otg_core_reset(USBHDriver *usbp) {
stm32_otg_t *const otgp = usbp->otg;
static void otg_core_reset(stm32_otg_t *const otgp) {
/* Wait AHB idle condition.*/
while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)
;
osalSysPolledDelayX(64);
while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) osalSysPolledDelayX(1);
/* Core reset and delay of at least 3 PHY cycles.*/
otgp->GRSTCTL = GRSTCTL_CSRST;
while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
;
osalSysPolledDelayX(12);
while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) osalSysPolledDelayX(1);
osalSysPolledDelayX(24);
osalSysPolledDelayX(18);
/* Wait AHB idle condition.*/
while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)
;
/* Wait AHB idle condition again.*/
while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) osalSysPolledDelayX(1);
}
static void otg_rxfifo_flush(USBHDriver *usbp) {
stm32_otg_t *const otgp = usbp->otg;
otgp->GRSTCTL = GRSTCTL_RXFFLSH;
while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0)
;
while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0) osalSysPolledDelayX(1);
/* Wait for 3 PHY Clocks.*/
osalSysPolledDelayX(24);
}
@ -1444,8 +1447,7 @@ static void otg_txfifo_flush(USBHDriver *usbp, uint32_t fifo) {
stm32_otg_t *const otgp = usbp->otg;
otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH;
while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0)
;
while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0) osalSysPolledDelayX(1);
/* Wait for 3 PHY Clocks.*/
osalSysPolledDelayX(24);
}
@ -1455,23 +1457,23 @@ static void _init(USBHDriver *host) {
usbhObjectInit(host);
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG1
#if STM32_USBH_USE_OTG2
if (&USBHD1 == host)
#endif
{
host->otg = OTG_FS;
host->channels_number = STM32_OTG_FS_CHANNELS_NUMBER;
host->otg = OTG1;
host->channels_number = OTG1_CHANNELS_NUMBER;
}
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG2
#if STM32_USBH_USE_OTG1
if (&USBHD2 == host)
#endif
{
host->otg = OTG_HS;
host->channels_number = STM32_OTG_HS_CHANNELS_NUMBER;
host->otg = OTG2;
host->channels_number = OTG2_CHANNELS_NUMBER;
}
#endif
INIT_LIST_HEAD(&host->ch_free[0]);
@ -1493,10 +1495,10 @@ static void _init(USBHDriver *host) {
}
void usbh_lld_init(void) {
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
_init(&USBHD1);
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
_init(&USBHD2);
#endif
}
@ -1505,59 +1507,81 @@ void usbh_lld_start(USBHDriver *host) {
stm32_otg_t *const otgp = host->otg;
/* Clock activation.*/
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG1
if (&USBHD1 == host)
#endif
{
#if STM32_OTG1_USE_ULPI
rccEnableOTG1_HSULPI(FALSE);
#endif
/* OTG FS clock enable and reset.*/
rccEnableOTG_FS(FALSE);
rccResetOTG_FS();
rccEnableOTG1(FALSE);
rccResetOTG1();
otgp->GINTMSK = 0;
/* Enables IRQ vector.*/
nvicEnableVector(STM32_OTG_FS_NUMBER, STM32_USB_OTG_FS_IRQ_PRIORITY);
}
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG_FS
if (&USBHD2 == host)
#endif
{
/* OTG HS clock enable and reset.*/
rccEnableOTG_HS(FALSE); // Disable HS clock when cpu is in sleep mode
#if STM32_USBH_USE_OTG_HS_ULPI
rccEnableOTG_HSULPI(FALSE);
#endif
rccResetOTG_HS();
otgp->GINTMSK = 0;
/* Enables IRQ vector.*/
nvicEnableVector(STM32_OTG_HS_NUMBER, STM32_USB_OTG_HS_IRQ_PRIORITY);
}
#endif
#if STM32_USBH_USE_OTG_HS_ULPI
/* Select vbus source */
otgp->GUSBCFG = USB_OTG_GUSBCFG_ULPIAR | USB_OTG_GUSBCFG_ULPIEVBUSD;
#if STM32_OTG1_USE_HS
otgp->GUSBCFG = GUSBCFG_TRDT(TRDT_VALUE_HS);
#else
otgp->GUSBCFG = GUSBCFG_PHYSEL;
otgp->GUSBCFG = GUSBCFG_TRDT(TRDT_VALUE_FS);
#endif
#if STM32_OTG1_USE_ULPI
otgp->GUSBCFG |= GUSBCFG_SRPCAP | GUSBCFG_HNPCAP;
#if STM32_OTG1_USE_ULPI_VBUS
otgp->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI;
#endif
#else
otgp->GUSBCFG |= GUSBCFG_PHYSEL;
#endif
otgp->GINTMSK = 0;
/* Enables IRQ vector.*/
nvicEnableVector(STM32_OTG1_NUMBER, STM32_USB_OTG1_IRQ_PRIORITY);
}
#endif
#if STM32_USBH_USE_OTG2
if (&USBHD2 == host)
{
#if STM32_OTG2_USE_ULPI
rccEnableOTG2_HSULPI(FALSE);
#endif
/* OTG HS clock enable and reset.*/
rccEnableOTG2(FALSE); // Disable HS clock when cpu is in sleep mode
rccResetOTG2();
#if STM32_OTG2_USE_HS
otgp->GUSBCFG = GUSBCFG_TRDT(TRDT_VALUE_HS);
#else
otgp->GUSBCFG = GUSBCFG_TRDT(TRDT_VALUE_FS);
#endif
#if STM32_OTG2_USE_ULPI
otgp->GUSBCFG |= GUSBCFG_SRPCAP | GUSBCFG_HNPCAP;
#if STM32_OTG2_USE_ULPI_VBUS
otgp->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI;
#endif
#else
otgp->GUSBCFG |= GUSBCFG_PHYSEL;
#endif
otgp->GINTMSK = 0;
/* Enables IRQ vector.*/
nvicEnableVector(STM32_OTG2_NUMBER, STM32_USB_OTG2_IRQ_PRIORITY);
}
#endif
/* Reset after a PHY change */
otg_core_reset(host);
otg_core_reset(otgp);
otgp->GCCFG = GCCFG_PWRDWN;
/* Forced host mode. */
otgp->GUSBCFG |= GUSBCFG_FHMOD | GUSBCFG_TRDT(5);
otgp->GUSBCFG |= GUSBCFG_FHMOD;
/* PHY enabled.*/
otgp->PCGCCTL = 0;
#if !STM32_USBH_USE_OTG_HS_ULPI
#if !STM32_OTG1_USE_ULPI && !STM32_OTG2_USE_ULPI
/* Internal FS PHY activation.*/
#if STM32_OTG_STEPPING == 1
#if defined(BOARD_OTG_NOVBUSSENS)
@ -1607,31 +1631,30 @@ void usbh_lld_stop(USBHDriver *host) {
otgp->GCCFG = GCCFG_PWRDWN;
/* Clock activation.*/
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG1
if (&USBHD1 == host)
#endif
{
/* Disable IRQ vector.*/
nvicDisableVector(STM32_OTG_FS_NUMBER);
nvicDisableVector(STM32_OTG1_NUMBER);
/* OTG FS clock disable.*/
rccDisableOTG_FS();
rccDisableOTG1();
#if defined(STM32H7XX) && STM32_OTG1_USE_ULPI
rccDisableOTG1_HSULPI();
#endif
}
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG2
if (&USBHD2 == host)
#endif
{
/* Enables IRQ vector.*/
nvicDisableVector(STM32_OTG_HS_NUMBER);
nvicDisableVector(STM32_OTG2_NUMBER);
/* OTG HS clock disable.*/
rccDisableOTG_HS(); // Disable HS clock when cpu is in sleep mode
#if STM32_USBH_USE_OTG_HS_ULPI
rccDisableOTG_HSULPI();
rccDisableOTG2(); // Disable HS clock when cpu is in sleep mode
#if ! defined(STM32H7XX) && STM32_OTG2_USE_ULPI
rccDisableOTG2_HSULPI();
#endif
}
#endif

5
os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h
View File

@ -153,12 +153,11 @@ uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh);
#define USBH_LLD_DECLARE_STRUCT_MEMBER(member) member __attribute__((aligned(4)))
#endif
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
extern USBHDriver USBHD1;
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
extern USBHDriver USBHD2;
#endif

4
testhal/STM32/STM32F0xx/COMP/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F0xx/crc/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F0xx/onewire/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F0xx/qei/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F1xx/onewire/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F1xx/qei/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F3xx/COMP/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h
View File

@ -102,12 +102,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h
View File

@ -91,12 +91,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F4xx/EICU/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h
View File

@ -90,12 +90,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h
View File

@ -93,12 +93,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h
View File

@ -93,12 +93,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

12
testhal/STM32/STM32F4xx/USB_HOST/main.c
View File

@ -911,12 +911,12 @@ int main(void) {
palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7));
palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7));
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
//VBUS - configured in board.h
//USB_FS - configured in board.h
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
#error "TODO: Initialize USB_HS pads"
#endif
@ -945,20 +945,20 @@ int main(void) {
chThdSleepMilliseconds(100);
//start
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
usbhStart(&USBHD1);
_usbh_dbgf(&USBHD1, "Started");
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
usbhStart(&USBHD2);
_usbh_dbgf(&USBHD2, "Started");
#endif
for(;;) {
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
usbhMainLoop(&USBHD1);
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
usbhMainLoop(&USBHD2);
#endif
chThdSleepMilliseconds(100);

6
testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h
View File

@ -92,13 +92,13 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS TRUE
#define STM32_USBH_USE_OTG1 TRUE
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS FALSE
#define STM32_USBH_USE_OTG_HS_ULPI TRUE
#define STM32_USBH_USE_OTG2 FALSE
#define STM32_OTG2_USE_ULPI TRUE
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F4xx/USB_MSD/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F4xx/onewire/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

12
testhal/STM32/STM32H7xx/USB_HOST/main.c
View File

@ -911,12 +911,12 @@ int main(void) {
palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7));
palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7));
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
//VBUS - configured in board.h
//USB_FS - configured in board.h
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
//USB_HS - configured in board.h
#endif
@ -945,20 +945,20 @@ int main(void) {
// chThdSleepMilliseconds(100);
//start
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
usbhStart(&USBHD1);
_usbh_dbgf(&USBHD1, "Started");
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
usbhStart(&USBHD2);
_usbh_dbgf(&USBHD2, "Started");
#endif
for(;;) {
#if STM32_USBH_USE_OTG_FS
#if STM32_USBH_USE_OTG1
usbhMainLoop(&USBHD1);
#endif
#if STM32_USBH_USE_OTG_HS
#if STM32_USBH_USE_OTG2
usbhMainLoop(&USBHD2);
#endif
chThdSleepMilliseconds(100);

6
testhal/STM32/STM32H7xx/USB_HOST/mcuconf_community.h
View File

@ -92,13 +92,13 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS FALSE
#define STM32_USBH_USE_OTG1 FALSE
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS TRUE
#define STM32_USBH_USE_OTG_HS_ULPI TRUE
#define STM32_USBH_USE_OTG2 TRUE
#define STM32_OTG2_USE_ULPI TRUE
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32H7xx/USB_MSD/mcuconf_community.h
View File

@ -92,12 +92,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
testhal/STM32/STM32L0xx/COMP/mcuconf_community.h
View File

@ -90,12 +90,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024

4
tools/templates/mcuconf_community.h
View File

@ -102,12 +102,12 @@
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG_FS 1
#define STM32_USBH_USE_OTG1 1
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG_HS 0
#define STM32_USBH_USE_OTG2 0
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024