NAND. Cosmetical improvement
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04c11df0b2
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@ -291,10 +291,12 @@ void nand_lld_start(NANDDriver *nandp) {
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(void *)nandp);
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(void *)nandp);
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osalDbgAssert(!b, "stream already allocated");
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osalDbgAssert(!b, "stream already allocated");
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nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) |
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nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) |
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STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
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STM32_DMA_CR_PSIZE_BYTE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_MSIZE_BYTE |
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STM32_DMA_CR_TCIE;
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE |
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STM32_DMA_CR_TCIE;
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/* dmaStreamSetFIFO(nandp->dma,
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/* dmaStreamSetFIFO(nandp->dma,
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STM32_DMA_FCR_DMDIS | NAND_STM32_DMA_FCR_FTH_LVL); */
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STM32_DMA_FCR_DMDIS | NAND_STM32_DMA_FCR_FTH_LVL); */
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nandp->nand->PCR = calc_eccps(nandp) | FSMC_PCR_PTYP | FSMC_PCR_PBKEN;
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nandp->nand->PCR = calc_eccps(nandp) | FSMC_PCR_PTYP | FSMC_PCR_PBKEN;
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@ -392,7 +394,7 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
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nand_lld_write_addr(nandp, addr, addrlen);
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nand_lld_write_addr(nandp, addr, addrlen);
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/* Now start DMA transfer to NAND buffer and put thread in sleep state.
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/* Now start DMA transfer to NAND buffer and put thread in sleep state.
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Tread will we woken up from ready ISR. */
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Tread will be woken up from ready ISR. */
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nandp->state = NAND_DMA_TX;
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nandp->state = NAND_DMA_TX;
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osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0,
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osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0,
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"State machine broken. ECCEN must be previously disabled.");
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"State machine broken. ECCEN must be previously disabled.");
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