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Correct DMA channel macros to start from 0

This commit is contained in:
Stefan Kerkmann 2021-03-25 17:53:42 +01:00
parent 7178909bb1
commit 1aa20a7fa6
2 changed files with 21 additions and 21 deletions
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2
os/hal/ports/GD/GD32VF103/DMA/gd32_dma.h
View File

@ -85,7 +85,7 @@
* @return An unique numeric stream identifier.
*/
#define GD32_DMA_STREAM_ID(dma, stream) \
((((dma) - 1) * GD32_DMA0_NUM_CHANNELS) + ((stream) - 1))
((((dma)) * GD32_DMA0_NUM_CHANNELS) + ((stream)))
/**
* @brief Returns a DMA stream identifier mask.

40
os/hal/ports/GD/GD32VF103/gd32_registry.h
View File

@ -108,10 +108,10 @@
/* DAC attributes.*/
#define GD32_HAS_DAC1_CH1 TRUE
#define GD32_DAC_DAC1_CH1_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_DAC_DAC1_CH1_DMA_STREAM GD32_DMA_STREAM_ID(0, 2)
#define GD32_HAS_DAC1_CH2 TRUE
#define GD32_DAC_DAC1_CH2_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_DAC_DAC1_CH2_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
/* DMA attributes.*/
#define GD32_ADVANCED_DMA FALSE
@ -183,16 +183,16 @@
/* I2C attributes.*/
#if GD32_HAS_I2C_0 || GD32_HAS_I2C_01
#define GD32_HAS_I2C1 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5)
#else
#define GD32_HAS_I2C1 FALSE
#endif
#if GD32_HAS_I2C_01
#define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#else
#define GD32_HAS_I2C2 FALSE
#endif
@ -206,8 +206,8 @@
#if GD32_HAS_SPI_0 || GD32_HAS_SPI_012
#define GD32_HAS_SPI1 TRUE
#define GD32_SPI1_SUPPORTS_I2S FALSE
#define GD32_SPI_SPI1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_SPI_SPI1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_SPI_SPI1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 1)
#define GD32_SPI_SPI1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 2)
#else
#define GD32_HAS_SPI1 FALSE
#endif
@ -216,14 +216,14 @@
#define GD32_HAS_SPI2 TRUE
#define GD32_SPI2_SUPPORTS_I2S TRUE
#define GD32_SPI2_I2S_FULLDUPLEX FALSE
#define GD32_SPI_SPI2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_SPI_SPI2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_SPI_SPI2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#define GD32_SPI_SPI2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_HAS_SPI3 TRUE
#define GD32_SPI3_SUPPORTS_I2S TRUE
#define GD32_SPI3_I2S_FULLDUPLEX FALSE
#define GD32_SPI_SPI3_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 1)
#define GD32_SPI_SPI3_TX_DMA_STREAM GD32_DMA_STREAM_ID(2, 2)
#define GD32_SPI_SPI3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 0)
#define GD32_SPI_SPI3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 1)
#else
#define GD32_HAS_SPI2 FALSE
#define GD32_HAS_SPI3 FALSE
@ -273,12 +273,12 @@
/* USART attributes.*/
#if GD32_HAS_USART_01 || GD32_HAS_USART_012 || GD32_HAS_USART_01234
#define GD32_HAS_USART1 TRUE
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#define GD32_HAS_USART2 TRUE
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6)
#else
#define GD32_HAS_USART1 FALSE
#define GD32_HAS_USART2 FALSE
@ -286,16 +286,16 @@
#if GD32_HAS_USART_012 || GD32_HAS_USART_01234
#define GD32_HAS_USART3 TRUE
#define GD32_UART_USART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_UART_USART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 2)
#define GD32_UART_USART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 1)
#else
#define GD32_HAS_USART3 FALSE
#endif
#if GD32_HAS_USART_01234
#define GD32_HAS_UART4 TRUE
#define GD32_UART_UART4_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 3)
#define GD32_UART_UART4_TX_DMA_STREAM GD32_DMA_STREAM_ID(2, 5)
#define GD32_UART_UART4_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_UART_UART4_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_UART5 TRUE
#else
#define GD32_HAS_UART4 FALSE