Add renumbered dma channel definitions
This commit is contained in:
Stefan Kerkmann
parent
92646d6824
commit
1d3f664311
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@ -126,18 +126,18 @@
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* instead: @p GD32_DMA0_STREAM0, @p GD32_DMA0_STREAM1 etc.
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*/
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const gd32_dma_stream_t _gd32_dma_streams[GD32_DMA_STREAMS] = {
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{DMA0, DMA0_Channel1, GD32_DMA0_CH0_CMASK, DMA0_CH0_VARIANT, 0, 0, GD32_DMA0_CH0_NUMBER},
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{DMA0, DMA0_Channel2, GD32_DMA0_CH1_CMASK, DMA0_CH1_VARIANT, 4, 1, GD32_DMA0_CH1_NUMBER},
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{DMA0, DMA0_Channel3, GD32_DMA0_CH2_CMASK, DMA0_CH2_VARIANT, 8, 2, GD32_DMA0_CH2_NUMBER},
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{DMA0, DMA0_Channel4, GD32_DMA0_CH3_CMASK, DMA0_CH3_VARIANT, 12, 3, GD32_DMA0_CH3_NUMBER},
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{DMA0, DMA0_Channel5, GD32_DMA0_CH4_CMASK, DMA0_CH4_VARIANT, 16, 4, GD32_DMA0_CH4_NUMBER},
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{DMA0, DMA0_Channel6, GD32_DMA0_CH5_CMASK, DMA0_CH5_VARIANT, 20, 5, GD32_DMA0_CH5_NUMBER},
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{DMA0, DMA0_Channel7, GD32_DMA0_CH6_CMASK, DMA0_CH6_VARIANT, 24, 6, GD32_DMA0_CH6_NUMBER},
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{DMA1, DMA1_Channel1, GD32_DMA1_CH0_CMASK, DMA1_CH0_VARIANT, 0, 0 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH0_NUMBER},
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{DMA1, DMA1_Channel2, GD32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 4, 1 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH1_NUMBER},
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{DMA1, DMA1_Channel3, GD32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 8, 2 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH2_NUMBER},
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{DMA1, DMA1_Channel4, GD32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 12, 3 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH3_NUMBER},
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{DMA1, DMA1_Channel5, GD32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 16, 4 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH4_NUMBER},
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{DMA0, DMA0_Channel0, GD32_DMA0_CH0_CMASK, DMA0_CH0_VARIANT, 0, 0, GD32_DMA0_CH0_NUMBER},
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{DMA0, DMA0_Channel1, GD32_DMA0_CH1_CMASK, DMA0_CH1_VARIANT, 4, 1, GD32_DMA0_CH1_NUMBER},
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{DMA0, DMA0_Channel2, GD32_DMA0_CH2_CMASK, DMA0_CH2_VARIANT, 8, 2, GD32_DMA0_CH2_NUMBER},
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{DMA0, DMA0_Channel3, GD32_DMA0_CH3_CMASK, DMA0_CH3_VARIANT, 12, 3, GD32_DMA0_CH3_NUMBER},
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{DMA0, DMA0_Channel4, GD32_DMA0_CH4_CMASK, DMA0_CH4_VARIANT, 16, 4, GD32_DMA0_CH4_NUMBER},
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{DMA0, DMA0_Channel5, GD32_DMA0_CH5_CMASK, DMA0_CH5_VARIANT, 20, 5, GD32_DMA0_CH5_NUMBER},
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{DMA0, DMA0_Channel6, GD32_DMA0_CH6_CMASK, DMA0_CH6_VARIANT, 24, 6, GD32_DMA0_CH6_NUMBER},
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{DMA1, DMA1_Channel0, GD32_DMA1_CH0_CMASK, DMA1_CH0_VARIANT, 0, 0 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH0_NUMBER},
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{DMA1, DMA1_Channel1, GD32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 4, 1 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH1_NUMBER},
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{DMA1, DMA1_Channel2, GD32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 8, 2 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH2_NUMBER},
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{DMA1, DMA1_Channel3, GD32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 12, 3 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH3_NUMBER},
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{DMA1, DMA1_Channel4, GD32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 16, 4 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH4_NUMBER},
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};
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/*===========================================================================*/
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@ -735,19 +735,19 @@ typedef struct
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#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
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#define DMA0_BASE (AHBPERIPH_BASE + 0x00000000U)
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#define DMA0_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
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#define DMA0_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
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#define DMA0_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
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#define DMA0_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
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#define DMA0_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
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#define DMA0_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
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#define DMA0_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
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#define DMA0_Channel0_BASE (AHBPERIPH_BASE + 0x00000008U)
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#define DMA0_Channel1_BASE (AHBPERIPH_BASE + 0x0000001CU)
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#define DMA0_Channel2_BASE (AHBPERIPH_BASE + 0x00000030U)
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#define DMA0_Channel3_BASE (AHBPERIPH_BASE + 0x00000044U)
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#define DMA0_Channel4_BASE (AHBPERIPH_BASE + 0x00000058U)
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#define DMA0_Channel5_BASE (AHBPERIPH_BASE + 0x0000006CU)
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#define DMA0_Channel6_BASE (AHBPERIPH_BASE + 0x00000080U)
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#define DMA1_BASE (AHBPERIPH_BASE + 0x00000400U)
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#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)
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#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)
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#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)
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#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)
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#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)
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#define DMA1_Channel0_BASE (AHBPERIPH_BASE + 0x00000408U)
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#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0000041CU)
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#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x00000430U)
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#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000444U)
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#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000458U)
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#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
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//#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
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@ -824,18 +824,18 @@ typedef struct
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#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
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#define DMA0 ((DMA_TypeDef *)DMA0_BASE)
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#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
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#define DMA0_Channel0 ((DMA_Channel_TypeDef *)DMA0_Channel0_BASE)
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#define DMA0_Channel1 ((DMA_Channel_TypeDef *)DMA0_Channel1_BASE)
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#define DMA0_Channel2 ((DMA_Channel_TypeDef *)DMA0_Channel2_BASE)
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#define DMA0_Channel3 ((DMA_Channel_TypeDef *)DMA0_Channel3_BASE)
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#define DMA0_Channel4 ((DMA_Channel_TypeDef *)DMA0_Channel4_BASE)
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#define DMA0_Channel5 ((DMA_Channel_TypeDef *)DMA0_Channel5_BASE)
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#define DMA0_Channel6 ((DMA_Channel_TypeDef *)DMA0_Channel6_BASE)
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#define DMA0_Channel7 ((DMA_Channel_TypeDef *)DMA0_Channel7_BASE)
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#define DMA1_Channel0 ((DMA_Channel_TypeDef *)DMA1_Channel0_BASE)
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#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
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#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
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#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
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#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
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#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
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#define RCC ((RCC_TypeDef *)RCC_BASE)
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#define CRC ((CRC_TypeDef *)CRC_BASE)
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#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
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@ -14268,18 +14268,18 @@ typedef struct
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#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
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/****************************** DMA Instances *********************************/
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#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA0_Channel1) || \
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#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA0_Channel0) || \
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((INSTANCE) == DMA0_Channel1) || \
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((INSTANCE) == DMA0_Channel2) || \
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((INSTANCE) == DMA0_Channel3) || \
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((INSTANCE) == DMA0_Channel4) || \
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((INSTANCE) == DMA0_Channel5) || \
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((INSTANCE) == DMA0_Channel6) || \
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((INSTANCE) == DMA0_Channel7) || \
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((INSTANCE) == DMA1_Channel0) || \
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((INSTANCE) == DMA1_Channel1) || \
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((INSTANCE) == DMA1_Channel2) || \
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((INSTANCE) == DMA1_Channel3) || \
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((INSTANCE) == DMA1_Channel4) || \
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((INSTANCE) == DMA1_Channel5))
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((INSTANCE) == DMA1_Channel4))
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/******************************* GPIO Instances *******************************/
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#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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@ -14608,7 +14608,7 @@ typedef struct
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#define USB_LP_IRQn CAN1_RX0_IRQn
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#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
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#define USB_HP_IRQn CAN1_TX_IRQn
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#define DMA1_Channel4_5_IRQn DMA1_Channel4_IRQn
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#define DMA1_Channel3_5_IRQn DMA1_Channel3_IRQn
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#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
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#define CEC_IRQn OTG_FS_WKUP_IRQn
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#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
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@ -14629,7 +14629,7 @@ typedef struct
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#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
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#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
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#define USB_HP_IRQHandler CAN1_TX_IRQHandler
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#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_IRQHandler
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#define DMA1_Channel3_5_IRQHandler DMA1_Channel3_IRQHandler
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#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
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#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
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#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
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