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Replace GD32_DAC_DAC with GD32_DAC

This commit is contained in:
Stefan Kerkmann 2021-04-05 17:32:32 +02:00
parent c7e847a17a
commit 2cd74f3ea2
3 changed files with 22 additions and 22 deletions
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16
os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c
View File

@ -31,11 +31,11 @@
/*===========================================================================*/
#define DAC_CH1_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_DAC_DAC_CH1_DMA_STREAM, \
GD32_DMA_GETCHANNEL(GD32_DAC_CH1_DMA_STREAM, \
GD32_DAC_CH1_DMA_CHN)
#define DAC_CH2_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_DAC_DAC_CH2_DMA_STREAM, \
GD32_DMA_GETCHANNEL(GD32_DAC_CH2_DMA_STREAM, \
GD32_DAC_CH2_DMA_CHN)
#define CHANNEL_DATA_OFFSET 3U
@ -64,13 +64,13 @@ static const dacparams_t dac1_ch1_params = {
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
.dmastream = GD32_DAC_DAC_CH1_DMA_STREAM,
.dmastream = GD32_DAC_CH1_DMA_STREAM,
.dmamode = GD32_DMA_CTL_CHSEL(DAC_CH1_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_DAC_DAC_CH1_DMA_PRIORITY) |
GD32_DMA_CTL_PRIO(GD32_DAC_CH1_DMA_PRIORITY) |
GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P |
GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_HTFIE |
GD32_DMA_CTL_FTFIE,
.dmairqprio = GD32_DAC_DAC_CH1_IRQ_PRIORITY
.dmairqprio = GD32_DAC_CH1_IRQ_PRIORITY
};
#endif
@ -80,13 +80,13 @@ static const dacparams_t dac1_ch2_params = {
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
.dmastream = GD32_DAC_DAC_CH2_DMA_STREAM,
.dmastream = GD32_DAC_CH2_DMA_STREAM,
.dmamode = GD32_DMA_CTL_CHSEL(DAC_CH2_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_DAC_DAC_CH2_DMA_PRIORITY) |
GD32_DMA_CTL_PRIO(GD32_DAC_CH2_DMA_PRIORITY) |
GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P |
GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_HTFIE |
GD32_DMA_CTL_FTFIE,
.dmairqprio = GD32_DAC_DAC_CH2_IRQ_PRIORITY
.dmairqprio = GD32_DAC_CH2_IRQ_PRIORITY
};
#endif

24
os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h
View File

@ -76,29 +76,29 @@
/**
* @brief DAC CH1 interrupt priority level setting.
*/
#if !defined(GD32_DAC_DAC_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC_CH1_IRQ_PRIORITY 10
#if !defined(GD32_DAC_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_CH1_IRQ_PRIORITY 10
#endif
/**
* @brief DAC CH2 interrupt priority level setting.
*/
#if !defined(GD32_DAC_DAC_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC_CH2_IRQ_PRIORITY 10
#if !defined(GD32_DAC_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_CH2_IRQ_PRIORITY 10
#endif
/**
* @brief DAC CH1 DMA priority (0..3|lowest..highest).
*/
#if !defined(GD32_DAC_DAC_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC_CH1_DMA_PRIORITY 2
#if !defined(GD32_DAC_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_CH1_DMA_PRIORITY 2
#endif
/**
* @brief DAC CH2 DMA priority (0..3|lowest..highest).
*/
#if !defined(GD32_DAC_DAC_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC_CH2_DMA_PRIORITY 2
#if !defined(GD32_DAC_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_CH2_DMA_PRIORITY 2
#endif
/** @} */
@ -131,23 +131,23 @@
#endif
#if GD32_DAC_USE_DAC_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC_CH1_IRQ_PRIORITY)
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_CH1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC CH1"
#endif
#if GD32_DAC_USE_DAC_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC_CH2_IRQ_PRIORITY)
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_CH2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC CH2"
#endif
#if GD32_DAC_USE_DAC_CH1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC_CH1_DMA_PRIORITY)
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_CH1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC CH1"
#endif
#if GD32_DAC_USE_DAC_CH2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC_CH2_DMA_PRIORITY)
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_CH2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC CH2"
#endif

4
os/hal/ports/GD/GD32VF103/gd32_registry.h
View File

@ -108,10 +108,10 @@
/* DAC attributes.*/
#define GD32_HAS_DAC_CH1 TRUE
#define GD32_DAC_DAC_CH1_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_DAC_CH1_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_DAC_CH2 TRUE
#define GD32_DAC_DAC_CH2_DMA_STREAM GD32_DMA_STREAM_ID(2, 3)
#define GD32_DAC_CH2_DMA_STREAM GD32_DMA_STREAM_ID(2, 3)
/* DMA attributes.*/
#define GD32_DMA0_NUM_CHANNELS 7