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Remove unused USB OTG Defines

This commit is contained in:
Stefan Kerkmann 2021-04-05 17:51:40 +02:00
parent d25731f7cf
commit 302e61bdcf
1 changed files with 0 additions and 116 deletions
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116
os/hal/ports/GD/GD32VF103/stm32f105xc.h
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@ -497,122 +497,6 @@ typedef struct
__IO uint32_t GP; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;
/**
* @brief __USB_OTG_Core_register
*/
typedef struct
{
__IO uint32_t GOTGCS; /*!< USB_OTG Control and Status Register Address offset: 000h */
__IO uint32_t GOTGINTF; /*!< USB_OTG Interrupt Register Address offset: 004h */
__IO uint32_t GAHBCS; /*!< Core AHB Configuration Register Address offset: 008h */
__IO uint32_t GUSBCS; /*!< Core USB Configuration Register Address offset: 00Ch */
__IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */
__IO uint32_t GINTF; /*!< Core Interrupt Register Address offset: 014h */
__IO uint32_t GINTEN; /*!< Core Interrupt Mask Register Address offset: 018h */
__IO uint32_t GRSTATR; /*!< Receive Sts Q Read Register Address offset: 01Ch */
__IO uint32_t GRSTATP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */
__IO uint32_t GRFLEN; /*!< Receive FIFO Size Register Address offset: 024h */
__IO uint32_t HNPTFLEN_DIEP0TFLEN; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */
__IO uint32_t HNPTFQSTAT; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */
uint32_t Reserved30[2]; /*!< Reserved 030h*/
__IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */
__IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */
uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */
__IO uint32_t HPTFLEN; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */
__IO uint32_t DIEPTFLEN[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */
} USB_OTG_GlobalTypeDef;
/**
* @brief __device_Registers
*/
typedef struct
{
__IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/
__IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/
__IO uint32_t DSTAT; /*!< dev Status Register (RO) Address offset: 808h*/
uint32_t Reserved0C; /*!< Reserved 80Ch*/
__IO uint32_t DIEPINTF; /*!< dev IN Endpoint Mask Address offset: 810h*/
__IO uint32_t DOEPINTF; /*!< dev OUT Endpoint Mask Address offset: 814h*/
__IO uint32_t DAEPINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/
__IO uint32_t DAEPINTEN; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/
uint32_t Reserved20; /*!< Reserved 820h*/
uint32_t Reserved9; /*!< Reserved 824h*/
__IO uint32_t DVBUSDT; /*!< dev VBUS discharge Register Address offset: 828h*/
__IO uint32_t DVBUSPT; /*!< dev VBUS Pulse Register Address offset: 82Ch*/
__IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/
__IO uint32_t DIEPFEINTEN; /*!< dev empty msk Address offset: 834h*/
__IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/
__IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/
uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/
__IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/
uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/
__IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/
} USB_OTG_DeviceTypeDef;
/**
* @brief __IN_Endpoint-Specific_Register
*/
typedef struct
{
__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t DIEPINTF; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DIEPLEN; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
__IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
__IO uint32_t DIEPTFSTAT; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
} USB_OTG_INEndpointTypeDef;
/**
* @brief __OUT_Endpoint-Specific_Registers
*/
typedef struct
{
__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINTF; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DOEPLEN; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
} USB_OTG_OUTEndpointTypeDef;
/**
* @brief __Host_Mode_Register_Structures
*/
typedef struct
{
__IO uint32_t HCTL; /*!< Host Configuration Register 400h*/
__IO uint32_t HFT; /*!< Host Frame Interval Register 404h*/
__IO uint32_t HFINFR; /*!< Host Frame Nbr/Frame Remaining 408h*/
uint32_t Reserved40C; /*!< Reserved 40Ch*/
__IO uint32_t HPTFQSTAT; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/
__IO uint32_t HACHINT; /*!< Host All Channels Interrupt Register 414h*/
__IO uint32_t HACHINTEN; /*!< Host All Channels Interrupt Mask 418h*/
} USB_OTG_HostTypeDef;
/**
* @brief __Host_Channel_Specific_Registers
*/
typedef struct
{
__IO uint32_t HCHCTL;
__IO uint32_t HCSPLT;
__IO uint32_t HCHINTF;
__IO uint32_t HCHINTEN;
__IO uint32_t HCHLEN;
__IO uint32_t HCDMA;
uint32_t Reserved[2];
} USB_OTG_HostChannelTypeDef;
/**
* @brief Window WATCHDOG
*/