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Renumber ADC peripherals to begin at 0

This commit is contained in:
Stefan Kerkmann 2021-04-05 17:37:28 +02:00
parent 2cd74f3ea2
commit 387ccb8dea
5 changed files with 71 additions and 71 deletions
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12
os/hal/ports/GD/GD32VF103/gd32_rcu.h
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@ -177,28 +177,28 @@
* @{
*/
/**
* @brief Enables the ADC1 peripheral clock.
* @brief Enables the ADC0 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rcuEnableADC1(lp) rcuEnableAPB2(RCU_APB2ENR_ADC1EN, lp)
#define rcuEnableADC0(lp) rcuEnableAPB2(RCU_APB2ENR_ADC0EN, lp)
/**
* @brief Disables the ADC1 peripheral clock.
* @brief Disables the ADC0 peripheral clock.
*
* @api
*/
#define rcuDisableADC1() rcuDisableAPB2(RCU_APB2ENR_ADC1EN)
#define rcuDisableADC0() rcuDisableAPB2(RCU_APB2ENR_ADC0EN)
/**
* @brief Resets the ADC1 peripheral.
* @brief Resets the ADC0 peripheral.
*
* @api
*/
#define rcuResetADC1() rcuResetAPB2(RCU_APB2RSTR_ADC1RST)
#define rcuResetADC0() rcuResetAPB2(RCU_APB2RSTR_ADC0RST)
/** @} */
/**

4
os/hal/ports/GD/GD32VF103/gd32_registry.h
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@ -98,8 +98,8 @@
* @{
*/
/* ADC attributes.*/
#define GD32_HAS_ADC0 TRUE
#define GD32_HAS_ADC1 TRUE
#define GD32_HAS_ADC2 TRUE
/* CAN attributes.*/
#define GD32_HAS_CAN0 TRUE
@ -143,7 +143,7 @@
#define GD32_DMA1_CH4_NUMBER 79
/* EXTI attributes.*/
#define GD32_EXTI_NUM_LINES 19
#define GD32_EXTI_NUM_LINES 15
#define GD32_EXTI_IMR_MASK 0x00000000U
/* Flash attributes.*/

44
os/hal/ports/GD/GD32VF103/hal_adc_lld.c
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@ -34,8 +34,8 @@
/* Driver exported variables. */
/*===========================================================================*/
/** @brief ADC1 driver identifier.*/
#if GD32_ADC_USE_ADC1 || defined(__DOXYGEN__)
/** @brief ADC0 driver identifier.*/
#if GD32_ADC_USE_ADC0 || defined(__DOXYGEN__)
ADCDriver ADCD1;
#endif
@ -88,34 +88,34 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
*/
void adc_lld_init(void) {
#if GD32_ADC_USE_ADC1
#if GD32_ADC_USE_ADC0
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.adc = ADC0;
ADCD1.dmastp = NULL;
ADCD1.dmamode = GD32_DMA_CTL_PRIO(GD32_ADC_ADC1_DMA_PRIORITY) |
ADCD1.dmamode = GD32_DMA_CTL_PRIO(GD32_ADC_ADC0_DMA_PRIORITY) |
GD32_DMA_CTL_MWIDTH_HWORD | GD32_DMA_CTL_PWIDTH_HWORD |
GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_FTFIE |
GD32_DMA_CTL_ERRIE;
/* Temporary activation.*/
rcuEnableADC1(true);
ADC1->CTL0 = 0;
ADC1->CTL1 = ADC_CTL1_ADCON;
rcuEnableADC0(true);
ADC0->CTL0 = 0;
ADC0->CTL1 = ADC_CTL1_ADCON;
/* Reset calibration just to be safe.*/
ADC1->CTL1 = ADC_CTL1_ADCON | ADC_CTL1_RSTCLB;
while ((ADC1->CTL1 & ADC_CTL1_RSTCLB) != 0)
ADC0->CTL1 = ADC_CTL1_ADCON | ADC_CTL1_RSTCLB;
while ((ADC0->CTL1 & ADC_CTL1_RSTCLB) != 0)
;
/* Calibration.*/
ADC1->CTL1 = ADC_CTL1_ADCON | ADC_CTL1_CLB;
while ((ADC1->CTL1 & ADC_CTL1_CLB) != 0)
ADC0->CTL1 = ADC_CTL1_ADCON | ADC_CTL1_CLB;
while ((ADC0->CTL1 & ADC_CTL1_CLB) != 0)
;
/* Return the ADC in low power mode.*/
ADC1->CTL1 = 0;
rcuDisableADC1();
ADC0->CTL1 = 0;
rcuDisableADC0();
#endif
}
@ -130,15 +130,15 @@ void adc_lld_start(ADCDriver *adcp) {
/* If in stopped state then enables the ADC and DMA clocks.*/
if (adcp->state == ADC_STOP) {
#if GD32_ADC_USE_ADC1
#if GD32_ADC_USE_ADC0
if (&ADCD1 == adcp) {
adcp->dmastp = dmaStreamAllocI(GD32_DMA_STREAM_ID(1, 1),
GD32_ADC_ADC1_IRQ_PRIORITY,
GD32_ADC_ADC0_IRQ_PRIORITY,
(gd32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->RDATA);
rcuEnableADC1(true);
dmaStreamSetPeripheral(adcp->dmastp, &ADC0->RDATA);
rcuEnableADC0(true);
}
#endif
@ -160,15 +160,15 @@ void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock.*/
if (adcp->state == ADC_READY) {
#if GD32_ADC_USE_ADC1
#if GD32_ADC_USE_ADC0
if (&ADCD1 == adcp) {
ADC1->CTL0 = 0;
ADC1->CTL1 = 0;
ADC0->CTL0 = 0;
ADC0->CTL1 = 0;
dmaStreamFreeI(adcp->dmastp);
adcp->dmastp = NULL;
rcuDisableADC1();
rcuDisableADC0();
}
#endif
}

28
os/hal/ports/GD/GD32VF103/hal_adc_lld.h
View File

@ -86,26 +86,26 @@
* @{
*/
/**
* @brief ADC1 driver enable switch.
* @details If set to @p TRUE the support for ADC1 is included.
* @brief ADC0 driver enable switch.
* @details If set to @p TRUE the support for ADC0 is included.
* @note The default is @p TRUE.
*/
#if !defined(GD32_ADC_USE_ADC1) || defined(__DOXYGEN__)
#define GD32_ADC_USE_ADC1 FALSE
#if !defined(GD32_ADC_USE_ADC0) || defined(__DOXYGEN__)
#define GD32_ADC_USE_ADC0 FALSE
#endif
/**
* @brief ADC1 DMA priority (0..3|lowest..highest).
* @brief ADC0 DMA priority (0..3|lowest..highest).
*/
#if !defined(GD32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ADC_ADC1_DMA_PRIORITY 2
#if !defined(GD32_ADC_ADC0_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ADC_ADC0_DMA_PRIORITY 2
#endif
/**
* @brief ADC1 interrupt priority level setting.
* @brief ADC0 interrupt priority level setting.
*/
#if !defined(GD32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ADC_ADC1_IRQ_PRIORITY 5
#if !defined(GD32_ADC_ADC0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ADC_ADC0_IRQ_PRIORITY 5
#endif
/** @} */
@ -113,11 +113,11 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if GD32_ADC_USE_ADC1 && !GD32_HAS_ADC1
#error "ADC1 not present in the selected device"
#if GD32_ADC_USE_ADC0 && !GD32_HAS_ADC0
#error "ADC0 not present in the selected device"
#endif
#if !GD32_ADC_USE_ADC1
#if !GD32_ADC_USE_ADC0
#error "ADC driver activated but no ADC peripheral assigned"
#endif
@ -261,7 +261,7 @@ typedef enum {
/* External declarations. */
/*===========================================================================*/
#if GD32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
#if GD32_ADC_USE_ADC0 && !defined(__DOXYGEN__)
extern ADCDriver ADCD1;
#endif

54
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -117,11 +117,11 @@ typedef struct
typedef struct
{
__IO uint32_t STAT; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
__IO uint32_t CTL0; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
__IO uint32_t CTL1; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
__IO uint32_t STAT; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC0 base address */
__IO uint32_t CTL0; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC0 base address + 0x04 */
__IO uint32_t CTL1; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC0 base address + 0x08 */
uint32_t RESERVED[16];
__IO uint32_t RDATA; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
__IO uint32_t RDATA; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC0 base address + 0x4C */
} ADC_Common_TypeDef;
/**
@ -676,8 +676,8 @@ typedef struct
#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
#define ADC0_BASE (APB2PERIPH_BASE + 0x00002400U)
#define ADC1_BASE (APB2PERIPH_BASE + 0x00002800U)
#define TIM0_BASE (APB2PERIPH_BASE + 0x00002C00U)
#define SPI0_BASE (APB2PERIPH_BASE + 0x00003000U)
#define USART0_BASE (APB2PERIPH_BASE + 0x00003800U)
@ -764,9 +764,9 @@ typedef struct
#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
#define ADC0 ((ADC_TypeDef *)ADC0_BASE)
#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
#define ADC02_COMMON ((ADC_Common_TypeDef *)ADC0_BASE)
#define TIM0 ((TIM_TypeDef *)TIM0_BASE)
#define SPI0 ((SPI_TypeDef *)SPI0_BASE)
#define USART0 ((USART_TypeDef *)USART0_BASE)
@ -1455,13 +1455,13 @@ typedef struct
#define RCU_APB2RSTR_IOPDRST_Pos (5U)
#define RCU_APB2RSTR_IOPDRST_Msk (0x1U << RCU_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
#define RCU_APB2RSTR_IOPDRST RCU_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
#define RCU_APB2RSTR_ADC1RST_Pos (9U)
#define RCU_APB2RSTR_ADC1RST_Msk (0x1U << RCU_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
#define RCU_APB2RSTR_ADC1RST RCU_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
#define RCU_APB2RSTR_ADC0RST_Pos (9U)
#define RCU_APB2RSTR_ADC0RST_Msk (0x1U << RCU_APB2RSTR_ADC0RST_Pos) /*!< 0x00000200 */
#define RCU_APB2RSTR_ADC0RST RCU_APB2RSTR_ADC0RST_Msk /*!< ADC 1 interface reset */
#define RCU_APB2RSTR_ADC2RST_Pos (10U)
#define RCU_APB2RSTR_ADC2RST_Msk (0x1U << RCU_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
#define RCU_APB2RSTR_ADC2RST RCU_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
#define RCU_APB2RSTR_ADC1RST_Pos (10U)
#define RCU_APB2RSTR_ADC1RST_Msk (0x1U << RCU_APB2RSTR_ADC1RST_Pos) /*!< 0x00000400 */
#define RCU_APB2RSTR_ADC1RST RCU_APB2RSTR_ADC1RST_Msk /*!< ADC 2 interface reset */
#define RCU_APB2RSTR_TIM0RST_Pos (11U)
#define RCU_APB2RSTR_TIM0RST_Msk (0x1U << RCU_APB2RSTR_TIM0RST_Pos) /*!< 0x00000800 */
@ -1591,13 +1591,13 @@ typedef struct
#define RCU_APB2ENR_IOPDEN_Pos (5U)
#define RCU_APB2ENR_IOPDEN_Msk (0x1U << RCU_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
#define RCU_APB2ENR_IOPDEN RCU_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
#define RCU_APB2ENR_ADC1EN_Pos (9U)
#define RCU_APB2ENR_ADC1EN_Msk (0x1U << RCU_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
#define RCU_APB2ENR_ADC1EN RCU_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
#define RCU_APB2ENR_ADC0EN_Pos (9U)
#define RCU_APB2ENR_ADC0EN_Msk (0x1U << RCU_APB2ENR_ADC0EN_Pos) /*!< 0x00000200 */
#define RCU_APB2ENR_ADC0EN RCU_APB2ENR_ADC0EN_Msk /*!< ADC 1 interface clock enable */
#define RCU_APB2ENR_ADC2EN_Pos (10U)
#define RCU_APB2ENR_ADC2EN_Msk (0x1U << RCU_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
#define RCU_APB2ENR_ADC2EN RCU_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
#define RCU_APB2ENR_ADC1EN_Pos (10U)
#define RCU_APB2ENR_ADC1EN_Msk (0x1U << RCU_APB2ENR_ADC1EN_Pos) /*!< 0x00000400 */
#define RCU_APB2ENR_ADC1EN RCU_APB2ENR_ADC1EN_Msk /*!< ADC 2 interface clock enable */
#define RCU_APB2ENR_TIM0EN_Pos (11U)
#define RCU_APB2ENR_TIM0EN_Msk (0x1U << RCU_APB2ENR_TIM0EN_Pos) /*!< 0x00000800 */
@ -12495,14 +12495,14 @@ typedef struct
*/
/****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC0) || \
((INSTANCE) == ADC1))
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC02_COMMON)
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC0)
#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC0)
/****************************** CAN Instances *********************************/
#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
@ -12850,7 +12850,7 @@ typedef struct
/******************************************************************************/
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
#define ADC0_IRQn ADC0_2_IRQn
#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
#define USB_LP_IRQn CAN1_RX0_IRQn
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
@ -12871,7 +12871,7 @@ typedef struct
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
#define ADC0_IRQHandler ADC0_2_IRQHandler
#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler