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Rename ADC registers

This commit is contained in:
Stefan Kerkmann 2021-03-30 22:03:22 +02:00
parent 14a840f775
commit 4aa9da0f34
4 changed files with 568 additions and 571 deletions
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52
os/hal/ports/GD/GD32VF103/hal_adc_lld.c
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@ -100,21 +100,21 @@ void adc_lld_init(void) {
/* Temporary activation.*/
rccEnableADC1(true);
ADC1->CR1 = 0;
ADC1->CR2 = ADC_CR2_ADON;
ADC1->CTL0 = 0;
ADC1->CTL1 = ADC_CTL1_ADCON;
/* Reset calibration just to be safe.*/
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
ADC1->CTL1 = ADC_CTL1_ADCON | ADC_CTL1_RSTCLB;
while ((ADC1->CTL1 & ADC_CTL1_RSTCLB) != 0)
;
/* Calibration.*/
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
ADC1->CTL1 = ADC_CTL1_ADCON | ADC_CTL1_CLB;
while ((ADC1->CTL1 & ADC_CTL1_CLB) != 0)
;
/* Return the ADC in low power mode.*/
ADC1->CR2 = 0;
ADC1->CTL1 = 0;
rccDisableADC1();
#endif
}
@ -137,15 +137,15 @@ void adc_lld_start(ADCDriver *adcp) {
(gd32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->RDATA);
rccEnableADC1(true);
}
#endif
/* ADC setup, the calibration procedure has already been performed
during initialization.*/
adcp->adc->CR1 = 0;
adcp->adc->CR2 = 0;
adcp->adc->CTL0 = 0;
adcp->adc->CTL1 = 0;
}
}
@ -162,8 +162,8 @@ void adc_lld_stop(ADCDriver *adcp) {
if (adcp->state == ADC_READY) {
#if GD32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
ADC1->CR1 = 0;
ADC1->CR2 = 0;
ADC1->CTL0 = 0;
ADC1->CTL1 = 0;
dmaStreamFreeI(adcp->dmastp);
adcp->dmastp = NULL;
@ -182,7 +182,7 @@ void adc_lld_stop(ADCDriver *adcp) {
* @notapi
*/
void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t mode, cr2;
uint32_t mode, ctl1;
const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/
@ -202,19 +202,19 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamEnable(adcp->dmastp);
/* ADC setup.*/
adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN;
cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0)
cr2 |= ADC_CR2_CONT;
adcp->adc->CR2 = grpp->cr2 | cr2;
adcp->adc->SMPR1 = grpp->smpr1;
adcp->adc->SMPR2 = grpp->smpr2;
adcp->adc->SQR1 = grpp->sqr1;
adcp->adc->SQR2 = grpp->sqr2;
adcp->adc->SQR3 = grpp->sqr3;
adcp->adc->CTL0 = grpp->ctl0 | ADC_CTL0_SM;
ctl1 = grpp->ctl1 | ADC_CTL1_DMA | ADC_CTL1_ADCON;
if ((ctl1 & (ADC_CTL1_ETERC | ADC_CTL1_ETEIC)) == 0)
ctl1 |= ADC_CTL1_CTN;
adcp->adc->CTL1 = grpp->ctl1 | ctl1;
adcp->adc->SAMPT0 = grpp->sampt0;
adcp->adc->SAMPT1 = grpp->sampt1;
adcp->adc->RSQ0 = grpp->rsq0;
adcp->adc->RSQ1 = grpp->rsq1;
adcp->adc->RSQ2 = grpp->rsq2;
/* ADC start by writing ADC_CR2_ADON a second time.*/
adcp->adc->CR2 = cr2;
/* ADC start by writing ADC_CTL1_ADCON a second time.*/
adcp->adc->CTL1 = ctl1;
}
/**
@ -227,7 +227,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
void adc_lld_stop_conversion(ADCDriver *adcp) {
dmaStreamDisable(adcp->dmastp);
adcp->adc->CR2 = 0;
adcp->adc->CTL1 = 0;
}
#endif /* HAL_USE_ADC */

92
os/hal/ports/GD/GD32VF103/hal_adc_lld.h
View File

@ -35,8 +35,8 @@
* @name Triggers selection
* @{
*/
#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */
#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */
#define ADC_CTL1_ETSRC_SRC(n) ((n) << 17) /**< @brief Trigger source. */
#define ADC_CTL1_ETSRC_SWSTART (7 << 17) /**< @brief Software trigger. */
/** @} */
/**
@ -176,30 +176,30 @@ typedef enum {
#define adc_lld_configuration_group_fields \
/* ADC CR1 register initialization data. \
NOTE: All the required bits must be defined into this field except \
@p ADC_CR1_SCAN that is enforced inside the driver.*/ \
uint32_t cr1; \
@p ADC_CTL0_SM that is enforced inside the driver.*/ \
uint32_t ctl0; \
/* ADC CR2 register initialization data. \
NOTE: All the required bits must be defined into this field except \
@p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are \
@p ADC_CTL1_DMA, @p ADC_CTL1_CTN and @p ADC_CTL1_ADCON that are \
enforced inside the driver.*/ \
uint32_t cr2; \
uint32_t ctl1; \
/* ADC SMPR1 register initialization data. \
NOTE: In this field must be specified the sample times for channels \
10...17.*/ \
uint32_t smpr1; \
uint32_t sampt0; \
/* ADC SMPR2 register initialization data. \
NOTE: In this field must be specified the sample times for channels \
0...9.*/ \
uint32_t smpr2; \
uint32_t sampt1; \
/* ADC SQR1 register initialization data. \
NOTE: Conversion group sequence 13...16 + sequence length.*/ \
uint32_t sqr1; \
uint32_t rsq0; \
/* ADC SQR2 register initialization data. \
NOTE: Conversion group sequence 7...12.*/ \
uint32_t sqr2; \
uint32_t rsq1; \
/* ADC SQR3 register initialization data. \
NOTE: Conversion group sequence 1...6.*/ \
uint32_t sqr3
uint32_t rsq2
/**
* @name Sequences building helper macros
@ -208,52 +208,52 @@ typedef enum {
/**
* @brief Number of channels in a conversion sequence.
*/
#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
#define ADC_RSQ0_NUM_CH(n) (((n) - 1) << 20)
#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
#define ADC_RSQ2_RSQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
#define ADC_RSQ2_RSQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
#define ADC_RSQ2_RSQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
#define ADC_RSQ2_RSQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
#define ADC_RSQ2_RSQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
#define ADC_RSQ2_RSQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
#define ADC_RSQ1_RSQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
#define ADC_RSQ1_RSQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
#define ADC_RSQ1_RSQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
#define ADC_RSQ1_RSQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
#define ADC_RSQ1_RSQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
#define ADC_RSQ1_RSQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
#define ADC_RSQ0_RSQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
#define ADC_RSQ0_RSQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
#define ADC_RSQ0_RSQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
#define ADC_RSQ0_RSQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
/** @} */
/**
* @name Sampling rate settings helper macros
* @{
*/
#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
#define ADC_SAMPT1_SMP_SPT0(n) ((n) << 0) /**< @brief AN0 sampling time. */
#define ADC_SAMPT1_SMP_SPT1(n) ((n) << 3) /**< @brief AN1 sampling time. */
#define ADC_SAMPT1_SMP_SPT2(n) ((n) << 6) /**< @brief AN2 sampling time. */
#define ADC_SAMPT1_SMP_SPT3(n) ((n) << 9) /**< @brief AN3 sampling time. */
#define ADC_SAMPT1_SMP_SPT4(n) ((n) << 12) /**< @brief AN4 sampling time. */
#define ADC_SAMPT1_SMP_SPT5(n) ((n) << 15) /**< @brief AN5 sampling time. */
#define ADC_SAMPT1_SMP_SPT6(n) ((n) << 18) /**< @brief AN6 sampling time. */
#define ADC_SAMPT1_SMP_SPT7(n) ((n) << 21) /**< @brief AN7 sampling time. */
#define ADC_SAMPT1_SMP_SPT8(n) ((n) << 24) /**< @brief AN8 sampling time. */
#define ADC_SAMPT1_SMP_SPT9(n) ((n) << 27) /**< @brief AN9 sampling time. */
#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
#define ADC_SAMPT0_SMP_SPT10(n) ((n) << 0) /**< @brief AN10 sampling time. */
#define ADC_SAMPT0_SMP_SPT11(n) ((n) << 3) /**< @brief AN11 sampling time. */
#define ADC_SAMPT0_SMP_SPT12(n) ((n) << 6) /**< @brief AN12 sampling time. */
#define ADC_SAMPT0_SMP_SPT13(n) ((n) << 9) /**< @brief AN13 sampling time. */
#define ADC_SAMPT0_SMP_SPT14(n) ((n) << 12) /**< @brief AN14 sampling time. */
#define ADC_SAMPT0_SMP_SPT15(n) ((n) << 15) /**< @brief AN15 sampling time. */
#define ADC_SAMPT0_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
sampling time. */
#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
#define ADC_SAMPT0_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
sampling time. */
/** @} */

43
os/hal/ports/GD/GD32VF103/platform.mk
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@ -1,29 +1,32 @@
# List of all the template platform files.
# Required platform files.
PLATFORMSRC := ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/hal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC/eclic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/gd32_isr.c \
${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/hal_efl_lld.c
# Required include directories.
PLATFORMINC := ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103 \
${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC
# Optional platform files.
ifeq ($(USE_SMART_BUILD),yes)
# Configuration files directory
ifeq ($(CONFDIR),)
CONFDIR = .
ifeq ($(HALCONFDIR),)
ifeq ($(CONFDIR),)
HALCONFDIR = .
else
HALCONFDIR := $(CONFDIR)
endif
endif
HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define"))
PLATFORMSRC := ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/hal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC/eclic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/gd32_isr.c
else
PLATFORMSRC = ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/hal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC/eclic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/gd32_isr.c
endif
# Required include directories
PLATFORMINC = ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103 \
${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC
HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/GD/GD32VF103/hal_adc_lld.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/GD/GD32VF103/hal_adc_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/GD/GD32VF103/hal_adc_lld.c
endif
# Drivers compatible with the platform.
@ -41,4 +44,4 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/xWDG/driver.mk
# Shared variables
ALLCSRC += $(PLATFORMSRC)
ALLINC += $(PLATFORMINC)
ALLINC += $(PLATFORMINC)

952
os/hal/ports/GD/GD32VF103/stm32f105xc.h
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