GPIO Remove obsolete ports, rename registers
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@ -30,12 +30,7 @@
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/* Driver local definitions. */
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/*===========================================================================*/
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#if GD32_HAS_GPIOG
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
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RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
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#elif GD32_HAS_GPIOE
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#if GD32_HAS_GPIOE
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN)
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@ -98,32 +93,22 @@ void _pal_lld_init(const PALConfig *config) {
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/*
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* Initial GPIO setup.
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*/
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GPIOA->ODR = config->PAData.odr;
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GPIOA->CRH = config->PAData.crh;
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GPIOA->CRL = config->PAData.crl;
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GPIOB->ODR = config->PBData.odr;
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GPIOB->CRH = config->PBData.crh;
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GPIOB->CRL = config->PBData.crl;
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GPIOC->ODR = config->PCData.odr;
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GPIOC->CRH = config->PCData.crh;
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GPIOC->CRL = config->PCData.crl;
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GPIOD->ODR = config->PDData.odr;
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GPIOD->CRH = config->PDData.crh;
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GPIOD->CRL = config->PDData.crl;
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GPIOA->OCTL = config->PAData.odr;
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GPIOA->CTL1 = config->PAData.crh;
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GPIOA->CTL0 = config->PAData.crl;
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GPIOB->OCTL = config->PBData.odr;
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GPIOB->CTL1 = config->PBData.crh;
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GPIOB->CTL0 = config->PBData.crl;
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GPIOC->OCTL = config->PCData.odr;
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GPIOC->CTL1 = config->PCData.crh;
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GPIOC->CTL0 = config->PCData.crl;
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GPIOD->OCTL = config->PDData.odr;
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GPIOD->CTL1 = config->PDData.crh;
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GPIOD->CTL0 = config->PDData.crl;
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#if GD32_HAS_GPIOE || defined(__DOXYGEN__)
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GPIOE->ODR = config->PEData.odr;
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GPIOE->CRH = config->PEData.crh;
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GPIOE->CRL = config->PEData.crl;
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#if GD32_HAS_GPIOF || defined(__DOXYGEN__)
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GPIOF->ODR = config->PFData.odr;
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GPIOF->CRH = config->PFData.crh;
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GPIOF->CRL = config->PFData.crl;
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#if GD32_HAS_GPIOG || defined(__DOXYGEN__)
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GPIOG->ODR = config->PGData.odr;
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GPIOG->CRH = config->PGData.crh;
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GPIOG->CRL = config->PGData.crl;
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#endif
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#endif
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GPIOE->OCTL = config->PEData.odr;
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GPIOE->CTL1 = config->PEData.crh;
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GPIOE->CTL0 = config->PEData.crl;
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#endif
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}
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@ -165,13 +150,14 @@ void _pal_lld_setgroupmode(ioportid_t port,
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0xB, /* PAL_MODE_GD32_ALTERNATE_PUSHPULL, 50MHz.*/
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0xF, /* PAL_MODE_GD32_ALTERNATE_OPENDRAIN, 50MHz.*/
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};
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// TODO RENAME
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uint32_t mh, ml, crh, crl, cfg;
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unsigned i;
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if (mode == PAL_MODE_INPUT_PULLUP)
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port->BSRR = mask;
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port->BOP = mask;
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else if (mode == PAL_MODE_INPUT_PULLDOWN)
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port->BRR = mask;
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port->BC = mask;
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cfg = cfgtab[mode];
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mh = ml = crh = crl = 0;
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for (i = 0; i < 8; i++) {
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@ -189,8 +175,8 @@ void _pal_lld_setgroupmode(ioportid_t port,
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crh |= cfg;
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mask <<= 1;
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}
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port->CRH = (port->CRH & mh) | crh;
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port->CRL = (port->CRL & ml) | crl;
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port->CTL1 = (port->CTL1 & mh) | crh;
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port->CTL0 = (port->CTL0 & ml) | crl;
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}
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#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__)
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@ -129,14 +129,6 @@ typedef struct {
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#if GD32_HAS_GPIOE || defined(__DOXYGEN__)
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/** @brief Port E setup data.*/
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gd32_gpio_setup_t PEData;
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#if GD32_HAS_GPIOF || defined(__DOXYGEN__)
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/** @brief Port F setup data.*/
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gd32_gpio_setup_t PFData;
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#if GD32_HAS_GPIOG || defined(__DOXYGEN__)
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/** @brief Port G setup data.*/
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gd32_gpio_setup_t PGData;
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#endif
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#endif
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#endif
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} PALConfig;
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@ -214,20 +206,6 @@ typedef uint32_t iopadid_t;
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#define IOPORT5 GPIOE
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#endif
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/**
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* @brief GPIO port F identifier.
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*/
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#if GD32_HAS_GPIOF || defined(__DOXYGEN__)
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#define IOPORT6 GPIOF
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#endif
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/**
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* @brief GPIO port G identifier.
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*/
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#if GD32_HAS_GPIOG || defined(__DOXYGEN__)
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#define IOPORT7 GPIOG
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#endif
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/*===========================================================================*/
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/* Implementation, some of the following macros could be implemented as */
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/* functions, if so please put them in pal_lld.c. */
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@ -252,7 +230,7 @@ typedef uint32_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_readport(port) ((ioportmask_t)((port)->IDR))
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#define pal_lld_readport(port) ((ioportmask_t)((port)->ISTAT))
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/**
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* @brief Reads the output latch.
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@ -266,7 +244,7 @@ typedef uint32_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_readlatch(port) ((ioportmask_t)((port)->ODR))
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#define pal_lld_readlatch(port) ((ioportmask_t)((port)->OCTL))
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/**
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* @brief Writes on a I/O port.
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@ -281,7 +259,7 @@ typedef uint32_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_writeport(port, bits) ((port)->ODR = (uint32_t)(bits))
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#define pal_lld_writeport(port, bits) ((port)->OCTL = (uint32_t)(bits))
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/**
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* @brief Sets a bits mask on a I/O port.
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@ -296,7 +274,7 @@ typedef uint32_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_setport(port, bits) ((port)->BSRR = (uint32_t)(bits))
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#define pal_lld_setport(port, bits) ((port)->BOP = (uint32_t)(bits))
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/**
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* @brief Clears a bits mask on a I/O port.
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@ -311,7 +289,7 @@ typedef uint32_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_clearport(port, bits) ((port)->BRR = (uint32_t)(bits))
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#define pal_lld_clearport(port, bits) ((port)->BC = (uint32_t)(bits))
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/**
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* @brief Writes a group of bits.
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@ -332,7 +310,7 @@ typedef uint32_t iopadid_t;
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#define pal_lld_writegroup(port, mask, offset, bits) { \
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uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \
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((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \
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(port)->BSRR = w; \
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(port)->BOP = w; \
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}
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/**
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@ -358,13 +358,13 @@ typedef struct
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typedef struct
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{
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__IO uint32_t CRL;
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__IO uint32_t CRH;
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__IO uint32_t IDR;
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__IO uint32_t ODR;
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__IO uint32_t BSRR;
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__IO uint32_t BRR;
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__IO uint32_t LCKR;
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__IO uint32_t CTL0;
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__IO uint32_t CTL1;
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__IO uint32_t ISTAT;
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__IO uint32_t OCTL;
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__IO uint32_t BOP;
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__IO uint32_t BC;
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__IO uint32_t LOCK;
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} GPIO_TypeDef;
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/**
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