rusefi
/
ChibiOS-Contrib
mirror of https://github.com/rusefi/ChibiOS-Contrib.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

moved i2c to LLD

This commit is contained in:
Stephane D'Alu 2016-07-11 23:09:07 +02:00
parent 5923ee5d50
commit 8eabdabb05
4 changed files with 40 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
os/hal/ports/NRF5/NRF51822/hal_i2c_lld.c → os/hal/ports/NRF5/LLD/hal_i2c_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51822/i2c_lld.c
* @brief NRF51822 I2C subsystem low level driver source.
* @file NRF5/LLD/hal_i2c_lld.c
* @brief NRF5 I2C subsystem low level driver source.
*
* @addtogroup I2C
* @{
@ -33,10 +33,10 @@
/*===========================================================================*/
/* These macros are needed to see if the slave is stuck and we as master send dummy clock cycles to end its wait */
#define I2C_HIGH(p) do { NRF_GPIO->OUTSET = (1UL << (p)); } while(0) /*!< Pulls I2C line high */
#define I2C_LOW(p) do { NRF_GPIO->OUTCLR = (1UL << (p)); } while(0) /*!< Pulls I2C line low */
#define I2C_INPUT(p) do { NRF_GPIO->DIRCLR = (1UL << (p)); } while(0) /*!< Configures I2C pin as input */
#define I2C_OUTPUT(p) do { NRF_GPIO->DIRSET = (1UL << (p)); } while(0) /*!< Configures I2C pin as output */
#define I2C_HIGH(p) do { IOPORT1->OUTSET = (1UL << (p)); } while(0) /*!< Pulls I2C line high */
#define I2C_LOW(p) do { IOPORT1->OUTCLR = (1UL << (p)); } while(0) /*!< Pulls I2C line low */
#define I2C_INPUT(p) do { IOPORT1->DIRCLR = (1UL << (p)); } while(0) /*!< Configures I2C pin as input */
#define I2C_OUTPUT(p) do { IOPORT1->DIRSET = (1UL << (p)); } while(0) /*!< Configures I2C pin as output */
#define I2C_PIN_CNF \
((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
@ -102,14 +102,14 @@ static void i2c_clear_bus(I2CDriver *i2cp)
const I2CConfig *cfg = i2cp->config;
int i;
NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
I2C_HIGH(cfg->sda_pad);
I2C_HIGH(cfg->scl_pad);
NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
nrf_delay_us(4);
@ -165,6 +165,9 @@ static void serve_interrupt(I2CDriver *i2cp) {
if(i2c->EVENTS_TXDSENT) {
i2c->EVENTS_TXDSENT = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_TXDSENT;
#endif
if(--i2cp->txbytes) {
@ -182,6 +185,10 @@ static void serve_interrupt(I2CDriver *i2cp) {
if(i2c->EVENTS_RXDREADY) {
i2c->EVENTS_RXDREADY = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_RXDREADY;
#endif
*i2cp->rxptr++ = i2c->RXD;
if(--i2cp->rxbytes) {
@ -194,7 +201,9 @@ static void serve_interrupt(I2CDriver *i2cp) {
uint32_t err = i2c->ERRORSRC;
i2c->EVENTS_ERROR = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_ERROR;
#endif
if (err & TWI_ERRORSRC_OVERRUN_Msk)
i2cp->errors |= I2C_OVERRUN;
if (err & (TWI_ERRORSRC_ANACK_Msk | TWI_ERRORSRC_DNACK_Msk))
@ -206,6 +215,9 @@ static void serve_interrupt(I2CDriver *i2cp) {
stop_count++;
i2c->EVENTS_STOPPED = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_STOPPED;
#endif
_i2c_wakeup_isr(i2cp);
}
}
@ -278,11 +290,15 @@ void i2c_lld_start(I2CDriver *i2cp) {
i2c_clear_bus(i2cp);
NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
i2c->EVENTS_RXDREADY = 0;
i2c->EVENTS_TXDSENT = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_RXDREADY;
(void)i2c->EVENTS_TXDSENT;
#endif
i2c->PSELSCL = cfg->scl_pad;
i2c->PSELSDA = cfg->sda_pad;
@ -330,8 +346,8 @@ void i2c_lld_stop(I2CDriver *i2cp) {
nvicDisableVector(I2C_IRQ_NUM);
NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
}
}

4
os/hal/ports/NRF5/NRF51822/hal_i2c_lld.h → os/hal/ports/NRF5/LLD/hal_i2c_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51822/i2c_lld.h
* @brief NRF51822 I2C subsystem low level driver header.
* @file NRF5/LLD/hal_i2c_lld.h
* @brief NRF5 I2C subsystem low level driver header.
*
* @addtogroup I2C
* @{

4
os/hal/ports/NRF5/NRF51822/platform.mk
View File

@ -20,7 +20,7 @@ PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c
endif
ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_i2c_lld.c
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c
endif
ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c
@ -49,7 +49,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c \

4
os/hal/ports/NRF5/NRF52832/platform.mk
View File

@ -15,6 +15,9 @@ endif
ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c
endif
ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c
endif
ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c
endif
@ -33,6 +36,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c \