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copy os/hal/ports/MIMXRT1062 from ../KINETIS/MK66F18 (no changes yet)

This commit is contained in:
Michael Stapelberg 2020-06-05 23:36:26 +02:00
parent 7bb5555a06
commit 92b862cdd0
5 changed files with 1226 additions and 0 deletions
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334
os/hal/ports/MIMXRT1062/hal_lld.c Normal file
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/*
ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
Portions Copyright (C) 2017 PJRC.COM, LLC.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
1. The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
2. If the Software is incorporated into a build system that allows
selection among a list of target devices, then similar target
devices manufactured by PJRC.COM must be included in the list of
target devices and selectable in the same manner.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/**
* @file MK66F18/hal_lld.c
* @brief Kinetis MK66F18 HAL Driver subsystem low level driver source template.
*
* @addtogroup HAL
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
#ifdef __CC_ARM
__attribute__ ((section(".ARM.__at_0x400")))
#else
__attribute__ ((used,section(".cfmconfig")))
#endif
const uint8_t _cfm[0x10] = {
0xFF, /* NV_BACKKEY3: KEY=0xFF */
0xFF, /* NV_BACKKEY2: KEY=0xFF */
0xFF, /* NV_BACKKEY1: KEY=0xFF */
0xFF, /* NV_BACKKEY0: KEY=0xFF */
0xFF, /* NV_BACKKEY7: KEY=0xFF */
0xFF, /* NV_BACKKEY6: KEY=0xFF */
0xFF, /* NV_BACKKEY5: KEY=0xFF */
0xFF, /* NV_BACKKEY4: KEY=0xFF */
0xFF, /* NV_FPROT3: PROT=0xFF */
0xFF, /* NV_FPROT2: PROT=0xFF */
0xFF, /* NV_FPROT1: PROT=0xFF */
0xFF, /* NV_FPROT0: PROT=0xFF */
0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
0xFF,
0xFF
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
* @todo Use a macro to define the system clock frequency.
*
* @notapi
*/
void hal_lld_init(void) {
#if defined(MK66F18)
/* Disable the MPU by default */
SYSMPU->CESR &= ~SYSMPU_CESR_VLD_MASK;
#endif
}
/**
* @brief MK66F18 clock initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function is meant to be invoked early during the system
* initialization, it is usually invoked from the file
* @p board.c.
* @todo This function needs to be more generic.
*
* @special
*/
void MK66F18_clock_init(void) {
#if !KINETIS_NO_INIT
/* Disable the watchdog */
WDOG->UNLOCK = 0xC520;
WDOG->UNLOCK = 0xD928;
WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
SIM->SCGC5 |= SIM_SCGC5_PORTA |
SIM_SCGC5_PORTB |
SIM_SCGC5_PORTC |
SIM_SCGC5_PORTD |
SIM_SCGC5_PORTE;
/* Ported from the Teensyduino Core Library at
https://github.com/PaulStoffregen/cores/blob/master/teensy3/mk20dx128.c
*/
/* Allow the MCU to enter High Speed Run mode (HSRUN) */
SMC->PMPROT = SMC_PMPROT_AHSRUN_SET(1) | SMC_PMPROT_AVLP_SET(1) | SMC_PMPROT_ALLS_SET(1) | SMC_PMPROT_AVLLS_SET(1);
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
/* This is the default mode at reset. */
/* Configure FEI mode */
MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
(KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
/* Set clock dividers */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
#if defined(MK66F18)
SIM_CLKDIV1_OUTDIV3(KINETIS_CLKDIV1_OUTDIV3-1) |
#endif
SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
uint32_t ratio, frdiv;
uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
uint8_t i;
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] = 0;
PORTA->PCR[19] = 0;
/*
* Start in FEI mode
*/
/* Internal capacitors for crystal */
#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* Disable the internal capacitors */
OSC0->CR = 0;
#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* TODO: need to add more flexible calculation, specially regarding
* divisors which may not be available depending on the XTAL
* frequency, which would required other registers to be modified.
*/
/* Enable OSC, low power mode */
if (KINETIS_XTAL_FREQUENCY > 8000000UL)
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0_SET(2);
else
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0_SET(1);
frdiv = 7;
ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
for (i = 0; i < ratio_quantity; ++i) {
if (ratio == ratios[i]) {
frdiv = i;
break;
}
}
/* Switch to crystal as clock source, FLL input of 31.25 KHz */
MCG->C1 = MCG_C1_CLKS_SET(2) | MCG_C1_FRDIV_SET(frdiv);
/* Wait for crystal oscillator to begin */
while (!(MCG->S & MCG_S_OSCINIT0));
/* Wait for the FLL to use the oscillator */
while (MCG->S & MCG_S_IREFST);
/* Wait for the MCGOUTCLK to use the oscillator */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_SET(2));
/* Ported from the Teensyduino Core Library at
https://github.com/PaulStoffregen/cores/blob/master/teensy3/mk20dx128.c
*/
#define F_CPU KINETIS_SYSCLK_FREQUENCY
#define MCG_C5 MCG->C5
#undef MCG_C5_PRDIV0
#define MCG_C5_PRDIV0 MCG_C5_PRDIV0_SET
#define MCG_C6 MCG->C6
#undef MCG_C6_VDIV0
#define MCG_C6_VDIV0 MCG_C6_VDIV0_SET
#if 1 /* PJRC_HSRUN */
// if we need faster than the crystal, turn on the PLL
SMC->PMCTRL = SMC_PMCTRL_RUNM_SET(3); // enter HSRUN mode
#define SMC_PMSTAT_HSRUN ((uint8_t)0x80)
while (SMC->PMSTAT != SMC_PMSTAT_HSRUN)
; // wait for HSRUN
#if F_CPU == 256000000
//See table in 27.4.6 MCG Control 6 Register (MCG_C6)
//16 -> Multiply factor 32. 32*8MHz =256MHz
MCG_C5 = MCG_C5_PRDIV0(0);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(16);
#elif F_CPU == 240000000
MCG_C5 = MCG_C5_PRDIV0(0);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(14);
#elif F_CPU == 216000000
MCG_C5 = MCG_C5_PRDIV0(0);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(11);
#elif F_CPU == 192000000
MCG_C5 = MCG_C5_PRDIV0(0);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(8);
#elif F_CPU == 180000000
MCG_C5 = MCG_C5_PRDIV0(1);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(29);
#elif F_CPU == 168000000
MCG_C5 = MCG_C5_PRDIV0(0);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(5);
#elif F_CPU == 144000000
MCG_C5 = MCG_C5_PRDIV0(0);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(2);
#elif F_CPU == 120000000
MCG_C5 = MCG_C5_PRDIV0(1);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(14);
#elif F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
MCG_C5 = MCG_C5_PRDIV0(1);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(8);
#elif F_CPU == 72000000
MCG_C5 = MCG_C5_PRDIV0(1);
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(2);
#elif F_CPU > 16000000
#error "MK66FX1M0 does not support this clock speed yet...."
#endif
#else /* PJRC_HSRUN */
/*
* Now in FBE mode
*/
#define KINETIS_PLLIN_FREQUENCY 2000000UL
/*
* Config PLL input for 2 MHz
* TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
*/
MCG->C5 = MCG_C5_PRDIV0_SET((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
/*
* Config PLL output to match KINETIS_SYSCLK_FREQUENCY
* TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
*/
for(i = 24; i < 56; i++)
{
if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
{
/* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0_SET(i-24);
break;
}
}
if(i>=56) /* Config PLL for 96 MHz output as default setting */
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0_SET(0);
#endif /* PJRC_HSRUN */
/* Wait for PLL to start using crystal as its input, and to lock */
while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
/*
* Now in PBE mode
*/
/* Set the PLL dividers for the different clocks */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
/* Configure peripherals to use MCGPLLCLK */
SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL;
/* Switch to PLL as clock source */
MCG->C1 = MCG_C1_CLKS_SET(0);
/* Wait for PLL clock to be used */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
/*
* Now in PEE mode
*/
#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
#error Unimplemented KINETIS_MCG_MODE
#endif /* KINETIS_MCG_MODE == ... */
#endif /* !KINETIS_NO_INIT */
}
/** @} */

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/*
ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file MK66F18/hal_lld.h
* @brief Kinetis MK66F18 HAL subsystem low level driver header.
*
* @addtogroup HAL
* @{
*/
#ifndef HAL_LLD_H_
#define HAL_LLD_H_
#include "kinetis_registry.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Defines the support for realtime counters in the HAL.
*/
#define HAL_IMPLEMENTS_COUNTERS FALSE
/**
* @name Platform identification
* @{
*/
#define PLATFORM_NAME "Kinetis"
/** @} */
/**
* @name Internal clock sources
* @{
*/
#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
/** @} */
#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Disables the MCG/system clock initialization in the HAL.
*/
#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
#define KINETIS_NO_INIT FALSE
#endif
/**
* @brief MCG mode selection.
*/
#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
#endif
/**
* @brief MCU PLL clock frequency.
*/
#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
#define KINETIS_PLLCLK_FREQUENCY 96000000UL
#endif
/**
* @brief Clock divider for core/system clocks (OUTDIV1).
* @note The allowed range is 1..16
* @note The default value is calculated for a 48 MHz system clock
* from a 96 MHz PLL output.
*/
#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
#if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
#define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
#else
#define KINETIS_CLKDIV1_OUTDIV1 2
#endif
#endif
/**
* @brief Clock divider for bus clock (OUTDIV2).
* @note The allowed range is 1..16
* @note The default value is calculated for a 48 MHz bus clock
* from a 96 MHz PLL output.
*/
#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
#if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
#define KINETIS_CLKDIV1_OUTDIV2 (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
#elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
#define KINETIS_CLKDIV1_OUTDIV2 KINETIS_CLKDIV1_OUTDIV1
#else
#define KINETIS_CLKDIV1_OUTDIV2 2
#endif
#endif
/**
* @brief Clock divider for FlexBus clock (OUTDIV3).
* @note The allowed range is 1..16
* @note The default value is calculated for a 48 MHz clock
* from a 96 MHz PLL output.
*/
#if !defined(KINETIS_CLKDIV1_OUTDIV3) || defined(__DOXYGEN__)
#if defined(KINETIS_FLEXBUSCLK_FREQUENCY) && KINETIS_FLEXBUSCLK_FREQUENCY > 0
#define KINETIS_CLKDIV1_OUTDIV3 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLEXBUSCLK_FREQUENCY)
#else
/* If no FlexBus frequency provided, use bus speed divider */
#define KINETIS_CLKDIV1_OUTDIV3 KINETIS_CLKDIV1_OUTDIV2
#endif
#endif
/**
* @brief Clock divider for flash clock (OUTDIV4).
* @note The allowed range is 1..16
* @note The default value is calculated for a 24 MHz flash clock
* from a 96 MHz PLL output
*/
#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
#if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
#define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
#elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
#define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_CLKDIV1_OUTDIV1*2)
#else
#define KINETIS_CLKDIV1_OUTDIV4 4
#endif
#endif
/**
* @brief FLL DCO tuning enable for 32.768 kHz reference.
* @note Set to 1 for fine-tuning DCO for maximum frequency with
* a 32.768 kHz reference.
* @note The default value is for a 32.768 kHz external crystal.
*/
#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
#define KINETIS_MCG_FLL_DMX32 1
#endif
/**
* @brief FLL DCO range selection.
* @note The allowed range is 0...3.
* @note The default value is calculated for 48 MHz FLL output
* from a 32.768 kHz external crystal.
* (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
*
*/
#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
#define KINETIS_MCG_FLL_DRS 2
#endif
/**
* @brief MCU system/core clock frequency.
*/
#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
#endif
/**
* @brief MCU bus clock frequency.
*/
#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
#define KINETIS_BUSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
#endif
/**
* @brief MCU flash clock frequency.
*/
#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !defined(KINETIS_SYSCLK_FREQUENCY)
#error KINETIS_SYSCLK_FREQUENCY must be defined
#endif
#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
#error KINETIS_SYSCLK_FREQUENCY out of range
#endif
#if !defined(KINETIS_BUSCLK_FREQUENCY)
#error KINETIS_BUSCLK_FREQUENCY must be defined
#endif
#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
#error KINETIS_BUSCLK_FREQUENCY out of range
#endif
#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
#error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
KINETIS_SYSCLK_FREQUENCY
#endif
#if !defined(KINETIS_FLASHCLK_FREQUENCY)
#error KINETIS_FLASHCLK_FREQUENCY must be defined
#endif
#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
#error KINETIS_FLASHCLK_FREQUENCY out of range
#endif
#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
#error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
KINETIS_SYSCLK_FREQUENCY
#endif
#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
#error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
#endif
#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
#endif
#if !(defined(KINETIS_CLKDIV1_OUTDIV3) && \
KINETIS_CLKDIV1_OUTDIV3 >= 1 && KINETIS_CLKDIV1_OUTDIV3 <= 16)
#error KINETIS_CLKDIV1_OUTDIV3 must be 1 through 16
#endif
#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
#endif
#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
#endif
#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type representing a system clock frequency.
*/
typedef uint32_t halclock_t;
/**
* @brief Type of the realtime free counter value.
*/
typedef uint32_t halrtcnt_t;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Returns the current value of the system free running counter.
* @note This service is implemented by returning the content of the
* DWT_CYCCNT register.
*
* @return The value of the system free running counter of
* type halrtcnt_t.
*
* @notapi
*/
#define hal_lld_get_counter_value() 0
/**
* @brief Realtime counter frequency.
* @note The DWT_CYCCNT register is incremented directly by the system
* clock so this function returns STM32_HCLK.
*
* @return The realtime counter frequency of type halclock_t.
*
* @notapi
*/
#define hal_lld_get_counter_frequency() 0
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#include "nvic.h"
#ifdef __cplusplus
extern "C" {
#endif
void hal_lld_init(void);
void MK66F18_clock_init(void);
#ifdef __cplusplus
}
#endif
#endif /* HAL_LLD_H_ */
/** @} */

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/*
ChibiOS - Copyright (C) 2014 Derek Mulcahy
(C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file MK66F18/kinetis_registry.h
* @brief MK66F18 capabilities registry.
*
* @addtogroup HAL
* @{
*/
#ifndef KINETIS_REGISTRY_H_
#define KINETIS_REGISTRY_H_
#if !defined(MK66F18) || defined(__DOXYGEN__)
#define MK66F18
#endif
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/**
* @brief Maximum system and core clock (f_SYS) frequency.
*/
#define KINETIS_SYSCLK_MAX 180000000L
/**
* @brief Maximum bus clock (f_BUS) frequency.
*/
#define KINETIS_BUSCLK_MAX 60000000L
/**
* @brief Maximum flash clock (f_FLASH) frequency.
*/
#define KINETIS_FLASHCLK_MAX 28000000L
/* ADC attributes.*/
#define KINETIS_HAS_ADC0 TRUE
#define KINETIS_ADC0_IRQ_VECTOR VectorDC
#define KINETIS_HAS_ADC1 TRUE
#define KINETIS_ADC1_IRQ_VECTOR Vector164
/* DAC attributes.*/
#define KINETIS_HAS_DAC0 TRUE
#define KINETIS_DAC0_IRQ_VECTOR Vector120
#define KINETIS_HAS_DAC1 TRUE
#define KINETIS_DAC1_IRQ_VECTOR Vector160
/* DMA attributes.*/
#define KINETIS_DMA0_IRQ_VECTOR Vector40
#define KINETIS_DMA1_IRQ_VECTOR Vector44
#define KINETIS_DMA2_IRQ_VECTOR Vector48
#define KINETIS_DMA3_IRQ_VECTOR Vector4C
#define KINETIS_DMA4_IRQ_VECTOR Vector50
#define KINETIS_DMA5_IRQ_VECTOR Vector54
#define KINETIS_DMA6_IRQ_VECTOR Vector58
#define KINETIS_DMA7_IRQ_VECTOR Vector5C
#define KINETIS_DMA8_IRQ_VECTOR Vector60
#define KINETIS_DMA9_IRQ_VECTOR Vector64
#define KINETIS_DMA10_IRQ_VECTOR Vector68
#define KINETIS_DMA11_IRQ_VECTOR Vector6C
#define KINETIS_DMA12_IRQ_VECTOR Vector70
#define KINETIS_DMA13_IRQ_VECTOR Vector74
#define KINETIS_DMA14_IRQ_VECTOR Vector78
#define KINETIS_DMA15_IRQ_VECTOR Vector7C
#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector80
/* EXT attributes.*/
#define KINETIS_PORTA_IRQ_VECTOR Vector12C
#define KINETIS_PORTB_IRQ_VECTOR Vector130
#define KINETIS_PORTC_IRQ_VECTOR Vector134
#define KINETIS_PORTD_IRQ_VECTOR Vector138
#define KINETIS_PORTE_IRQ_VECTOR Vector13C
#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
/* I2C attributes.*/
#define KINETIS_HAS_I2C0 TRUE
#define KINETIS_I2C0_IRQ_VECTOR VectorA0
#define KINETIS_HAS_I2C1 TRUE
#define KINETIS_I2C1_IRQ_VECTOR VectorA4
/* Serial attributes.*/
#define KINETIS_HAS_SERIAL0 TRUE
#define KINETIS_SERIAL0_IRQ_VECTOR VectorBC
#define KINETIS_HAS_SERIAL1 TRUE
#define KINETIS_SERIAL1_IRQ_VECTOR VectorC4
#define KINETIS_HAS_SERIAL2 TRUE
#define KINETIS_SERIAL2_IRQ_VECTOR VectorCC
#define KINETIS_HAS_SERIAL3 TRUE
#define KINETIS_SERIAL3_IRQ_VECTOR VectorD4
#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorC0
#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR VectorC8
#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR VectorD0
#define KINETIS_SERIAL3_ERROR_IRQ_VECTOR VectorD8
#define KINETIS_SERIAL0_IS_LPUART FALSE
#define KINETIS_SERIAL0_IS_UARTLP FALSE
#define KINETIS_SERIAL1_IS_LPUART FALSE
#define KINETIS_SERIAL1_IS_UARTLP FALSE
#define KINETIS_SERIAL2_IS_LPUART FALSE
#define KINETIS_SERIAL2_IS_UARTLP FALSE
#define KINETIS_SERIAL3_IS_LPUART FALSE
#define KINETIS_SERIAL3_IS_UARTLP FALSE
/* SPI attributes.*/
#define KINETIS_HAS_SPI0 TRUE
#define KINETIS_SPI0_IRQ_VECTOR VectorA8
#define KINETIS_HAS_SPI1 TRUE
#define KINETIS_SPI1_IRQ_VECTOR VectorAC
/* FlexTimer attributes.*/
#define KINETIS_FTM0_CHANNELS 8
#define KINETIS_FTM1_CHANNELS 2
#define KINETIS_FTM2_CHANNELS 2
#define KINETIS_FTM3_CHANNELS 8
#define KINETIS_HAS_FTM0 TRUE
#define KINETIS_FTM0_IRQ_VECTOR VectorE8
#define KINETIS_HAS_FTM1 TRUE
#define KINETIS_FTM1_IRQ_VECTOR VectorEC
#define KINETIS_HAS_FTM2 TRUE
#define KINETIS_FTM2_IRQ_VECTOR VectorF0
#define KINETIS_HAS_FTM3 TRUE
#define KINETIS_FTM3_IRQ_VECTOR Vector15C
/* GPT attributes.*/
#define KINETIS_HAS_PIT0 TRUE
#define KINETIS_PIT0_IRQ_VECTOR Vector100
#define KINETIS_HAS_PIT1 TRUE
#define KINETIS_PIT1_IRQ_VECTOR Vector104
#define KINETIS_HAS_PIT2 TRUE
#define KINETIS_PIT2_IRQ_VECTOR Vector108
#define KINETIS_HAS_PIT3 TRUE
#define KINETIS_PIT3_IRQ_VECTOR Vector10C
#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
/* USB attributes.*/
#define KINETIS_HAS_USB TRUE
#define KINETIS_USB_IRQ_VECTOR Vector114
#define KINETIS_USB0_IS_USBOTG TRUE
#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
/* LPTMR attributes.*/
#define KINETIS_LPTMR0_IRQ_VECTOR Vector128
/* SDHC (SDC, MMC, SDIO) attributes */
#define KINETIS_HAS_SDHC TRUE
#define KINETIS_SDHC_IRQ_VECTOR Vector184
/** @} */
#endif /* KINETIS_REGISTRY_H_ */
/** @} */

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/*
ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/* TODO Still need to edit this entire file */
/**
* @defgroup MK66FX1M0_DRIVERS MK66FX1M0 Drivers
* @details This section describes all the supported drivers on the MK66FX1M0
* platform and the implementation details of the single drivers.
*
* @ingroup platforms
*/
/**
* @defgroup MK66FX1M0_HAL MK66FX1M0 Initialization Support
* @details The MK66FX1M0 HAL support is responsible for system initialization.
*
* @section mk66fx1m0_hal_1 Supported HW resources
* - PLL1.
* - PLL2.
* - RCC.
* - Flash.
* .
* @section mk66fx1m0_hal_2 MK66FX1M0 HAL driver implementation features
* - PLL startup and stabilization.
* - Clock tree initialization.
* - Clock source selection.
* - Flash wait states initialization based on the selected clock options.
* - SYSTICK initialization based on current clock and kernel required rate.
* - DMA support initialization.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_ADC MK66FX1M0 ADC Support
* @details The MK66FX1M0 ADC driver supports the ADC peripherals using DMA
* channels for maximum performance.
*
* @section mk66fx1m0_adc_1 Supported HW resources
* - ADC1.
* - ADC2.
* - ADC3.
* - DMA2.
* .
* @section mk66fx1m0_adc_2 MK66FX1M0 ADC driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Streaming conversion using DMA for maximum performance.
* - Programmable ADC interrupt priority level.
* - Programmable DMA bus priority for each DMA channel.
* - Programmable DMA interrupt priority for each DMA channel.
* - DMA and ADC errors detection.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_CAN MK66FX1M0 CAN Support
* @details The MK66FX1M0 CAN driver uses the CAN peripherals.
*
* @section mk66fx1m0_can_1 Supported HW resources
* - bxCAN1.
* .
* @section mk66fx1m0_can_2 MK66FX1M0 CAN driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Support for bxCAN sleep mode.
* - Programmable bxCAN interrupts priority level.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_EXT MK66FX1M0 EXT Support
* @details The MK66FX1M0 EXT driver uses the EXTI peripheral.
*
* @section mk66fx1m0_ext_1 Supported HW resources
* - EXTI.
* .
* @section mk66fx1m0_ext_2 MK66FX1M0 EXT driver implementation features
* - Each EXTI channel can be independently enabled and programmed.
* - Programmable EXTI interrupts priority level.
* - Capability to work as event sources (WFE) rather than interrupt sources.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_GPT MK66FX1M0 GPT Support
* @details The MK66FX1M0 GPT driver uses the TIMx peripherals.
*
* @section mk66fx1m0_gpt_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
* - TIM5.
* - TIM8.
* .
* @section mk66fx1m0_gpt_2 MK66FX1M0 GPT driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_ICU MK66FX1M0 ICU Support
* @details The MK66FX1M0 ICU driver uses the TIMx peripherals.
*
* @section mk66fx1m0_icu_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
* - TIM5.
* - TIM8.
* .
* @section mk66fx1m0_icu_2 MK66FX1M0 ICU driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_MAC MK66FX1M0 MAC Support
* @details The MK66FX1M0 MAC driver supports the ETH peripheral.
*
* @section mk66fx1m0_mac_1 Supported HW resources
* - ETH.
* - PHY (external).
* .
* @section mk66fx1m0_mac_2 MK66FX1M0 MAC driver implementation features
* - Dedicated DMA operations.
* - Support for checksum off-loading.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_PAL MK66FX1M0 PAL Support
* @details The MK66FX1M0 PAL driver uses the GPIO peripherals.
*
* @section mk66fx1m0_pal_1 Supported HW resources
* - GPIOA.
* - GPIOB.
* - GPIOC.
* - GPIOD.
* - GPIOE.
* - GPIOF.
* - GPIOG.
* - GPIOH.
* - GPIOI.
* .
* @section mk66fx1m0_pal_2 MK66FX1M0 PAL driver implementation features
* The PAL driver implementation fully supports the following hardware
* capabilities:
* - 16 bits wide ports.
* - Atomic set/reset functions.
* - Atomic set+reset function (atomic bus operations).
* - Output latched regardless of the pad setting.
* - Direct read of input pads regardless of the pad setting.
* .
* @section mk66fx1m0_pal_3 Supported PAL setup modes
* The MK66FX1M0 PAL driver supports the following I/O modes:
* - @p PAL_MODE_RESET.
* - @p PAL_MODE_UNCONNECTED.
* - @p PAL_MODE_INPUT.
* - @p PAL_MODE_INPUT_PULLUP.
* - @p PAL_MODE_INPUT_PULLDOWN.
* - @p PAL_MODE_INPUT_ANALOG.
* - @p PAL_MODE_OUTPUT_PUSHPULL.
* - @p PAL_MODE_OUTPUT_OPENDRAIN.
* - @p PAL_MODE_ALTERNATE (non standard).
* .
* Any attempt to setup an invalid mode is ignored.
*
* @section mk66fx1m0_pal_4 Suboptimal behavior
* The MK66FX1M0 GPIO is less than optimal in several areas, the limitations
* should be taken in account while using the PAL driver:
* - Pad/port toggling operations are not atomic.
* - Pad/group mode setup is not atomic.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_PWM MK66FX1M0 PWM Support
* @details The MK66FX1M0 PWM driver uses the TIMx peripherals.
*
* @section mk66fx1m0_pwm_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
* - TIM5.
* - TIM8.
* .
* @section mk66fx1m0_pwm_2 MK66FX1M0 PWM driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Four independent PWM channels per timer.
* - Programmable TIMx interrupts priority level.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_SDC MK66FX1M0 SDC Support
* @details The MK66FX1M0 SDC driver uses the SDIO peripheral.
*
* @section mk66fx1m0_sdc_1 Supported HW resources
* - SDIO.
* - DMA2.
* .
* @section mk66fx1m0_sdc_2 MK66FX1M0 SDC driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Programmable interrupt priority.
* - DMA is used for receiving and transmitting.
* - Programmable DMA bus priority for each DMA channel.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_SERIAL MK66FX1M0 Serial Support
* @details The MK66FX1M0 Serial driver uses the USART/UART peripherals in a
* buffered, interrupt driven, implementation.
*
* @section mk66fx1m0_serial_1 Supported HW resources
* The serial driver can support any of the following hardware resources:
* - USART1.
* - USART2.
* - USART3.
* - UART4.
* - UART5.
* - USART6.
* .
* @section mk66fx1m0_serial_2 MK66FX1M0 Serial driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Fully interrupt driven.
* - Programmable priority levels for each UART/USART.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_SPI MK66FX1M0 SPI Support
* @details The SPI driver supports the MK66FX1M0 SPI peripherals using DMA
* channels for maximum performance.
*
* @section mk66fx1m0_spi_1 Supported HW resources
* - SPI1.
* - SPI2.
* - SPI3.
* - DMA1.
* - DMA2.
* .
* @section mk66fx1m0_spi_2 MK66FX1M0 SPI driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each SPI can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable interrupt priority levels for each SPI.
* - DMA is used for receiving and transmitting.
* - Programmable DMA bus priority for each DMA channel.
* - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_UART MK66FX1M0 UART Support
* @details The UART driver supports the MK66FX1M0 USART peripherals using DMA
* channels for maximum performance.
*
* @section mk66fx1m0_uart_1 Supported HW resources
* The UART driver can support any of the following hardware resources:
* - USART1.
* - USART2.
* - USART3.
* - DMA1.
* - DMA2.
* .
* @section mk66fx1m0_uart_2 MK66FX1M0 UART driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable interrupt priority levels for each UART/USART.
* - DMA is used for receiving and transmitting.
* - Programmable DMA bus priority for each DMA channel.
* - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_PLATFORM_DRIVERS MK66FX1M0 Platform Drivers
* @details Platform support drivers. Platform drivers do not implement HAL
* standard driver templates, their role is to support platform
* specific functionalities.
*
* @ingroup MK66FX1M0_DRIVERS
*/
/**
* @defgroup MK66FX1M0_DMA MK66FX1M0 DMA Support
* @details This DMA helper driver is used by the other drivers in order to
* access the shared DMA resources in a consistent way.
*
* @section mk66fx1m0_dma_1 Supported HW resources
* The DMA driver can support any of the following hardware resources:
* - DMA1.
* - DMA2.
* .
* @section mk66fx1m0_dma_2 MK66FX1M0 DMA driver implementation features
* - Exports helper functions/macros to the other drivers that share the
* DMA resource.
* - Automatic DMA clock stop when not in use by any driver.
* - DMA streams and interrupt vectors sharing among multiple drivers.
* .
* @ingroup MK66FX1M0_PLATFORM_DRIVERS
*/
/**
* @defgroup MK66FX1M0_ISR MK66FX1M0 ISR Support
* @details This ISR helper driver is used by the other drivers in order to
* map ISR names to physical vector names.
*
* @ingroup MK66FX1M0_PLATFORM_DRIVERS
*/
/**
* @defgroup MK66FX1M0_RCC MK66FX1M0 RCC Support
* @details This RCC helper driver is used by the other drivers in order to
* access the shared RCC resources in a consistent way.
*
* @section mk66fx1m0_rcc_1 Supported HW resources
* - RCC.
* .
* @section mk66fx1m0_rcc_2 MK66FX1M0 RCC driver implementation features
* - Peripherals reset.
* - Peripherals clock enable.
* - Peripherals clock disable.
* .
* @ingroup MK66FX1M0_PLATFORM_DRIVERS
*/

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PLATFORMSRC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/hal_st_lld.c
PLATFORMINC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18
ifeq ($(USE_SMART_BUILD),yes)
# Configuration files directory
ifeq ($(CONFDIR),)
CONFDIR = .
endif
HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
endif
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SPIv1/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SDHCv1/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/FTMv1/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk
# Shared variables
ALLCSRC += $(PLATFORMSRC_CONTRIB)
ALLINC += $(PLATFORMINC_CONTRIB)