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sn32f2xx: spi driver (#40) 

* sn32 spi driver

* use spi0

* requested changes

* don't enable on init

* fix SPIx_Disable

* fix typo

* fix spi init
This commit is contained in:
1Conan 2022-02-05 02:53:21 +08:00 committed by Dimitris Mantzouranis
parent 99bd79f7c9
commit 98a487a74d
6 changed files with 312 additions and 280 deletions
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280
os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI.h
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@ -1,188 +1,190 @@
#ifndef __SN32F2XX_SSP_H
#define __SN32F2XX_SSP_H
#ifndef __SN32F2XX_SPI_H
#define __SN32F2XX_SPI_H
#include "hal.h"
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4001 C000 (SSP0)
0x4005 8000 (SSP1)
*/
Base Address: 0x4001 C000 (SPI0)
/* SSP n Control register 0 <SSPn_CTRL0> (0x00) */
#define SSP_SSPEN_DIS 0 //[0:0] SSP enable bit
#define SSP_SSPEN_EN 1
#define mskSSP_SSPEN_DIS (SSP_SSPEN_DIS<<0)
#define mskSSP_SSPEN_EN (SSP_SSPEN_EN<<0)
*/
//[1:1] Loop back mode disable
#define SSP_LOOPBACK_DIS 0 //Disable
#define SSP_LOOPBACK_EN 1 //Data input from data output
#define mskSSP_LOOPBACK_DIS (SSP_LOOPBACK_DIS<<1)
#define mskSSP_LOOPBACK_EN (SSP_LOOPBACK_EN<<1)
/* SPI n Control register 0 <SPIn_CTRL0> (0x00) */
#define SPI_SPIEN_DIS 0 //[0:0] SPI enable bit
#define SPI_SPIEN_EN 1
#define mskSPI_SPIEN_DIS (SPI_SPIEN_DIS<<0)
#define mskSPI_SPIEN_EN (SPI_SPIEN_EN<<0)
//[2:2] Slave data output disable bit (ONLY used in slave mode)
#define SSP_SDODIS_EN 0 //Enable slave data output
#define SSP_SDODIS_DIS 1 //Disable slave data output. (MISO=0)
#define mskSSP_SDODIS_EN (SSP_SDODIS_EN<<2)
#define mskSSP_SDODIS_DIS (SSP_SDODIS_DIS<<2)
//[1:1] Loop back mode disable
#define SPI_LOOPBACK_DIS 0 //Disable
#define SPI_LOOPBACK_EN 1 //Data input from data output
#define mskSPI_LOOPBACK_DIS (SPI_LOOPBACK_DIS<<1)
#define mskSPI_LOOPBACK_EN (SPI_LOOPBACK_EN<<1)
#define SSP_MS_MASTER_MODE 0 //[3:3] Master/Slave selection bit
#define SSP_MS_SLAVE_MODE 1
#define mskSSP_MS_MASTER_MODE (SSP_MS_MASTER_MODE<<3)
#define mskSSP_MS_SLAVE_MODE (SSP_MS_SLAVE_MODE<<3)
//[2:2] Slave data output disable bit (ONLY used in slave mode)
#define SPI_SDODIS_EN 0 //Enable slave data output
#define SPI_SDODIS_DIS 1 //Disable slave data output. (MISO=0)
#define mskSPI_SDODIS_EN (SPI_SDODIS_EN<<2)
#define mskSPI_SDODIS_DIS (SPI_SDODIS_DIS<<2)
#define SSP_FORMAT_SPI_MODE 0 //[4:4] Interface format
#define SSP_FORMAT_SSP_MODE 1
#define mskSSP_FORMAT_SPI_MODE (SSP_FORMAT_SPI_MODE<<4)
#define mskSSP_FORMAT_SSP_MODE (SSP_FORMAT_SSP_MODE<<4)
#define SPI_MS_MASTER_MODE 0 //[3:3] Master/Slave selection bit
#define SPI_MS_SLAVE_MODE 1
#define mskSPI_MS_MASTER_MODE (SPI_MS_MASTER_MODE<<3)
#define mskSPI_MS_SLAVE_MODE (SPI_MS_SLAVE_MODE<<3)
//[7:6] SSP FSM and FIFO Reset bit
#define SSP_FRESET_DO_NOTHING 0 //Do nothing
#define SSP_FRESET_RESET_FIFO 3 //Reset finite state machine and FIFO
#define mskSSP_FRESET_DO_NOTHING (SSP_FRESET_DO_NOTHING<<6)
#define mskSSP_FRESET_RESET_FIFO (SSP_FRESET_RESET_FIFO<<6)
//[7:6] SPI FSM and FIFO Reset bit
#define SPI_FRESET_DO_NOTHING 0 //Do nothing
#define SPI_FRESET_RESET_FIFO 3 //Reset finite state machine and FIFO
#define mskSPI_FRESET_DO_NOTHING (SPI_FRESET_DO_NOTHING<<6)
#define mskSPI_FRESET_RESET_FIFO (SPI_FRESET_RESET_FIFO<<6)
#define SSP_DL_3 2 //[11:8] Data Length = DL[3:0]+1
#define SSP_DL_4 3
#define SSP_DL_5 4
#define SSP_DL_6 5
#define SSP_DL_7 6
#define SSP_DL_8 7
#define SSP_DL_9 8
#define SSP_DL_10 9
#define SSP_DL_11 10
#define SSP_DL_12 11
#define SSP_DL_13 12
#define SSP_DL_14 13
#define SSP_DL_15 14
#define SSP_DL_16 15
#define SPI_DL_3 2 //[11:8] Data Length = DL[3:0]+1
#define SPI_DL_4 3
#define SPI_DL_5 4
#define SPI_DL_6 5
#define SPI_DL_7 6
#define SPI_DL_8 7
#define SPI_DL_9 8
#define SPI_DL_10 9
#define SPI_DL_11 10
#define SPI_DL_12 11
#define SPI_DL_13 12
#define SPI_DL_14 13
#define SPI_DL_15 14
#define SPI_DL_16 15
#define SSP_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level
#define SSP_TXFIFOTH_1 1
#define SSP_TXFIFOTH_2 2
#define SSP_TXFIFOTH_3 3
#define SSP_TXFIFOTH_4 4
#define SSP_TXFIFOTH_5 5
#define SSP_TXFIFOTH_6 6
#define SSP_TXFIFOTH_7 7
#define SPI_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level
#define SPI_TXFIFOTH_1 1
#define SPI_TXFIFOTH_2 2
#define SPI_TXFIFOTH_3 3
#define SPI_TXFIFOTH_4 4
#define SPI_TXFIFOTH_5 5
#define SPI_TXFIFOTH_6 6
#define SPI_TXFIFOTH_7 7
#define SSP_RXFIFOTH_0 0 //[17:15]RX FIFO Threshold level
#define SSP_RXFIFOTH_1 1
#define SSP_RXFIFOTH_2 2
#define SSP_RXFIFOTH_3 3
#define SSP_RXFIFOTH_4 4
#define SSP_RXFIFOTH_5 5
#define SSP_RXFIFOTH_6 6
#define SSP_RXFIFOTH_7 7
#define SPI_RXFIFOTH_0 0 //[17:15]RX FIFO Threshold level
#define SPI_RXFIFOTH_1 1
#define SPI_RXFIFOTH_2 2
#define SPI_RXFIFOTH_3 3
#define SPI_RXFIFOTH_4 4
#define SPI_RXFIFOTH_5 5
#define SPI_RXFIFOTH_6 6
#define SPI_RXFIFOTH_7 7
//[18:18]Auto-SEL disable bit. For SPI mode only.
#define SSP_SELDIS_EN 0 //Enable Auto-SEL flow control
#define SSP_SELDIS_DIS 1 //Disable Auto-SEL flow control
#define mskSSP_SELDIS_EN (SSP_SELDIS_EN<<18)
#define mskSSP_SELDIS_DIS (SSP_SELDIS_DIS<<18)
//[18:18]Auto-SEL disable bit. For SPI mode only.
#define SPI_SELDIS_EN 0 //Enable Auto-SEL flow control
#define SPI_SELDIS_DIS 1 //Disable Auto-SEL flow control
#define mskSPI_SELDIS_EN (SPI_SELDIS_EN<<18)
#define mskSPI_SELDIS_DIS (SPI_SELDIS_DIS<<18)
/* SSP n Control register 1 <SSPn_CTRL1> (0x04) */
//[0:0]MSB/LSB selection bit
#define SSP_MLSB_MSB 0 //MSB transmit first
#define SSP_MLSB_LSB 1 //LSB transmit first
#define mskSSP_MLSB_MSB (SSP_MLSB_MSB<<0)
#define mskSSP_MLSB_LSB (SSP_MLSB_LSB<<0)
/* SPI n Control register 1 <SPIn_CTRL1> (0x04) */
//[0:0]MSB/LSB selection bit
#define SPI_MLSB_MSB 0 //MSB transmit first
#define SPI_MLSB_LSB 1 //LSB transmit first
#define mskSPI_MLSB_MSB (SPI_MLSB_MSB<<0)
#define mskSPI_MLSB_LSB (SPI_MLSB_LSB<<0)
//[1:1]Clock polarity selection bit
#define SSP_CPOL_SCK_IDLE_LOW 0 //SCK idles at Low level
#define SSP_CPOL_SCK_IDLE_HIGH 1 //SCK idles at High level
#define mskSSP_CPOL_SCK_IDLE_LOW (SSP_CPOL_SCK_IDLE_LOW<<1)
#define mskSSP_CPOL_SCK_IDLE_HIGH (SSP_CPOL_SCK_IDLE_HIGH<<1)
//[1:1]Clock polarity selection bit
#define SPI_CPOL_SCK_IDLE_LOW 0 //SCK idles at Low level
#define SPI_CPOL_SCK_IDLE_HIGH 1 //SCK idles at High level
#define mskSPI_CPOL_SCK_IDLE_LOW (SPI_CPOL_SCK_IDLE_LOW<<1)
#define mskSPI_CPOL_SCK_IDLE_HIGH (SPI_CPOL_SCK_IDLE_HIGH<<1)
//[2:2]Clock phase for edge sampling
#define SSP_CPHA_FALLING_EDGE 0 //Data changes at clock falling edge
#define SSP_CPHA_RISING_EDGE 1 //Data changes at clock rising edge
#define mskSSP_CPHA_FALLING_EDGE (SSP_CPHA_FALLING_EDGE<<2)
#define mskSSP_CPHA_RISING_EDGE (SSP_CPHA_RISING_EDGE<<2)
//[2:2]Clock phase for edge sampling
#define SPI_CPHA_FALLING_EDGE 0 //Data changes at clock falling edge
#define SPI_CPHA_RISING_EDGE 1 //Data changes at clock rising edge
#define mskSPI_CPHA_FALLING_EDGE (SPI_CPHA_FALLING_EDGE<<2)
#define mskSPI_CPHA_RISING_EDGE (SPI_CPHA_RISING_EDGE<<2)
/* SSP n Clock Divider register <SSPn_CLKDIV> (0x08) */
//[7:0]SSPn clock divider
#define SSP_DIV 6 //MCLK/n, n = 2, 4, 6, 8, ...,512
/* SPI n Clock Divider register <SPIn_CLKDIV> (0x08) */
//[7:0]SPIn clock divider
#define SPI_DIV 6 //MCLK/n,MCLK=system clk n = 2, 4, 6, 8, ...,512
/* SSP n Status register <SSPn_STAT> (0x0C) */
#define mskSSP_TX_EMPTY (0x1<<0) //TX FIFO empty flag
#define mskSSP_TX_FULL (0x1<<1) //TX FIFO full flag
#define mskSSP_RX_EMPTY (0x1<<2) //RX FIFO empty flag
#define mskSSP_RX_FULL (0x1<<3) //RX FIFO full flag
#define mskSSP_BUSY (0x1<<4) //Busy flag
#define mskSSP_TXFIFOTHF (0x1<<5) //TX FIFO threshold flag
#define mskSSP_RXFIFOTHF (0x1<<6) //RX FIFO threshold flag
/* SPI n Status register <SPIn_STAT> (0x0C) */
#define mskSPI_TX_EMPTY (0x1<<0) //TX FIFO empty flag
#define mskSPI_TX_FULL (0x1<<1) //TX FIFO full flag
#define mskSPI_RX_EMPTY (0x1<<2) //RX FIFO empty flag
#define mskSPI_RX_FULL (0x1<<3) //RX FIFO full flag
#define mskSPI_BUSY (0x1<<4) //Busy flag
#define mskSPI_TXFIFOTHF (0x1<<5) //TX FIFO threshold flag
#define mskSPI_RXFIFOTHF (0x1<<6) //RX FIFO threshold flag
/* SSP n Interrupt Enable register <SSPn_IE> (0x10) */
#define SSP_RXOVFIE_DIS 0 //[0:0]RX Overflow interrupt enable
#define SSP_RXOVFIE_EN 1
#define mskSSP_RXOVFIE_DIS (SSP_RXOVFIE_DIS<<0)
#define mskSSP_RXOVFIE_EN (SSP_RXOVFIE_EN<<0)
/* SPI n Interrupt Enable register <SPIn_IE> (0x10) */
#define SPI_RXOVFIE_DIS 0 //[0:0]RX Overflow interrupt enable
#define SPI_RXOVFIE_EN 1
#define mskSPI_RXOVFIE_DIS (SPI_RXOVFIE_DIS<<0)
#define mskSPI_RXOVFIE_EN (SPI_RXOVFIE_EN<<0)
#define SSP_RXTOIE_DIS 0 //[1:1]RX time-out interrupt enable
#define SSP_RXTOIE_EN 1
#define mskSSP_RXTOIE_DIS (SSP_RXTOIE_DIS<<1)
#define mskSSP_RXTOIE_EN (SSP_RXTOIE_EN<<1)
#define SPI_RXTOIE_DIS 0 //[1:1]RX time-out interrupt enable
#define SPI_RXTOIE_EN 1
#define mskSPI_RXTOIE_DIS (SPI_RXTOIE_DIS<<1)
#define mskSPI_RXTOIE_EN (SPI_RXTOIE_EN<<1)
#define SSP_RXFIFOTHIE_DIS 0 //[2:2]RX FIFO threshold interrupt enable
#define SSP_RXFIFOTHIE_EN 1
#define mskSSP_RXFIFOTHIE_DIS (SSP_RXFIFOTHIE_DIS<<2)
#define mskSSP_RXFIFOTHIE_EN (SSP_RXFIFOTHIE_EN <<2)
#define SPI_RXFIFOTHIE_DIS 0 //[2:2]RX FIFO threshold interrupt enable
#define SPI_RXFIFOTHIE_EN 1
#define mskSPI_RXFIFOTHIE_DIS (SPI_RXFIFOTHIE_DIS<<2)
#define mskSPI_RXFIFOTHIE_EN (SPI_RXFIFOTHIE_EN <<2)
#define SSP_TXFIFOTHIE_DIS 0 //[3:3]TX FIFO threshold interrupt enable
#define SSP_TXFIFOTHIE_EN 1
#define mskSSP_TXFIFOTHIE_DIS (SSP_TXFIFOTHIE_DIS<<3)
#define mskSSP_TXFIFOTHIE_EN (SSP_TXFIFOTHIE_EN<<3)
#define SPI_TXFIFOTHIE_DIS 0 //[3:3]TX FIFO threshold interrupt enable
#define SPI_TXFIFOTHIE_EN 1
#define mskSPI_TXFIFOTHIE_DIS (SPI_TXFIFOTHIE_DIS<<3)
#define mskSPI_TXFIFOTHIE_EN (SPI_TXFIFOTHIE_EN<<3)
/* SSP n Raw Interrupt Status register <SSPn_RIS> (0x14) */
/* SSP n Interrupt Clear register <SSPn_IC> (0x18) */
#define mskSSP_RXOVFIF (0x1<<0) //[0:0]RX overflow interrupt flag
#define mskSSP_RXOVFIC mskSSP_RXOVFIF
/* SPI n Raw Interrupt Status register <SPIn_RIS> (0x14) */
/* SPI n Interrupt Clear register <SPIn_IC> (0x18) */
#define mskSPI_RXOVFIF (0x1<<0) //[0:0]RX overflow interrupt flag
#define mskSPI_RXOVFIC mskSPI_RXOVFIF
#define mskSSP_RXTOIF (0x1<<1) //[1:1]RX time-out interrupt flag
#define mskSSP_RXTOIC mskSSP_RXTOIF
#define mskSPI_RXTOIF (0x1<<1) //[1:1]RX time-out interrupt flag
#define mskSPI_RXTOIC mskSPI_RXTOIF
#define mskSSP_RXFIFOTHIF (0x1<<2) //[2:2]RX FIFO threshold interrupt flag
#define mskSSP_RXFIFOTHIC mskSSP_RXFIFOTHIF
#define mskSPI_RXFIFOTHIF (0x1<<2) //[2:2]RX FIFO threshold interrupt flag
#define mskSPI_RXFIFOTHIC mskSPI_RXFIFOTHIF
#define mskSSP_TXFIFOTHIF (0x1<<3) //[3:3]TX FIFO threshold interrupt flag
#define mskSSP_TXFIFOTHIC mskSSP_TXFIFOTHIF
#define mskSPI_TXFIFOTHIF (0x1<<3) //[3:3]TX FIFO threshold interrupt flag
#define mskSPI_TXFIFOTHIC mskSPI_TXFIFOTHIF
/* SSP n Data Fetch register <SSPn_DF> (0x20) */
//[0:0]SSP data fetch control bit
#define SSP_DF_DIS 0 //Disable
#define SSP_DF_EN 1 //Enable when SCKn frequency > 6MHz
#define mskSSP_DF_DIS (SSP_DF_DIS<<0)
#define mskSSP_SSP_DF_EN (SSP_DF_EN<<0)
/* SPI n Data Fetch register <SPIn_DF> (0x20) */
//[0:0]SPI data fetch control bit
#define SPI_DF_DIS 0 //Disable
#define SPI_DF_EN 1 //Enable when SCKn frequency > 6MHz
#define mskSPI_DF_DIS (SPI_DF_DIS<<0)
#define mskSPI_SPI_DF_EN (SPI_DF_EN<<0)
/*_____ M A C R O S ________________________________________________________*/
#define __SPI0_FIFO_RESET (SN_SSP0->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO)
#define __SPI1_FIFO_RESET (SN_SSP1->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO)
#define __SPI0_CLR_SEL0 (SN_GPIO2->DATA_b.DATA15=0)
#define __SPI0_SET_SEL0 (SN_GPIO2->DATA_b.DATA15=1)
#define __SPI1_CLR_SEL1 (SN_GPIO3->DATA_b.DATA6=0)
#define __SPI1_SET_SEL1 (SN_GPIO3->DATA_b.DATA6=1)
//SSP Data Fetch speed (High: SCK>6MHz)
#define __SSP0_DATA_FETCH_HIGH_SPEED (SN_SSP0->DF = SSP_DF_EN) //*(volatile unsigned long *)(0x4001C020) = 1
#define __SSP1_DATA_FETCH_HIGH_SPEED (SN_SSP1->DF = SSP_DF_EN) //*(volatile unsigned long *)(0x40058020) = 1
#define __SPI0_FIFO_RESET (SN_SPI0->CTRL0_b.FRESET = SPI_FRESET_RESET_FIFO)
#define __SPI1_FIFO_RESET (SN_SPI1->CTRL0_b.FRESET = SPI_FRESET_RESET_FIFO)
#define __SPI0_CLR_SEL0 (SN_GPIO2->DATA_b.DATA9 = 0)
#define __SPI0_SET_SEL0 (SN_GPIO2->DATA_b.DATA9 = 1)
#define __SPI1_CLR_SEL0 (SN_GPIO2->DATA_b.DATA10 = 0)
#define __SPI1_SET_SEL0 (SN_GPIO2->DATA_b.DATA10 = 1)
//SPI Data Fetch speed (High: SCK>6MHz)
#define __SPI0_DATA_FETCH_HIGH_SPEED (SN_SPI0->DFDLY = SPI_DF_EN)
#define __SPI1_DATA_FETCH_HIGH_SPEED (SN_SPI1->DFDLY = SPI_DF_EN)
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern void SPI0_Init(void);
extern void SPI0_Enable(void);
extern void SPI0_Disable(void);
extern void SPI0_Write1(uint8_t data);
extern void SPI0_Write(uint8_t *data, uint8_t len);
extern void SPI0_Write_End(void);
extern void SPI1_Init(void);
extern void SPI1_Enable(void);
extern void SPI1_Disable(void);
#endif /*__SN32F2XX_SSP_H*/
extern void SPI1_Write1(uint8_t data);
extern void SPI1_Write(uint8_t *data, uint8_t len);
extern void SPI1_Write_End(void);
#endif /*__SN32F2xx_SPI_H*/

154
os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI0.c
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@ -1,13 +1,13 @@
/******************** (C) COPYRIGHT 2014 SONiX *******************************
* COMPANY: SONiX
* DATE: 2014/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: SPI0 related functions.
* COMPANY: SONiX
* DATE: 2014/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: SPI0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
* 1.1 2014/05/23 SA1 1. Add __SSP0_DATA_FETCH_HIGH_SPEED macro
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
* 1.1 2014/05/23 SA1 1. Add __SSP0_DATA_FETCH_HIGH_SPEED macro
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -19,7 +19,6 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F2xx.h>
#include "SPI.h"
@ -35,87 +34,100 @@
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : SPI0_Init
* Description : Initialization of SPI0 init
* Input : None
* Output : None
* Return : None
* Note : None
* Function : SPI0_Init
* Description : Initialization of SPI0 init
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI0_Init(void)
{
//Enable HCLK for SSP0
SN_SYS1->AHBCLKEN |= (0x1 << 12); //Enable clock for SSP0.
void SPI0_Init() {
sys1EnableSPI0();
SN_SPI0->CTRL0_b.DL = SPI_DL_8;
//SSP0 PCLK
SN_SYS1->APBCP0 |= (0x00 << 20); //PCLK = HCLK/1
//SN_SYS1->APBCP0 |= (0x01 << 20); //PCLK = HCLK/2
//SN_SYS1->APBCP0 |= (0x02 << 20); //PCLK = HCLK/4
//SN_SYS1->APBCP0 |= (0x03 << 20); //PCLK = HCLK/8
//SN_SYS1->APBCP0 |= (0x04 << 20); //PCLK = HCLK/16
#ifdef SN32_SPI_SLAVE_MODE
SN_SPI0->CTRL0_b.MS = SPI_MS_SLAVE_MODE;
SN_SPI0->CTRL0_b.SDODIS = SPI_SDODIS_EN;
#else
SN_SPI0->CTRL0_b.MS = SPI_MS_MASTER_MODE;
#endif
//SSP0 setting
SN_SSP0->CTRL0_b.DL = SSP_DL_8; //3 ~ 16 Data length
SN_SSP0->CTRL0_b.FORMAT = SSP_FORMAT_SPI_MODE; //Interface format
SN_SSP0->CTRL0_b.MS = SSP_MS_MASTER_MODE; //Master/Slave selection bit
SN_SSP0->CTRL0_b.LOOPBACK = SSP_LOOPBACK_DIS; //Loop back mode
SN_SSP0->CTRL0_b.SDODIS = SSP_SDODIS_EN; //Slave data output
//(ONLY used in slave mode)
SN_SPI0->CTRL0_b.LOOPBACK = SPI_LOOPBACK_DIS;
SN_SSP0->CLKDIV_b.DIV = (SSP_DIV/2) - 1; //SSPn clock divider
#ifdef SN32_SPI_RXFIFO_THRESHOLD
SN_SPI0->CTRL0_b.RXFIFOTH = SN32_SPI_TXFIFO_THRESHOLD;
#endif
//SSP0 SPI mode
SN_SSP0->CTRL1 = SSP_CPHA_FALLING_EDGE| //Clock phase for edge sampling
SSP_CPOL_SCK_IDLE_LOW| //Clock polarity selection bit
SSP_MLSB_MSB; //MSB/LSB selection bit
#ifdef SN32_SPI_TXFIFO_THRESHOLD
SN_SPI0->CTRL0_b.TXFIFOTH = SN32_SPI_TXFIFO_THRESHOLD;
#endif
//SSP0 SEL0 setting
SN_SSP0->CTRL0_b.SELDIS = SSP_SELDIS_DIS; //Auto-SEL disable bit
SN_GPIO2->MODE_b.MODE15=1; //SEL(P2.15) is outout high
__SPI0_SET_SEL0;
#ifdef SN32_SPI_CLKDIV
SN_SPI0->CLKDIV_b.DIV = SN32_SPI_CLKDIV;
#else
SN_SPI0->CLKDIV_b.DIV = (SPI_DIV / 2) - 1;
#endif
//SSP0 Fifo reset
__SPI0_FIFO_RESET;
SN_SPI0->CTRL1_b.CPHA = SPI_CPHA_FALLING_EDGE;
SN_SPI0->CTRL1_b.CPOL = SPI_CPOL_SCK_IDLE_LOW;
SN_SPI0->CTRL1_b.MLSB = SPI_MLSB_MSB;
//SSP0 interrupt disable
NVIC_DisableIRQ(SSP0_IRQn);
#ifdef SN32_SPI_AUTOSEL
SN_SPI0->CTRL0_b.SELDIS = SN32_SPI_AUTOSEL;
#endif
//__SSP0_DATA_FETCH_HIGH_SPEED; //Enable if Freq. of SCK > 6MHz
__SPI0_FIFO_RESET;
//SSP0 enable
SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit
uint32_t spiClock = (SN32_HCLK / ((2 * SN_SPI0->CLKDIV_b.DIV) + 2));
if (spiClock > 6000000) {
__SPI0_DATA_FETCH_HIGH_SPEED;
}
NVIC_DisableIRQ(SN32_SPI0_NUMBER);
}
/*****************************************************************************
* Function : SPI0_Enable
* Description : SPI0 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
* Function : SPI0_Enable
* Description : SPI0 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI0_Enable(void)
{
//Enable HCLK for SSP0
SN_SYS1->AHBCLKEN |= (0x1 << 12); //Enable clock for SSP0.
void SPI0_Enable() {
sys1EnableSPI0();
SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit
__SPI0_FIFO_RESET;
SN_SPI0->CTRL0_b.SPIEN = SPI_SPIEN_EN;
__SPI0_FIFO_RESET;
}
/*****************************************************************************
* Function : SPI0_Disable
* Description : SPI0 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
* Function : SPI0_Disable
* Description : SPI0 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI0_Disable(void)
{
SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_DIS; //SSP disable bit
void SPI0_Disable() {
SN_SPI0->CTRL0_b.SPIEN = SPI_SPIEN_DIS;
//Disable HCLK for SSP0
SN_SYS1->AHBCLKEN &=~ (0x1 << 12); //Disable clock for SSP0.
//Disable HCLK for SSP0
sys1DisableSPI0();
}
void SPI0_Write1(uint8_t data) {
while (SN_SPI0->STAT_b.TX_FULL);
SN_SPI0->DATA = data;
}
void SPI0_Write(uint8_t *data, uint8_t len) {
for (uint8_t i = 0; i < len; i++) {
SPI0_Write1(data[i]);
}
}
void SPI0_Write_End() {
while (!SN_SPI0->STAT_b.TX_EMPTY);
}

153
os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI1.c
View File

@ -1,13 +1,13 @@
/******************** (C) COPYRIGHT 2014 SONiX *******************************
* COMPANY: SONiX
* DATE: 2014/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: SPI1 related functions.
* COMPANY: SONiX
* DATE: 2014/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: SPI1 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
* 1.1 2014/05/23 SA1 1. Add __SSP1_DATA_FETCH_HIGH_SPEED macro
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
* 1.1 2014/05/23 SA1 1. Add __SSP1_DATA_FETCH_HIGH_SPEED macro
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
@ -19,7 +19,6 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F2xx.h>
#include "SPI.h"
@ -35,86 +34,100 @@
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : SPI1_Init
* Description : Initialization of SPI1 init
* Input : None
* Output : None
* Return : None
* Note : None
* Function : SPI1_Init
* Description : Initialization of SPI1 init
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI1_Init(void)
{
//Enable HCLK for SSP1
SN_SYS1->AHBCLKEN |= (0x1 << 13); //Enable clock for SSP1.
void SPI1_Init() {
sys1EnableSPI1();
SN_SPI1->CTRL0_b.DL = SPI_DL_8;
//SSP1 PCLK
SN_SYS1->APBCP0 |= (0x00 << 24); //PCLK = HCLK/1
//SN_SYS1->APBCP0 |= (0x01 << 24); //PCLK = HCLK/2
//SN_SYS1->APBCP0 |= (0x02 << 24); //PCLK = HCLK/4
//SN_SYS1->APBCP0 |= (0x03 << 24); //PCLK = HCLK/8
//SN_SYS1->APBCP0 |= (0x04 << 24); //PCLK = HCLK/16
#ifdef SN32_SPI_SLAVE_MODE
SN_SPI1->CTRL0_b.MS = SPI_MS_SLAVE_MODE;
SN_SPI1->CTRL0_b.SDODIS = SPI_SDODIS_EN;
#else
SN_SPI1->CTRL0_b.MS = SPI_MS_MASTER_MODE;
#endif
//SSP1 setting
SN_SSP1->CTRL0_b.DL = SSP_DL_8; //3 ~ 16 Data length
SN_SSP1->CTRL0_b.FORMAT = SSP_FORMAT_SPI_MODE; //Interface format
SN_SSP1->CTRL0_b.MS = SSP_MS_MASTER_MODE; //Master/Slave selection bit
SN_SSP1->CTRL0_b.LOOPBACK = SSP_LOOPBACK_DIS; //Loop back mode
SN_SSP1->CTRL0_b.SDODIS = SSP_SDODIS_EN; //Slave data output
SN_SPI1->CTRL0_b.LOOPBACK = SPI_LOOPBACK_DIS;
SN_SSP1->CLKDIV_b.DIV = (SSP_DIV/2) - 1; //SSPn clock divider
#ifdef SN32_SPI_RXFIFO_THRESHOLD
SN_SPI1->CTRL0_b.RXFIFOTH = SN32_SPI_TXFIFO_THRESHOLD;
#endif
//SSP1 SPI mode
SN_SSP1->CTRL1 = SSP_CPHA_FALLING_EDGE| //Clock phase for edge sampling
SSP_CPOL_SCK_IDLE_LOW| //Clock polarity selection bit
SSP_MLSB_MSB; //MSB/LSB selection bit
#ifdef SN32_SPI_TXFIFO_THRESHOLD
SN_SPI1->CTRL0_b.TXFIFOTH = SN32_SPI_TXFIFO_THRESHOLD;
#endif
//SSP1 SEL1 Setting
SN_SSP1->CTRL0_b.SELDIS = SSP_SELDIS_DIS; //Auto-SEL disable bit
SN_GPIO3->MODE_b.MODE6=1; //SEL1(P3.6) is outout high
__SPI1_SET_SEL1;
#ifdef SN32_SPI_CLKDIV
SN_SPI1->CLKDIV_b.DIV = SN32_SPI_CLKDIV;
#else
SN_SPI1->CLKDIV_b.DIV = (SPI_DIV / 2) - 1;
#endif
//SSP1 Fifo reset
__SPI1_FIFO_RESET;
SN_SPI1->CTRL1_b.CPHA = SPI_CPHA_FALLING_EDGE;
SN_SPI1->CTRL1_b.CPOL = SPI_CPOL_SCK_IDLE_LOW;
SN_SPI1->CTRL1_b.MLSB = SPI_MLSB_MSB;
//SSP1 interrupt disable
NVIC_DisableIRQ(SSP1_IRQn);
#ifdef SN32_SPI_AUTOSEL
SN_SPI1->CTRL0_b.SELDIS = SN32_SPI_AUTOSEL;
#endif
//__SSP1_DATA_FETCH_HIGH_SPEED; //Enable if Freq. of SCK > 6MHz
__SPI1_FIFO_RESET;
//SSP1 enable
SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit
uint32_t spiClock = (SN32_HCLK / ((2 * SN_SPI1->CLKDIV_b.DIV) + 2));
if (spiClock > 6000000) {
__SPI1_DATA_FETCH_HIGH_SPEED;
}
NVIC_DisableIRQ(SN32_SPI1_NUMBER);
}
/*****************************************************************************
* Function : SPI1_Enable
* Description : SPI1 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
* Function : SPI1_Enable
* Description : SPI1 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI1_Enable(void)
{
//Enable HCLK for SSP1
SN_SYS1->AHBCLKEN |= (0x1 << 13); //Enable clock for SSP0.
void SPI1_Enable() {
sys1EnableSPI1();
SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit
__SPI1_FIFO_RESET;
SN_SPI1->CTRL0_b.SPIEN = SPI_SPIEN_EN;
__SPI1_FIFO_RESET;
}
/*****************************************************************************
* Function : SPI1_Disable
* Description : SPI1 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
* Function : SPI1_Disable
* Description : SPI1 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI1_Disable(void)
{
SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_DIS; //SSP disable bit
void SPI1_Disable() {
SN_SPI1->CTRL0_b.SPIEN = SPI_SPIEN_DIS;
//Disable HCLK for SSP1
SN_SYS1->AHBCLKEN &=~ (0x1 << 13); //Disable clock for SSP0.
//Disable HCLK for SSP1
sys1DisableSPI1();
}
void SPI1_Write1(uint8_t data) {
while (SN_SPI1->STAT_b.TX_FULL);
SN_SPI1->DATA = data;
}
void SPI1_Write(uint8_t *data, uint8_t len) {
for (uint8_t i = 0; i < len; i++) {
SPI1_Write1(data[i]);
}
}
void SPI1_Write_End() {
while (!SN_SPI1->STAT_b.TX_EMPTY);
}

3
os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk Normal file
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@ -0,0 +1,3 @@
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI0.c
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SPI

1
os/hal/ports/SN32/SN32F240B/platform.mk
View File

@ -24,6 +24,7 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk
# Shared variables
ALLCSRC += $(PLATFORMSRC_CONTRIB)

1
os/hal/ports/SN32/SN32F260/platform.mk
View File

@ -24,6 +24,7 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk
# Shared variables
ALLCSRC += $(PLATFORMSRC_CONTRIB)