rusefi
/
ChibiOS-Contrib
mirror of https://github.com/rusefi/ChibiOS-Contrib.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Rename USART registers

This commit is contained in:
Stefan Kerkmann 2021-03-25 21:14:50 +01:00
parent 22b8934b7f
commit 9ddf61ae87
6 changed files with 284 additions and 288 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

92
os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.c
View File

@ -83,7 +83,7 @@ static const SerialConfig default_config =
{
SERIAL_DEFAULT_BITRATE,
0,
USART_CR2_STOP1_BITS,
USART_CTL1_STB1_BITS,
0
};
@ -115,25 +115,25 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
/* Correcting USARTDIV when oversampling by 8 instead of 16.
Fraction is still 4 bits wide, but only lower 3 bits used.
Mantissa is doubled, but Fraction is left the same.*/
#if defined(USART_CR1_OVER8)
if (config->cr1 & USART_CR1_OVER8)
#if defined(USART_CTL0_OVER8)
if (config->ctl0 & USART_CTL0_OVER8)
fck = ((fck & ~7) * 2) | (fck & 7);
#endif
u->BRR = fck;
u->BAUD = fck;
/* Note that some bits are enforced.*/
u->CR2 = config->cr2 | USART_CR2_LBDIE;
u->CR3 = config->cr3 | USART_CR3_EIE;
u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE |
USART_CR1_RXNEIE | USART_CR1_TE |
USART_CR1_RE;
u->SR = 0;
(void)u->SR; /* SR reset step 1.*/
(void)u->DR; /* SR reset step 2.*/
u->CTL1 = config->ctl1 | USART_CTL1_LBDIE;
u->CTL2 = config->ctl2 | USART_CTL2_ERRIE;
u->CTL0 = config->ctl0 | USART_CTL0_UEN | USART_CTL0_PERRIE |
USART_CTL0_RBNEIE | USART_CTL0_TEN |
USART_CTL0_REN;
u->STAT = 0;
(void)u->STAT; /* SR reset step 1.*/
(void)u->DATA; /* SR reset step 2.*/
/* Deciding mask to be applied on the data register on receive, this is
required in order to mask out the parity bit.*/
if ((config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_PCE) {
if ((config->ctl0 & (USART_CTL0_WL | USART_CTL0_PCEN)) == USART_CTL0_PCEN) {
sdp->rxmask = 0x7F;
}
else {
@ -149,27 +149,27 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
*/
static void usart_deinit(USART_TypeDef *u) {
u->CR1 = 0;
u->CR2 = 0;
u->CR3 = 0;
u->CTL0 = 0;
u->CTL1 = 0;
u->CTL2 = 0;
}
/**
* @brief Error handling routine.
*
* @param[in] sdp pointer to a @p SerialDriver object
* @param[in] sr USART SR register value
* @param[in] stat USART STAT register value
*/
static void set_error(SerialDriver *sdp, uint16_t sr) {
static void set_error(SerialDriver *sdp, uint16_t stat) {
eventflags_t sts = 0;
if (sr & USART_SR_ORE)
if (stat & USART_STAT_ORERR)
sts |= SD_OVERRUN_ERROR;
if (sr & USART_SR_PE)
if (stat & USART_STAT_PERR)
sts |= SD_PARITY_ERROR;
if (sr & USART_SR_FE)
if (stat & USART_STAT_FERR)
sts |= SD_FRAMING_ERROR;
if (sr & USART_SR_NE)
if (stat & USART_STAT_NERR)
sts |= SD_NOISE_ERROR;
chnAddFlagsI(sdp, sts);
}
@ -181,53 +181,53 @@ static void set_error(SerialDriver *sdp, uint16_t sr) {
*/
static void serve_interrupt(SerialDriver *sdp) {
USART_TypeDef *u = sdp->usart;
uint16_t cr1 = u->CR1;
uint16_t sr = u->SR;
uint16_t ctl0 = u->CTL0;
uint16_t stat = u->STAT;
/* Special case, LIN break detection.*/
if (sr & USART_SR_LBD) {
if (stat & USART_STAT_LBDF) {
osalSysLockFromISR();
chnAddFlagsI(sdp, SD_BREAK_DETECTED);
u->SR = ~USART_SR_LBD;
u->STAT = ~USART_STAT_LBDF;
osalSysUnlockFromISR();
}
/* Data available.*/
osalSysLockFromISR();
while (sr & (USART_SR_RXNE | USART_SR_ORE | USART_SR_NE | USART_SR_FE |
USART_SR_PE)) {
while (stat & (USART_STAT_RBNE | USART_STAT_ORERR | USART_STAT_NERR | USART_STAT_FERR |
USART_STAT_PERR)) {
uint8_t b;
/* Error condition detection.*/
if (sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE))
set_error(sdp, sr);
b = (uint8_t)u->DR & sdp->rxmask;
if (sr & USART_SR_RXNE)
if (stat & (USART_STAT_ORERR | USART_STAT_NERR | USART_STAT_FERR | USART_STAT_PERR))
set_error(sdp, stat);
b = (uint8_t)u->DATA & sdp->rxmask;
if (stat & USART_STAT_RBNE)
sdIncomingDataI(sdp, b);
sr = u->SR;
stat = u->STAT;
}
osalSysUnlockFromISR();
/* Transmission buffer empty.*/
if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) {
if ((ctl0 & USART_CTL0_TBEIE) && (stat & USART_STAT_TBE)) {
msg_t b;
osalSysLockFromISR();
b = oqGetI(&sdp->oqueue);
if (b < MSG_OK) {
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
u->CR1 = cr1 & ~USART_CR1_TXEIE;
u->CTL0 = ctl0 & ~USART_CTL0_TBEIE;
}
else
u->DR = b;
u->DATA = b;
osalSysUnlockFromISR();
}
/* Physical transmission end.*/
if ((cr1 & USART_CR1_TCIE) && (sr & USART_SR_TC)) {
if ((ctl0 & USART_CTL0_TCIE) && (stat & USART_STAT_TC)) {
osalSysLockFromISR();
if (oqIsEmptyI(&sdp->oqueue)) {
chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
u->CR1 = cr1 & ~USART_CR1_TCIE;
u->CTL0 = ctl0 & ~USART_CTL0_TCIE;
}
osalSysUnlockFromISR();
}
@ -237,7 +237,7 @@ static void serve_interrupt(SerialDriver *sdp) {
static void notify1(io_queue_t *qp) {
(void)qp;
USART1->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
USART1->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif
@ -245,7 +245,7 @@ static void notify1(io_queue_t *qp) {
static void notify2(io_queue_t *qp) {
(void)qp;
USART2->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
USART2->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif
@ -253,7 +253,7 @@ static void notify2(io_queue_t *qp) {
static void notify3(io_queue_t *qp) {
(void)qp;
USART3->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
USART3->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif
@ -261,7 +261,7 @@ static void notify3(io_queue_t *qp) {
static void notify4(io_queue_t *qp) {
(void)qp;
UART4->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
UART4->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif
@ -269,7 +269,7 @@ static void notify4(io_queue_t *qp) {
static void notify5(io_queue_t *qp) {
(void)qp;
UART5->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
UART5->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif
@ -277,7 +277,7 @@ static void notify5(io_queue_t *qp) {
static void notify6(io_queue_t *qp) {
(void)qp;
USART6->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
USART6->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif
@ -285,7 +285,7 @@ static void notify6(io_queue_t *qp) {
static void notify7(io_queue_t *qp) {
(void)qp;
UART7->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
UART7->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif
@ -293,7 +293,7 @@ static void notify7(io_queue_t *qp) {
static void notify8(io_queue_t *qp) {
(void)qp;
UART8->CR1 |= USART_CR1_TXEIE | USART_CR1_TCIE;
UART8->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif

20
os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.h
View File

@ -270,17 +270,17 @@ typedef struct {
uint32_t speed;
/* End of the mandatory fields.*/
/**
* @brief Initialization value for the CR1 register.
* @brief Initialization value for the CTL0 register.
*/
uint16_t cr1;
uint16_t ctl0;
/**
* @brief Initialization value for the CR2 register.
* @brief Initialization value for the CTL1 register.
*/
uint16_t cr2;
uint16_t ctl1;
/**
* @brief Initialization value for the CR3 register.
* @brief Initialization value for the CTL2 register.
*/
uint16_t cr3;
uint16_t ctl2;
} SerialConfig;
/**
@ -311,10 +311,10 @@ typedef struct {
/*
* Extra USARTs definitions here (missing from the ST header file).
*/
#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/
#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/
#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/
#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/
#define USART_CTL1_STB1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/
#define USART_CTL1_STB0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/
#define USART_CTL1_STB2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/
#define USART_CTL1_STB1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/
/*===========================================================================*/
/* External declarations. */

102
os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.c
View File

@ -95,12 +95,12 @@
GD32_UART8_TX_DMA_CHN)
#define GD32_UART45_CR2_CHECK_MASK \
(USART_CR2_STOP_0 | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
USART_CR2_LBCL)
(USART_CTL1_STB_0 | USART_CTL1_CKEN | USART_CTL1_CPL | USART_CTL1_CPH | \
USART_CTL1_CLEN)
#define GD32_UART45_CR3_CHECK_MASK \
(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_SCEN | \
USART_CR3_NACK)
(USART_CTL2_CTSIE | USART_CTL2_CTSEN | USART_CTL2_RTSEN | USART_CTL2_SCEN | \
USART_CTL2_NKEN)
/*===========================================================================*/
/* Driver exported variables. */
@ -157,22 +157,22 @@ UARTDriver UARTD8;
/**
* @brief Status bits translation.
*
* @param[in] sr USART SR register value
* @param[in] stat USART STAT register value
*
* @return The error flags.
*/
static uartflags_t translate_errors(uint16_t sr) {
static uartflags_t translate_errors(uint16_t stat) {
uartflags_t sts = 0;
if (sr & USART_SR_ORE)
if (stat & USART_STAT_ORERR)
sts |= UART_OVERRUN_ERROR;
if (sr & USART_SR_PE)
if (stat & USART_STAT_PERR)
sts |= UART_PARITY_ERROR;
if (sr & USART_SR_FE)
if (stat & USART_STAT_FERR)
sts |= UART_FRAMING_ERROR;
if (sr & USART_SR_NE)
if (stat & USART_STAT_NERR)
sts |= UART_NOISE_ERROR;
if (sr & USART_SR_LBD)
if (stat & USART_STAT_LBDF)
sts |= UART_BREAK_DETECTED;
return sts;
}
@ -210,9 +210,9 @@ static void usart_stop(UARTDriver *uartp) {
dmaStreamDisable(uartp->dmatx);
/* Stops USART operations.*/
uartp->usart->CR1 = 0;
uartp->usart->CR2 = 0;
uartp->usart->CR3 = 0;
uartp->usart->CTL0 = 0;
uartp->usart->CTL1 = 0;
uartp->usart->CTL2 = 0;
}
/**
@ -223,7 +223,7 @@ static void usart_stop(UARTDriver *uartp) {
*/
static void usart_start(UARTDriver *uartp) {
uint32_t fck;
uint16_t cr1;
uint16_t ctl0;
USART_TypeDef *u = uartp->usart;
/* Defensive programming, starting from a clean state.*/
@ -242,27 +242,27 @@ static void usart_start(UARTDriver *uartp) {
/* Correcting USARTDIV when oversampling by 8 instead of 16.
Fraction is still 4 bits wide, but only lower 3 bits used.
Mantissa is doubled, but Fraction is left the same.*/
#if defined(USART_CR1_OVER8)
if (uartp->config->cr1 & USART_CR1_OVER8)
#if defined(USART_CTL0_OVER8)
if (uartp->config->ctl0 & USART_CTL0_OVER8)
fck = ((fck & ~7) * 2) | (fck & 7);
#endif
u->BRR = fck;
u->BAUD = fck;
/* Resetting eventual pending status flags.*/
(void)u->SR; /* SR reset step 1.*/
(void)u->DR; /* SR reset step 2.*/
u->SR = 0;
(void)u->STAT; /* SR reset step 1.*/
(void)u->DATA; /* SR reset step 2.*/
u->STAT = 0;
/* Note that some bits are enforced because required for correct driver
operations.*/
u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
USART_CR3_EIE;
u->CTL1 = uartp->config->ctl1 | USART_CTL1_LBDIE;
u->CTL2 = uartp->config->ctl2 | USART_CTL2_DENT | USART_CTL2_DENR |
USART_CTL2_ERRIE;
/* Mustn't ever set TCIE here - if done, it causes an immediate
interrupt.*/
cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
u->CR1 = uartp->config->cr1 | cr1;
ctl0 = USART_CTL0_UEN | USART_CTL0_PERRIE | USART_CTL0_TEN | USART_CTL0_REN;
u->CTL0 = uartp->config->ctl0 | ctl0;
/* Starting the receiver idle loop.*/
uart_enter_rx_idle_loop(uartp);
@ -327,30 +327,30 @@ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
* @param[in] uartp pointer to the @p UARTDriver object
*/
static void serve_usart_irq(UARTDriver *uartp) {
uint16_t sr;
uint16_t stat;
USART_TypeDef *u = uartp->usart;
uint32_t cr1 = u->CR1;
uint32_t ctl0 = u->CTL0;
sr = u->SR; /* SR reset step 1.*/
(void)u->DR; /* SR reset step 2.*/
stat = u->STAT; /* SR reset step 1.*/
(void)u->DATA; /* SR reset step 2.*/
if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE |
USART_SR_FE | USART_SR_PE)) {
u->SR = ~USART_SR_LBD;
_uart_rx_error_isr_code(uartp, translate_errors(sr));
if (stat & (USART_STAT_LBDF | USART_STAT_ORERR | USART_STAT_NERR |
USART_STAT_FERR | USART_STAT_PERR)) {
u->STAT = ~USART_STAT_LBDF;
_uart_rx_error_isr_code(uartp, translate_errors(stat));
}
if ((sr & USART_SR_TC) && (cr1 & USART_CR1_TCIE)) {
if ((stat & USART_STAT_TC) && (ctl0 & USART_CTL0_TCIE)) {
/* TC interrupt cleared and disabled.*/
u->SR = ~USART_SR_TC;
u->CR1 = cr1 & ~USART_CR1_TCIE;
u->STAT = ~USART_STAT_TC;
u->CTL0 = ctl0 & ~USART_CTL0_TCIE;
/* End of transmission, a callback is generated.*/
_uart_tx2_isr_code(uartp);
}
/* Timeout interrupt sources are only checked if enabled in CR1.*/
if ((cr1 & USART_CR1_IDLEIE) && (sr & USART_SR_IDLE)) {
if ((ctl0 & USART_CTL0_IDLEIE) && (stat & USART_STAT_IDLEF)) {
_uart_timeout_isr_code(uartp);
}
}
@ -674,9 +674,9 @@ void uart_lld_start(UARTDriver *uartp) {
#if GD32_UART_USE_UART4
if (&UARTD4 == uartp) {
osalDbgAssert((uartp->config->cr2 & GD32_UART45_CR2_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->ctl1 & GD32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART4 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & GD32_UART45_CR3_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->ctl2 & GD32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART4 CR3 register settings");
uartp->dmarx = dmaStreamAllocI(GD32_UART_UART4_RX_DMA_STREAM,
@ -702,9 +702,9 @@ void uart_lld_start(UARTDriver *uartp) {
#if GD32_UART_USE_UART5
if (&UARTD5 == uartp) {
osalDbgAssert((uartp->config->cr2 & GD32_UART45_CR2_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->ctl1 & GD32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART5 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & GD32_UART45_CR3_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->ctl2 & GD32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART5 CR3 register settings");
uartp->dmarx = dmaStreamAllocI(GD32_UART_UART5_RX_DMA_STREAM,
@ -752,9 +752,9 @@ void uart_lld_start(UARTDriver *uartp) {
#if GD32_UART_USE_UART7
if (&UARTD7 == uartp) {
osalDbgAssert((uartp->config->cr2 & GD32_UART45_CR2_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->ctl1 & GD32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART7 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & GD32_UART45_CR3_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->ctl2 & GD32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART7 CR3 register settings");
uartp->dmarx = dmaStreamAllocI(GD32_UART_UART7_RX_DMA_STREAM,
@ -780,9 +780,9 @@ void uart_lld_start(UARTDriver *uartp) {
#if GD32_UART_USE_UART8
if (&UARTD8 == uartp) {
osalDbgAssert((uartp->config->cr2 & GD32_UART45_CR2_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->ctl1 & GD32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART8 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & GD32_UART45_CR3_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->ctl2 & GD32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART8 CR3 register settings");
uartp->dmarx = dmaStreamAllocI(GD32_UART_UART8_RX_DMA_STREAM,
@ -807,12 +807,12 @@ void uart_lld_start(UARTDriver *uartp) {
/* Static DMA setup, the transfer size depends on the USART settings,
it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) {
if ((uartp->config->ctl0 & (USART_CTL0_WL | USART_CTL0_PCEN)) == USART_CTL0_WL) {
uartp->dmarxmode |= GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
uartp->dmatxmode |= GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
}
dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR);
dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR);
dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DATA);
dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DATA);
uartp->rxbuf = 0;
}
@ -930,8 +930,8 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
#else
if (uartp->config->txend2_cb != NULL) {
#endif
uartp->usart->SR = ~USART_SR_TC;
uartp->usart->CR1 |= USART_CR1_TCIE;
uartp->usart->STAT = ~USART_STAT_TC;
uartp->usart->CTL0 |= USART_CTL0_TCIE;
}
/* Starting transfer.*/

12
os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.h
View File

@ -614,17 +614,17 @@ typedef struct {
*/
uint32_t speed;
/**
* @brief Initialization value for the CR1 register.
* @brief Initialization value for the CTL0 register.
*/
uint16_t cr1;
uint16_t ctl0;
/**
* @brief Initialization value for the CR2 register.
* @brief Initialization value for the CTL1 register.
*/
uint16_t cr2;
uint16_t ctl1;
/**
* @brief Initialization value for the CR3 register.
* @brief Initialization value for the CTL2 register.
*/
uint16_t cr3;
uint16_t ctl2;
} UARTConfig;
/**

4
os/hal/ports/GD/GD32VF103/gd32_registry.h
View File

@ -114,10 +114,6 @@
#define GD32_DAC_DAC1_CH2_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
/* DMA attributes.*/
#define GD32_ADVANCED_DMA FALSE
#define GD32_DMA_SUPPORTS_DMAMUX FALSE
#define GD32_DMA_SUPPORTS_CSELR FALSE
#define GD32_DMA0_NUM_CHANNELS 7
#define GD32_DMA0_CH0_HANDLER vector30
#define GD32_DMA0_CH1_HANDLER vector31

342
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -540,13 +540,13 @@ typedef struct
typedef struct
{
__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
__IO uint32_t STAT; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DATA; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BAUD; /*!< USART Baud rate register, Address offset: 0x08 */
__IO uint32_t CTL0; /*!< USART Control register 1, Address offset: 0x0C */
__IO uint32_t CTL1; /*!< USART Control register 2, Address offset: 0x10 */
__IO uint32_t CTL2; /*!< USART Control register 3, Address offset: 0x14 */
__IO uint32_t GP; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;
@ -12101,179 +12101,179 @@ typedef struct
/* */
/******************************************************************************/
/******************* Bit definition for USART_SR register *******************/
#define USART_SR_PE_Pos (0U)
#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
#define USART_SR_FE_Pos (1U)
#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
#define USART_SR_NE_Pos (2U)
#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
#define USART_SR_ORE_Pos (3U)
#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
#define USART_SR_IDLE_Pos (4U)
#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
#define USART_SR_RXNE_Pos (5U)
#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_SR_TC_Pos (6U)
#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
#define USART_SR_TXE_Pos (7U)
#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_SR_LBD_Pos (8U)
#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
#define USART_SR_CTS_Pos (9U)
#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
/******************* Bit definition for USART_STAT register *******************/
#define USART_STAT_PERR_Pos (0U)
#define USART_STAT_PERR_Msk (0x1U << USART_STAT_PERR_Pos) /*!< 0x00000001 */
#define USART_STAT_PERR USART_STAT_PERR_Msk /*!< Parity Error */
#define USART_STAT_FERR_Pos (1U)
#define USART_STAT_FERR_Msk (0x1U << USART_STAT_FERR_Pos) /*!< 0x00000002 */
#define USART_STAT_FERR USART_STAT_FERR_Msk /*!< Framing Error */
#define USART_STAT_NERR_Pos (2U)
#define USART_STAT_NERR_Msk (0x1U << USART_STAT_NERR_Pos) /*!< 0x00000004 */
#define USART_STAT_NERR USART_STAT_NERR_Msk /*!< Noise Error Flag */
#define USART_STAT_ORERR_Pos (3U)
#define USART_STAT_ORERR_Msk (0x1U << USART_STAT_ORERR_Pos) /*!< 0x00000008 */
#define USART_STAT_ORERR USART_STAT_ORERR_Msk /*!< OverRun Error */
#define USART_STAT_IDLEF_Pos (4U)
#define USART_STAT_IDLEF_Msk (0x1U << USART_STAT_IDLEF_Pos) /*!< 0x00000010 */
#define USART_STAT_IDLEF USART_STAT_IDLEF_Msk /*!< IDLE line detected */
#define USART_STAT_RBNE_Pos (5U)
#define USART_STAT_RBNE_Msk (0x1U << USART_STAT_RBNE_Pos) /*!< 0x00000020 */
#define USART_STAT_RBNE USART_STAT_RBNE_Msk /*!< Read Data Register Not Empty */
#define USART_STAT_TC_Pos (6U)
#define USART_STAT_TC_Msk (0x1U << USART_STAT_TC_Pos) /*!< 0x00000040 */
#define USART_STAT_TC USART_STAT_TC_Msk /*!< Transmission Complete */
#define USART_STAT_TBE_Pos (7U)
#define USART_STAT_TBE_Msk (0x1U << USART_STAT_TBE_Pos) /*!< 0x00000080 */
#define USART_STAT_TBE USART_STAT_TBE_Msk /*!< Transmit Data Register Empty */
#define USART_STAT_LBDF_Pos (8U)
#define USART_STAT_LBDF_Msk (0x1U << USART_STAT_LBDF_Pos) /*!< 0x00000100 */
#define USART_STAT_LBDF USART_STAT_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_STAT_CTSF_Pos (9U)
#define USART_STAT_CTSF_Msk (0x1U << USART_STAT_CTSF_Pos) /*!< 0x00000200 */
#define USART_STAT_CTSF USART_STAT_CTSF_Msk /*!< CTS Flag */
/******************* Bit definition for USART_DR register *******************/
#define USART_DR_DR_Pos (0U)
#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/******************* Bit definition for USART_DATA register *******************/
#define USART_DATA_DATA_Pos (0U)
#define USART_DATA_DATA_Msk (0x1FFU << USART_DATA_DATA_Pos) /*!< 0x000001FF */
#define USART_DATA_DATA USART_DATA_DATA_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_Fraction_Pos (0U)
#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
#define USART_BRR_DIV_Mantissa_Pos (4U)
#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
/****************** Bit definition for USART_BAUD register *******************/
#define USART_BAUD_FRADIV_Pos (0U)
#define USART_BAUD_FRADIV_Msk (0xFU << USART_BAUD_FRADIV_Pos) /*!< 0x0000000F */
#define USART_BAUD_FRADIV USART_BAUD_FRADIV_Msk /*!< Fraction of USARTDIV */
#define USART_BAUD_INTDIV_Pos (4U)
#define USART_BAUD_INTDIV_Msk (0xFFFU << USART_BAUD_INTDIV_Pos) /*!< 0x0000FFF0 */
#define USART_BAUD_INTDIV USART_BAUD_INTDIV_Msk /*!< Mantissa of USARTDIV */
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
#define USART_CR1_RWU_Pos (1U)
#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_UE_Pos (13U)
#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
/****************** Bit definition for USART_CTL0 register *******************/
#define USART_CTL0_SBKCMD_Pos (0U)
#define USART_CTL0_SBKCMD_Msk (0x1U << USART_CTL0_SBKCMD_Pos) /*!< 0x00000001 */
#define USART_CTL0_SBKCMD USART_CTL0_SBKCMD_Msk /*!< Send Break */
#define USART_CTL0_RWU_Pos (1U)
#define USART_CTL0_RWU_Msk (0x1U << USART_CTL0_RWU_Pos) /*!< 0x00000002 */
#define USART_CTL0_RWU USART_CTL0_RWU_Msk /*!< Receiver wakeup */
#define USART_CTL0_REN_Pos (2U)
#define USART_CTL0_REN_Msk (0x1U << USART_CTL0_REN_Pos) /*!< 0x00000004 */
#define USART_CTL0_REN USART_CTL0_REN_Msk /*!< Receiver Enable */
#define USART_CTL0_TEN_Pos (3U)
#define USART_CTL0_TEN_Msk (0x1U << USART_CTL0_TEN_Pos) /*!< 0x00000008 */
#define USART_CTL0_TEN USART_CTL0_TEN_Msk /*!< Transmitter Enable */
#define USART_CTL0_IDLEIE_Pos (4U)
#define USART_CTL0_IDLEIE_Msk (0x1U << USART_CTL0_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CTL0_IDLEIE USART_CTL0_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CTL0_RBNEIE_Pos (5U)
#define USART_CTL0_RBNEIE_Msk (0x1U << USART_CTL0_RBNEIE_Pos) /*!< 0x00000020 */
#define USART_CTL0_RBNEIE USART_CTL0_RBNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CTL0_TCIE_Pos (6U)
#define USART_CTL0_TCIE_Msk (0x1U << USART_CTL0_TCIE_Pos) /*!< 0x00000040 */
#define USART_CTL0_TCIE USART_CTL0_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CTL0_TBEIE_Pos (7U)
#define USART_CTL0_TBEIE_Msk (0x1U << USART_CTL0_TBEIE_Pos) /*!< 0x00000080 */
#define USART_CTL0_TBEIE USART_CTL0_TBEIE_Msk /*!< PE Interrupt Enable */
#define USART_CTL0_PERRIE_Pos (8U)
#define USART_CTL0_PERRIE_Msk (0x1U << USART_CTL0_PERRIE_Pos) /*!< 0x00000100 */
#define USART_CTL0_PERRIE USART_CTL0_PERRIE_Msk /*!< PE Interrupt Enable */
#define USART_CTL0_PM_Pos (9U)
#define USART_CTL0_PM_Msk (0x1U << USART_CTL0_PM_Pos) /*!< 0x00000200 */
#define USART_CTL0_PM USART_CTL0_PM_Msk /*!< Parity Selection */
#define USART_CTL0_PCEN_Pos (10U)
#define USART_CTL0_PCEN_Msk (0x1U << USART_CTL0_PCEN_Pos) /*!< 0x00000400 */
#define USART_CTL0_PCEN USART_CTL0_PCEN_Msk /*!< Parity Control Enable */
#define USART_CTL0_WM_Pos (11U)
#define USART_CTL0_WM_Msk (0x1U << USART_CTL0_WM_Pos) /*!< 0x00000800 */
#define USART_CTL0_WM USART_CTL0_WM_Msk /*!< Wakeup method */
#define USART_CTL0_WL_Pos (12U)
#define USART_CTL0_WL_Msk (0x1U << USART_CTL0_WL_Pos) /*!< 0x00001000 */
#define USART_CTL0_WL USART_CTL0_WL_Msk /*!< Word length */
#define USART_CTL0_UEN_Pos (13U)
#define USART_CTL0_UEN_Msk (0x1U << USART_CTL0_UEN_Pos) /*!< 0x00002000 */
#define USART_CTL0_UEN USART_CTL0_UEN_Msk /*!< USART Enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_ADD_Pos (0U)
#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
/****************** Bit definition for USART_CTL1 register *******************/
#define USART_CTL1_ADDR_Pos (0U)
#define USART_CTL1_ADDR_Msk (0xFU << USART_CTL1_ADDR_Pos) /*!< 0x0000000F */
#define USART_CTL1_ADDR USART_CTL1_ADDR_Msk /*!< Address of the USART node */
#define USART_CTL1_LBLEN_Pos (5U)
#define USART_CTL1_LBLEN_Msk (0x1U << USART_CTL1_LBLEN_Pos) /*!< 0x00000020 */
#define USART_CTL1_LBLEN USART_CTL1_LBLEN_Msk /*!< LIN Break Detection Length */
#define USART_CTL1_LBDIE_Pos (6U)
#define USART_CTL1_LBDIE_Msk (0x1U << USART_CTL1_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CTL1_LBDIE USART_CTL1_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CTL1_CLEN_Pos (8U)
#define USART_CTL1_CLEN_Msk (0x1U << USART_CTL1_CLEN_Pos) /*!< 0x00000100 */
#define USART_CTL1_CLEN USART_CTL1_CLEN_Msk /*!< Last Bit Clock pulse */
#define USART_CTL1_CPH_Pos (9U)
#define USART_CTL1_CPH_Msk (0x1U << USART_CTL1_CPH_Pos) /*!< 0x00000200 */
#define USART_CTL1_CPH USART_CTL1_CPH_Msk /*!< Clock Phase */
#define USART_CTL1_CPL_Pos (10U)
#define USART_CTL1_CPL_Msk (0x1U << USART_CTL1_CPL_Pos) /*!< 0x00000400 */
#define USART_CTL1_CPL USART_CTL1_CPL_Msk /*!< Clock Polarity */
#define USART_CTL1_CKEN_Pos (11U)
#define USART_CTL1_CKEN_Msk (0x1U << USART_CTL1_CKEN_Pos) /*!< 0x00000800 */
#define USART_CTL1_CKEN USART_CTL1_CKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CTL1_STB_Pos (12U)
#define USART_CTL1_STB_Msk (0x3U << USART_CTL1_STB_Pos) /*!< 0x00003000 */
#define USART_CTL1_STB USART_CTL1_STB_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CTL1_STB_0 (0x1U << USART_CTL1_STB_Pos) /*!< 0x00001000 */
#define USART_CTL1_STB_1 (0x2U << USART_CTL1_STB_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CTL1_LMEN_Pos (14U)
#define USART_CTL1_LMEN_Msk (0x1U << USART_CTL1_LMEN_Pos) /*!< 0x00004000 */
#define USART_CTL1_LMEN USART_CTL1_LMEN_Msk /*!< LIN mode enable */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
/****************** Bit definition for USART_CTL2 register *******************/
#define USART_CTL2_ERRIE_Pos (0U)
#define USART_CTL2_ERRIE_Msk (0x1U << USART_CTL2_ERRIE_Pos) /*!< 0x00000001 */
#define USART_CTL2_ERRIE USART_CTL2_ERRIE_Msk /*!< Error Interrupt Enable */
#define USART_CTL2_IREN_Pos (1U)
#define USART_CTL2_IREN_Msk (0x1U << USART_CTL2_IREN_Pos) /*!< 0x00000002 */
#define USART_CTL2_IREN USART_CTL2_IREN_Msk /*!< IrDA mode Enable */
#define USART_CTL2_IRLP_Pos (2U)
#define USART_CTL2_IRLP_Msk (0x1U << USART_CTL2_IRLP_Pos) /*!< 0x00000004 */
#define USART_CTL2_IRLP USART_CTL2_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CTL2_HDEN_Pos (3U)
#define USART_CTL2_HDEN_Msk (0x1U << USART_CTL2_HDEN_Pos) /*!< 0x00000008 */
#define USART_CTL2_HDEN USART_CTL2_HDEN_Msk /*!< Half-Duplex Selection */
#define USART_CTL2_NKEN_Pos (4U)
#define USART_CTL2_NKEN_Msk (0x1U << USART_CTL2_NKEN_Pos) /*!< 0x00000010 */
#define USART_CTL2_NKEN USART_CTL2_NKEN_Msk /*!< Smartcard NACK enable */
#define USART_CTL2_SCEN_Pos (5U)
#define USART_CTL2_SCEN_Msk (0x1U << USART_CTL2_SCEN_Pos) /*!< 0x00000020 */
#define USART_CTL2_SCEN USART_CTL2_SCEN_Msk /*!< Smartcard mode enable */
#define USART_CTL2_DENR_Pos (6U)
#define USART_CTL2_DENR_Msk (0x1U << USART_CTL2_DENR_Pos) /*!< 0x00000040 */
#define USART_CTL2_DENR USART_CTL2_DENR_Msk /*!< DMA Enable Receiver */
#define USART_CTL2_DENT_Pos (7U)
#define USART_CTL2_DENT_Msk (0x1U << USART_CTL2_DENT_Pos) /*!< 0x00000080 */
#define USART_CTL2_DENT USART_CTL2_DENT_Msk /*!< DMA Enable Transmitter */
#define USART_CTL2_RTSEN_Pos (8U)
#define USART_CTL2_RTSEN_Msk (0x1U << USART_CTL2_RTSEN_Pos) /*!< 0x00000100 */
#define USART_CTL2_RTSEN USART_CTL2_RTSEN_Msk /*!< RTS Enable */
#define USART_CTL2_CTSEN_Pos (9U)
#define USART_CTL2_CTSEN_Msk (0x1U << USART_CTL2_CTSEN_Pos) /*!< 0x00000200 */
#define USART_CTL2_CTSEN USART_CTL2_CTSEN_Msk /*!< CTS Enable */
#define USART_CTL2_CTSIE_Pos (10U)
#define USART_CTL2_CTSIE_Msk (0x1U << USART_CTL2_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CTL2_CTSIE USART_CTL2_CTSIE_Msk /*!< CTS Interrupt Enable */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
/****************** Bit definition for USART_GP register ******************/
#define USART_GP_PSC_Pos (0U)
#define USART_GP_PSC_Msk (0xFFU << USART_GP_PSC_Pos) /*!< 0x000000FF */
#define USART_GP_PSC USART_GP_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GP_PSC_0 (0x01U << USART_GP_PSC_Pos) /*!< 0x00000001 */
#define USART_GP_PSC_1 (0x02U << USART_GP_PSC_Pos) /*!< 0x00000002 */
#define USART_GP_PSC_2 (0x04U << USART_GP_PSC_Pos) /*!< 0x00000004 */
#define USART_GP_PSC_3 (0x08U << USART_GP_PSC_Pos) /*!< 0x00000008 */
#define USART_GP_PSC_4 (0x10U << USART_GP_PSC_Pos) /*!< 0x00000010 */
#define USART_GP_PSC_5 (0x20U << USART_GP_PSC_Pos) /*!< 0x00000020 */
#define USART_GP_PSC_6 (0x40U << USART_GP_PSC_Pos) /*!< 0x00000040 */
#define USART_GP_PSC_7 (0x80U << USART_GP_PSC_Pos) /*!< 0x00000080 */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
#define USART_GP_GUAT_Pos (8U)
#define USART_GP_GUAT_Msk (0xFFU << USART_GP_GUAT_Pos) /*!< 0x0000FF00 */
#define USART_GP_GUAT USART_GP_GUAT_Msk /*!< Guard time value */
/******************************************************************************/
/* */