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Rename Independent Watchdog registers

This commit is contained in:
Stefan Kerkmann 2021-03-29 21:15:03 +02:00
parent 4f93d001a4
commit a421b9821b
4 changed files with 79 additions and 102 deletions
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5
os/hal/ports/GD/GD32VF103/gd32_registry.h
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@ -307,9 +307,8 @@
#define GD32_HAS_USB TRUE
/* IWDG attributes.*/
#define GD32_HAS_IWDG TRUE
#define GD32_IWDG_IS_WINDOWED FALSE
/* FWDGT attributes.*/
#define GD32_HAS_FWDGT TRUE
/* FSMC attributes.*/
#if GD32_HAS_EXMC

66
os/hal/ports/GD/GD32VF103/stm32f105xc.h
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@ -404,11 +404,11 @@ typedef struct
typedef struct
{
__IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
} IWDG_TypeDef;
__IO uint32_t CTL; /*!< Key register, Address offset: 0x00 */
__IO uint32_t PSC; /*!< Prescaler register, Address offset: 0x04 */
__IO uint32_t RLD; /*!< Reload register, Address offset: 0x08 */
__IO uint32_t STAT; /*!< Status register, Address offset: 0x0C */
} FWDGT_TypeDef;
/**
* @brief Power Control
@ -679,7 +679,7 @@ typedef struct
#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
//#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
#define FWDGT_BASE (APB1PERIPH_BASE + 0x00003000U)
#define SPI1_BASE (APB1PERIPH_BASE + 0x00003800U)
#define SPI2_BASE (APB1PERIPH_BASE + 0x00003C00U)
#define USART1_BASE (APB1PERIPH_BASE + 0x00004400U)
@ -767,7 +767,7 @@ typedef struct
#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
#define RTC ((RTC_TypeDef *)RTC_BASE)
#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
#define FWDGT ((FWDGT_TypeDef *)FWDGT_BASE)
#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
#define USART1 ((USART_TypeDef *)USART1_BASE)
@ -1774,9 +1774,9 @@ typedef struct
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
#define RCC_CSR_FWDGTRSTF_Pos (29U)
#define RCC_CSR_FWDGTRSTF_Msk (0x1U << RCC_CSR_FWDGTRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_FWDGTRSTF RCC_CSR_FWDGTRSTF_Msk /*!< Independent Watchdog reset flag */
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
@ -5172,35 +5172,35 @@ typedef struct
/******************************************************************************/
/* */
/* Independent WATCHDOG (IWDG) */
/* FREE WATCHDOG TIMER (FWDGT) */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
/******************* Bit definition for FWDGT_CTL register ********************/
#define FWDGT_CTL_CMD_Pos (0U)
#define FWDGT_CTL_CMD_Msk (0xFFFFU << FWDGT_CTL_CMD_Pos) /*!< 0x0000FFFF */
#define FWDGT_CTL_CMD FWDGT_CTL_CMD_Msk /*!< Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
/******************* Bit definition for FWDGT_PSC register ********************/
#define FWDGT_PSC_PSC_Pos (0U)
#define FWDGT_PSC_PSC_Msk (0x7U << FWDGT_PSC_PSC_Pos) /*!< 0x00000007 */
#define FWDGT_PSC_PSC FWDGT_PSC_PSC_Msk /*!< PR[2:0] (Prescaler divider) */
#define FWDGT_PSC_PSC_0 (0x1U << FWDGT_PSC_PSC_Pos) /*!< 0x00000001 */
#define FWDGT_PSC_PSC_1 (0x2U << FWDGT_PSC_PSC_Pos) /*!< 0x00000002 */
#define FWDGT_PSC_PSC_2 (0x4U << FWDGT_PSC_PSC_Pos) /*!< 0x00000004 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
/******************* Bit definition for FWDGT_RLD register *******************/
#define FWDGT_RLD_RLD_Pos (0U)
#define FWDGT_RLD_RLD_Msk (0xFFFU << FWDGT_RLD_RLD_Pos) /*!< 0x00000FFF */
#define FWDGT_RLD_RLD FWDGT_RLD_RLD_Msk /*!< Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
/******************* Bit definition for FWDGT_STAT register ********************/
#define FWDGT_STAT_PUD_Pos (0U)
#define FWDGT_STAT_PUD_Msk (0x1U << FWDGT_STAT_PUD_Pos) /*!< 0x00000001 */
#define FWDGT_STAT_PUD FWDGT_STAT_PUD_Msk /*!< Watchdog prescaler value update */
#define FWDGT_STAT_RUD_Pos (1U)
#define FWDGT_STAT_RUD_Msk (0x1U << FWDGT_STAT_RUD_Pos) /*!< 0x00000002 */
#define FWDGT_STAT_RUD FWDGT_STAT_RUD_Msk /*!< Watchdog counter reload value update */
/******************************************************************************/
/* */

41
os/hal/ports/GD/GD32VF103/xWDG/hal_wdg_lld.c
View File

@ -30,20 +30,20 @@
/* Driver local definitions. */
/*===========================================================================*/
#define KR_KEY_RELOAD 0xAAAAU
#define KR_KEY_ENABLE 0xCCCCU
#define KR_KEY_WRITE 0x5555U
#define KR_KEY_PROTECT 0x0000U
#define CTL_CMD_RELOAD 0xAAAAU
#define CTL_CMD_ENABLE 0xCCCCU
#define CTL_CMD_WRITE 0x5555U
#define CTL_CMD_PROTECT 0x0000U
#if !defined(IWDG) && defined(IWDG1)
#define IWDG IWDG1
#if !defined(FWDGT) && defined(FWDGT1)
#define FWDGT FWDGT1
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
#if GD32_WDG_USE_IWDG || defined(__DOXYGEN__)
#if GD32_WDG_USE_FWDGT || defined(__DOXYGEN__)
WDGDriver WDGD1;
#endif
@ -70,9 +70,9 @@ WDGDriver WDGD1;
*/
void wdg_lld_init(void) {
#if GD32_WDG_USE_IWDG
#if GD32_WDG_USE_FWDGT
WDGD1.state = WDG_STOP;
WDGD1.wdg = IWDG;
WDGD1.wdg = FWDGT;
#endif
}
@ -85,24 +85,19 @@ void wdg_lld_init(void) {
*/
void wdg_lld_start(WDGDriver *wdgp) {
/* Enable IWDG and unlock for write.*/
wdgp->wdg->KR = KR_KEY_ENABLE;
wdgp->wdg->KR = KR_KEY_WRITE;
/* Enable FWDGT and unlock for write.*/
wdgp->wdg->CTL = CTL_CMD_ENABLE;
wdgp->wdg->CTL = CTL_CMD_WRITE;
/* Write configuration.*/
wdgp->wdg->PR = wdgp->config->pr;
wdgp->wdg->RLR = wdgp->config->rlr;
wdgp->wdg->PSC = wdgp->config->psc;
wdgp->wdg->RLD = wdgp->config->rld;
/* Wait the registers to be updated.*/
while (wdgp->wdg->SR != 0)
while (wdgp->wdg->STAT != 0)
;
#if GD32_IWDG_IS_WINDOWED
/* This also triggers a refresh.*/
wdgp->wdg->WINR = wdgp->config->winr;
#else
wdgp->wdg->KR = KR_KEY_RELOAD;
#endif
wdgp->wdg->CTL = CTL_CMD_RELOAD;
}
/**
@ -115,7 +110,7 @@ void wdg_lld_start(WDGDriver *wdgp) {
void wdg_lld_stop(WDGDriver *wdgp) {
osalDbgAssert(wdgp->state == WDG_STOP,
"IWDG cannot be stopped once activated");
"FWDGT cannot be stopped once activated");
}
/**
@ -127,7 +122,7 @@ void wdg_lld_stop(WDGDriver *wdgp) {
*/
void wdg_lld_reset(WDGDriver * wdgp) {
wdgp->wdg->KR = KR_KEY_RELOAD;
wdgp->wdg->CTL = CTL_CMD_RELOAD;
}
#endif /* HAL_USE_WDG == TRUE */

69
os/hal/ports/GD/GD32VF103/xWDG/hal_wdg_lld.h
View File

@ -35,31 +35,22 @@
* @name RLR register definitions
* @{
*/
#define GD32_IWDG_RL_MASK (0x00000FFF << 0)
#define GD32_IWDG_RL(n) ((n) << 0)
#define GD32_FWDGT_RLD_MASK (0x00000FFF << 0)
#define GD32_FWDGT_RLD(n) ((n) << 0)
/** @} */
/**
* @name PR register definitions
* @{
*/
#define GD32_IWDG_PR_MASK (7 << 0)
#define GD32_IWDG_PR_4 0U
#define GD32_IWDG_PR_8 1U
#define GD32_IWDG_PR_16 2U
#define GD32_IWDG_PR_32 3U
#define GD32_IWDG_PR_64 4U
#define GD32_IWDG_PR_128 5U
#define GD32_IWDG_PR_256 6U
/** @} */
/**
* @name WINR register definitions
* @{
*/
#define GD32_IWDG_WIN_MASK (0x00000FFF << 0)
#define GD32_IWDG_WIN(n) ((n) << 0)
#define GD32_IWDG_WIN_DISABLED GD32_IWDG_WIN(0x00000FFF)
#define GD32_FWDGT_PSC_MASK (7 << 0)
#define GD32_FWDGT_PSC_4 0U
#define GD32_FWDGT_PSC_8 1U
#define GD32_FWDGT_PSC_16 2U
#define GD32_FWDGT_PSC_32 3U
#define GD32_FWDGT_PSC_64 4U
#define GD32_FWDGT_PSC_128 5U
#define GD32_FWDGT_PSC_256 6U
/** @} */
/*===========================================================================*/
@ -71,12 +62,12 @@
* @{
*/
/**
* @brief IWDG driver enable switch.
* @details If set to @p TRUE the support for IWDG is included.
* @brief FWDGT driver enable switch.
* @details If set to @p TRUE the support for FWDGT is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_WDG_USE_IWDG) || defined(__DOXYGEN__)
#define GD32_WDG_USE_IWDG FALSE
#if !defined(GD32_WDG_USE_FWDGT) || defined(__DOXYGEN__)
#define GD32_WDG_USE_FWDGT FALSE
#endif
/** @} */
@ -84,11 +75,11 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if GD32_WDG_USE_IWDG && !GD32_HAS_IWDG
#error "IWDG not present in the selected device"
#if GD32_WDG_USE_FWDGT && !GD32_HAS_FWDGT
#error "FWDGT not present in the selected device"
#endif
#if !GD32_WDG_USE_IWDG
#if !GD32_WDG_USE_FWDGT
#error "WDG driver activated but no xWDG peripheral assigned"
#endif
@ -96,8 +87,8 @@
#error "GD32_LSI_ENABLED not defined"
#endif
#if (GD32_WDG_USE_IWDG == TRUE) && (GD32_LSI_ENABLED == FALSE)
#error "IWDG requires LSI clock"
#if (GD32_WDG_USE_FWDGT == TRUE) && (GD32_LSI_ENABLED == FALSE)
#error "FWDGT requires LSI clock"
#endif
/*===========================================================================*/
@ -115,23 +106,15 @@ typedef struct WDGDriver WDGDriver;
*/
typedef struct {
/**
* @brief Configuration of the IWDG_PR register.
* @brief Configuration of the FWDGT_PSC register.
* @details See the STM32 reference manual for details.
*/
uint32_t pr;
uint32_t psc;
/**
* @brief Configuration of the IWDG_RLR register.
* @brief Configuration of the FWDGT_RLD register.
* @details See the STM32 reference manual for details.
*/
uint32_t rlr;
#if GD32_IWDG_IS_WINDOWED || defined(__DOXYGEN__)
/**
* @brief Configuration of the IWDG_WINR register.
* @details See the STM32 reference manual for details.
* @note This field is not present in F1, F2, F4, L1 sub-families.
*/
uint32_t winr;
#endif
uint32_t rld;
} WDGConfig;
/**
@ -148,9 +131,9 @@ struct WDGDriver {
const WDGConfig *config;
/* End of the mandatory fields.*/
/**
* @brief Pointer to the IWDG registers block.
* @brief Pointer to the FWDGT registers block.
*/
IWDG_TypeDef *wdg;
FWDGT_TypeDef *wdg;
};
/*===========================================================================*/
@ -161,7 +144,7 @@ struct WDGDriver {
/* External declarations. */
/*===========================================================================*/
#if GD32_WDG_USE_IWDG && !defined(__DOXYGEN__)
#if GD32_WDG_USE_FWDGT && !defined(__DOXYGEN__)
extern WDGDriver WDGD1;
#endif