Rename Independent Watchdog registers
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@ -307,9 +307,8 @@
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#define GD32_HAS_USB TRUE
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/* IWDG attributes.*/
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#define GD32_HAS_IWDG TRUE
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#define GD32_IWDG_IS_WINDOWED FALSE
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/* FWDGT attributes.*/
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#define GD32_HAS_FWDGT TRUE
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/* FSMC attributes.*/
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#if GD32_HAS_EXMC
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@ -404,11 +404,11 @@ typedef struct
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typedef struct
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{
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__IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
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__IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
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__IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
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__IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
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} IWDG_TypeDef;
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__IO uint32_t CTL; /*!< Key register, Address offset: 0x00 */
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__IO uint32_t PSC; /*!< Prescaler register, Address offset: 0x04 */
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__IO uint32_t RLD; /*!< Reload register, Address offset: 0x08 */
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__IO uint32_t STAT; /*!< Status register, Address offset: 0x0C */
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} FWDGT_TypeDef;
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/**
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* @brief Power Control
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@ -679,7 +679,7 @@ typedef struct
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#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
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//#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
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#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
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#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
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#define FWDGT_BASE (APB1PERIPH_BASE + 0x00003000U)
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#define SPI1_BASE (APB1PERIPH_BASE + 0x00003800U)
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#define SPI2_BASE (APB1PERIPH_BASE + 0x00003C00U)
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#define USART1_BASE (APB1PERIPH_BASE + 0x00004400U)
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@ -767,7 +767,7 @@ typedef struct
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#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
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#define RTC ((RTC_TypeDef *)RTC_BASE)
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#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
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#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
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#define FWDGT ((FWDGT_TypeDef *)FWDGT_BASE)
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#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
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#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
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#define USART1 ((USART_TypeDef *)USART1_BASE)
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@ -1774,9 +1774,9 @@ typedef struct
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#define RCC_CSR_SFTRSTF_Pos (28U)
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#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
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#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
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#define RCC_CSR_IWDGRSTF_Pos (29U)
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#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
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#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
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#define RCC_CSR_FWDGTRSTF_Pos (29U)
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#define RCC_CSR_FWDGTRSTF_Msk (0x1U << RCC_CSR_FWDGTRSTF_Pos) /*!< 0x20000000 */
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#define RCC_CSR_FWDGTRSTF RCC_CSR_FWDGTRSTF_Msk /*!< Independent Watchdog reset flag */
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#define RCC_CSR_WWDGRSTF_Pos (30U)
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#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
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#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
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@ -5172,35 +5172,35 @@ typedef struct
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/******************************************************************************/
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/* */
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/* Independent WATCHDOG (IWDG) */
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/* FREE WATCHDOG TIMER (FWDGT) */
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/* */
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/******************************************************************************/
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/******************* Bit definition for IWDG_KR register ********************/
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#define IWDG_KR_KEY_Pos (0U)
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#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
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#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
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/******************* Bit definition for FWDGT_CTL register ********************/
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#define FWDGT_CTL_CMD_Pos (0U)
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#define FWDGT_CTL_CMD_Msk (0xFFFFU << FWDGT_CTL_CMD_Pos) /*!< 0x0000FFFF */
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#define FWDGT_CTL_CMD FWDGT_CTL_CMD_Msk /*!< Key value (write only, read 0000h) */
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/******************* Bit definition for IWDG_PR register ********************/
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#define IWDG_PR_PR_Pos (0U)
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#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
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#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
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#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
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#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
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#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
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/******************* Bit definition for FWDGT_PSC register ********************/
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#define FWDGT_PSC_PSC_Pos (0U)
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#define FWDGT_PSC_PSC_Msk (0x7U << FWDGT_PSC_PSC_Pos) /*!< 0x00000007 */
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#define FWDGT_PSC_PSC FWDGT_PSC_PSC_Msk /*!< PR[2:0] (Prescaler divider) */
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#define FWDGT_PSC_PSC_0 (0x1U << FWDGT_PSC_PSC_Pos) /*!< 0x00000001 */
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#define FWDGT_PSC_PSC_1 (0x2U << FWDGT_PSC_PSC_Pos) /*!< 0x00000002 */
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#define FWDGT_PSC_PSC_2 (0x4U << FWDGT_PSC_PSC_Pos) /*!< 0x00000004 */
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/******************* Bit definition for IWDG_RLR register *******************/
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#define IWDG_RLR_RL_Pos (0U)
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#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
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#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
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/******************* Bit definition for FWDGT_RLD register *******************/
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#define FWDGT_RLD_RLD_Pos (0U)
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#define FWDGT_RLD_RLD_Msk (0xFFFU << FWDGT_RLD_RLD_Pos) /*!< 0x00000FFF */
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#define FWDGT_RLD_RLD FWDGT_RLD_RLD_Msk /*!< Watchdog counter reload value */
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/******************* Bit definition for IWDG_SR register ********************/
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#define IWDG_SR_PVU_Pos (0U)
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#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
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#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
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#define IWDG_SR_RVU_Pos (1U)
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#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
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#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
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/******************* Bit definition for FWDGT_STAT register ********************/
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#define FWDGT_STAT_PUD_Pos (0U)
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#define FWDGT_STAT_PUD_Msk (0x1U << FWDGT_STAT_PUD_Pos) /*!< 0x00000001 */
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#define FWDGT_STAT_PUD FWDGT_STAT_PUD_Msk /*!< Watchdog prescaler value update */
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#define FWDGT_STAT_RUD_Pos (1U)
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#define FWDGT_STAT_RUD_Msk (0x1U << FWDGT_STAT_RUD_Pos) /*!< 0x00000002 */
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#define FWDGT_STAT_RUD FWDGT_STAT_RUD_Msk /*!< Watchdog counter reload value update */
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/******************************************************************************/
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/* */
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@ -30,20 +30,20 @@
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/* Driver local definitions. */
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/*===========================================================================*/
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#define KR_KEY_RELOAD 0xAAAAU
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#define KR_KEY_ENABLE 0xCCCCU
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#define KR_KEY_WRITE 0x5555U
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#define KR_KEY_PROTECT 0x0000U
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#define CTL_CMD_RELOAD 0xAAAAU
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#define CTL_CMD_ENABLE 0xCCCCU
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#define CTL_CMD_WRITE 0x5555U
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#define CTL_CMD_PROTECT 0x0000U
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#if !defined(IWDG) && defined(IWDG1)
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#define IWDG IWDG1
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#if !defined(FWDGT) && defined(FWDGT1)
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#define FWDGT FWDGT1
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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#if GD32_WDG_USE_IWDG || defined(__DOXYGEN__)
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#if GD32_WDG_USE_FWDGT || defined(__DOXYGEN__)
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WDGDriver WDGD1;
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#endif
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@ -70,9 +70,9 @@ WDGDriver WDGD1;
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*/
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void wdg_lld_init(void) {
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#if GD32_WDG_USE_IWDG
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#if GD32_WDG_USE_FWDGT
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WDGD1.state = WDG_STOP;
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WDGD1.wdg = IWDG;
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WDGD1.wdg = FWDGT;
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#endif
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}
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@ -85,24 +85,19 @@ void wdg_lld_init(void) {
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*/
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void wdg_lld_start(WDGDriver *wdgp) {
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/* Enable IWDG and unlock for write.*/
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wdgp->wdg->KR = KR_KEY_ENABLE;
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wdgp->wdg->KR = KR_KEY_WRITE;
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/* Enable FWDGT and unlock for write.*/
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wdgp->wdg->CTL = CTL_CMD_ENABLE;
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wdgp->wdg->CTL = CTL_CMD_WRITE;
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/* Write configuration.*/
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wdgp->wdg->PR = wdgp->config->pr;
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wdgp->wdg->RLR = wdgp->config->rlr;
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wdgp->wdg->PSC = wdgp->config->psc;
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wdgp->wdg->RLD = wdgp->config->rld;
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/* Wait the registers to be updated.*/
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while (wdgp->wdg->SR != 0)
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while (wdgp->wdg->STAT != 0)
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;
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#if GD32_IWDG_IS_WINDOWED
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/* This also triggers a refresh.*/
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wdgp->wdg->WINR = wdgp->config->winr;
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#else
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wdgp->wdg->KR = KR_KEY_RELOAD;
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#endif
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wdgp->wdg->CTL = CTL_CMD_RELOAD;
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}
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/**
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@ -115,7 +110,7 @@ void wdg_lld_start(WDGDriver *wdgp) {
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void wdg_lld_stop(WDGDriver *wdgp) {
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osalDbgAssert(wdgp->state == WDG_STOP,
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"IWDG cannot be stopped once activated");
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"FWDGT cannot be stopped once activated");
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}
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/**
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@ -127,7 +122,7 @@ void wdg_lld_stop(WDGDriver *wdgp) {
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*/
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void wdg_lld_reset(WDGDriver * wdgp) {
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wdgp->wdg->KR = KR_KEY_RELOAD;
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wdgp->wdg->CTL = CTL_CMD_RELOAD;
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}
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#endif /* HAL_USE_WDG == TRUE */
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@ -35,31 +35,22 @@
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* @name RLR register definitions
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* @{
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*/
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#define GD32_IWDG_RL_MASK (0x00000FFF << 0)
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#define GD32_IWDG_RL(n) ((n) << 0)
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#define GD32_FWDGT_RLD_MASK (0x00000FFF << 0)
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#define GD32_FWDGT_RLD(n) ((n) << 0)
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/** @} */
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/**
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* @name PR register definitions
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* @{
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*/
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#define GD32_IWDG_PR_MASK (7 << 0)
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#define GD32_IWDG_PR_4 0U
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#define GD32_IWDG_PR_8 1U
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#define GD32_IWDG_PR_16 2U
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#define GD32_IWDG_PR_32 3U
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#define GD32_IWDG_PR_64 4U
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#define GD32_IWDG_PR_128 5U
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#define GD32_IWDG_PR_256 6U
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/** @} */
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/**
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* @name WINR register definitions
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* @{
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*/
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#define GD32_IWDG_WIN_MASK (0x00000FFF << 0)
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#define GD32_IWDG_WIN(n) ((n) << 0)
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#define GD32_IWDG_WIN_DISABLED GD32_IWDG_WIN(0x00000FFF)
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#define GD32_FWDGT_PSC_MASK (7 << 0)
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#define GD32_FWDGT_PSC_4 0U
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#define GD32_FWDGT_PSC_8 1U
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#define GD32_FWDGT_PSC_16 2U
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#define GD32_FWDGT_PSC_32 3U
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#define GD32_FWDGT_PSC_64 4U
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#define GD32_FWDGT_PSC_128 5U
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#define GD32_FWDGT_PSC_256 6U
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/** @} */
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/*===========================================================================*/
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@ -71,12 +62,12 @@
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* @{
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*/
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/**
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* @brief IWDG driver enable switch.
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* @details If set to @p TRUE the support for IWDG is included.
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* @brief FWDGT driver enable switch.
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* @details If set to @p TRUE the support for FWDGT is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_WDG_USE_IWDG) || defined(__DOXYGEN__)
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#define GD32_WDG_USE_IWDG FALSE
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#if !defined(GD32_WDG_USE_FWDGT) || defined(__DOXYGEN__)
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#define GD32_WDG_USE_FWDGT FALSE
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#endif
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/** @} */
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@ -84,11 +75,11 @@
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if GD32_WDG_USE_IWDG && !GD32_HAS_IWDG
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#error "IWDG not present in the selected device"
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#if GD32_WDG_USE_FWDGT && !GD32_HAS_FWDGT
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#error "FWDGT not present in the selected device"
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#endif
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#if !GD32_WDG_USE_IWDG
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#if !GD32_WDG_USE_FWDGT
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#error "WDG driver activated but no xWDG peripheral assigned"
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#endif
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#error "GD32_LSI_ENABLED not defined"
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#endif
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#if (GD32_WDG_USE_IWDG == TRUE) && (GD32_LSI_ENABLED == FALSE)
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#error "IWDG requires LSI clock"
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#if (GD32_WDG_USE_FWDGT == TRUE) && (GD32_LSI_ENABLED == FALSE)
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#error "FWDGT requires LSI clock"
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#endif
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/*===========================================================================*/
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*/
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typedef struct {
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/**
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* @brief Configuration of the IWDG_PR register.
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* @brief Configuration of the FWDGT_PSC register.
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* @details See the STM32 reference manual for details.
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*/
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uint32_t pr;
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uint32_t psc;
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/**
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* @brief Configuration of the IWDG_RLR register.
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* @brief Configuration of the FWDGT_RLD register.
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* @details See the STM32 reference manual for details.
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*/
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uint32_t rlr;
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#if GD32_IWDG_IS_WINDOWED || defined(__DOXYGEN__)
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/**
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* @brief Configuration of the IWDG_WINR register.
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* @details See the STM32 reference manual for details.
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* @note This field is not present in F1, F2, F4, L1 sub-families.
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*/
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uint32_t winr;
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#endif
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uint32_t rld;
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} WDGConfig;
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/**
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const WDGConfig *config;
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/* End of the mandatory fields.*/
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/**
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* @brief Pointer to the IWDG registers block.
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* @brief Pointer to the FWDGT registers block.
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*/
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IWDG_TypeDef *wdg;
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FWDGT_TypeDef *wdg;
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};
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if GD32_WDG_USE_IWDG && !defined(__DOXYGEN__)
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#if GD32_WDG_USE_FWDGT && !defined(__DOXYGEN__)
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extern WDGDriver WDGD1;
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#endif
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