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Merge pull request #205 from ChibiOS/fsmc 

FSMC drivers update
This commit is contained in:
Fabien Poussin 2019-11-04 10:49:50 +01:00 committed by GitHub
parent 462e4e00f6 c65efdcfa1
commit d1aad88536
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
64 changed files with 1207 additions and 487 deletions
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14
demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

4
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC TRUE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM TRUE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

5
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c
View File

@ -23,7 +23,6 @@
#include "usbcfg.h"
#endif
#include "hal_fsmc_sdram.h"
#include "ili9341.h"
#include "hal_stm32_ltdc.h"
#include "hal_stm32_dma2d.h"
@ -556,8 +555,8 @@ int main(void) {
/*
* Initialise FSMC for SDRAM.
*/
fsmcSdramInit();
fsmcSdramStart(&SDRAMD, &sdram_cfg);
sdramInit();
sdramStart(&SDRAMD1, &sdram_cfg);
sdram_bulk_erase();
/*

30
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h
View File

@ -19,29 +19,31 @@
*/
#define STM32_FSMC_USE_FSMC1 TRUE
#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
#define STM32_FSMC_DMA_CHN 0x03010201
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
/*
* FSMC SDRAM driver system settings.
*/
#define STM32_USE_FSMC_SDRAM TRUE
#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0
#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
/*
* FSMC SRAM driver system settings.
*/
#define STM32_USE_FSMC_SRAM FALSE
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
#define STM32_SRAM_USE_SRAM1 FALSE
#define STM32_SRAM_USE_SRAM2 FALSE
#define STM32_SRAM_USE_SRAM3 FALSE
#define STM32_SRAM_USE_SRAM4 FALSE
/*
* FSMC SDRAM driver system settings.
*/
#define STM32_SDRAM_USE_SDRAM1 FALSE
#define STM32_SDRAM_USE_SDRAM2 TRUE
/*
* LTDC driver system settings.

14
demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

12
os/hal/hal.mk
View File

@ -10,9 +10,18 @@ endif
HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c
ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),)
HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c
endif
ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),)
HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c
endif
ifneq ($(findstring HAL_USE_SRAM TRUE,$(HALCONF)),)
HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c
endif
ifneq ($(findstring HAL_USE_SDRAM TRUE,$(HALCONF)),)
HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c
endif
ifneq ($(findstring HAL_USE_ONEWIRE TRUE,$(HALCONF)),)
HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c
endif
@ -75,7 +84,10 @@ HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c
endif
else
HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \

25
os/hal/include/hal_community.h
View File

@ -27,6 +27,10 @@
/* Error checks on the configuration header file.*/
#if !defined(HAL_USE_COMP)
#define HAL_USE_COMP FALSE
#endif
#if !defined(HAL_USE_CRC)
#define HAL_USE_CRC FALSE
#endif
@ -39,6 +43,10 @@
#define HAL_USE_EICU FALSE
#endif
#if !defined(HAL_USE_FSMC)
#define HAL_USE_FSMC FALSE
#endif
#if !defined(HAL_USE_NAND)
#define HAL_USE_NAND FALSE
#endif
@ -47,6 +55,10 @@
#define HAL_USE_ONEWIRE FALSE
#endif
#if !defined(HAL_USE_OPAMP)
#define HAL_USE_OPAMP FALSE
#endif
#if !defined(HAL_USE_QEI)
#define HAL_USE_QEI FALSE
#endif
@ -71,12 +83,12 @@
#define HAL_USE_USB_MSD FALSE
#endif
#if !defined(HAL_USE_COMP)
#define HAL_USE_COMP FALSE
#if !defined(HAL_USE_SDRAM)
#define HAL_USE_SDRAM FALSE
#endif
#if !defined(HAL_USE_OPAMP)
#define HAL_USE_OPAMP FALSE
#if !defined(HAL_USE_SRAM)
#define HAL_USE_SRAM FALSE
#endif
/* Abstract interfaces.*/
@ -84,7 +96,6 @@
/* Shared headers.*/
/* Normal drivers.*/
#include "hal_nand.h"
#include "hal_eicu.h"
#include "hal_rng.h"
#include "hal_usbh.h"
@ -92,6 +103,7 @@
#include "hal_qei.h"
#include "hal_comp.h"
#include "hal_opamp.h"
#include "hal_fsmc.h"
/* Complex drivers.*/
#include "hal_onewire.h"
@ -99,6 +111,9 @@
#include "hal_eeprom.h"
#include "hal_usb_hid.h"
#include "hal_usb_msd.h"
#include "hal_nand.h"
#include "hal_sram.h"
#include "hal_sdram.h"
/*===========================================================================*/
/* Driver constants. */

53
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h → os/hal/include/hal_fsmc.h
View File

@ -25,6 +25,8 @@
#ifndef HAL_FSMC_H_
#define HAL_FSMC_H_
#include "hal.h"
#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
@ -159,7 +161,7 @@ typedef struct {
__IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */
uint32_t RESERVED[63]; /**< Reserved */
__IO uint32_t BWTR; /**< SRAM/NOR write timing registers */
} FSMC_SRAM_NOR_TypeDef;
} FSMC_SRAM_TypeDef;
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
@ -246,10 +248,15 @@ typedef struct {
/* Driver pre-compile time settings. */
/*===========================================================================*/
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
/**
* @name Configuration options
* @{
*/
/**
* @brief FSMC driver enable switch.
* @details If set to @p TRUE the support for FSMC is included.
@ -295,29 +302,35 @@ struct FSMCDriver {
fsmcstate_t state;
/* End of the mandatory fields.*/
#if STM32_SRAM_USE_FSMC_SRAM1
FSMC_SRAM_NOR_TypeDef *sram1;
#if HAL_USE_SRAM
#if STM32_SRAM_USE_SRAM1
FSMC_SRAM_TypeDef *sram1;
#endif
#if STM32_SRAM_USE_SRAM2
FSMC_SRAM_TypeDef *sram2;
#endif
#if STM32_SRAM_USE_SRAM3
FSMC_SRAM_TypeDef *sram3;
#endif
#if STM32_SRAM_USE_SRAM4
FSMC_SRAM_TypeDef *sram4;
#endif
#endif
#if STM32_SRAM_USE_FSMC_SRAM2
FSMC_SRAM_NOR_TypeDef *sram2;
#endif
#if STM32_SRAM_USE_FSMC_SRAM3
FSMC_SRAM_NOR_TypeDef *sram3;
#endif
#if STM32_SRAM_USE_FSMC_SRAM4
FSMC_SRAM_NOR_TypeDef *sram4;
#endif
#if STM32_NAND_USE_FSMC_NAND1
#if HAL_USE_NAND
#if STM32_NAND_USE_NAND1
FSMC_NAND_TypeDef *nand1;
#endif
#if STM32_NAND_USE_FSMC_NAND2
#endif
#if STM32_NAND_USE_NAND1
FSMC_NAND_TypeDef *nand2;
#endif
#endif
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F7))
#if STM32_USE_FSMC_SDRAM
FSMC_SDRAM_TypeDef *sdram;
#if HAL_USE_SDRAM
FSMC_SDRAM_TypeDef *sdram;
#endif
#endif
};
@ -337,9 +350,9 @@ extern FSMCDriver FSMCD1;
#ifdef __cplusplus
extern "C" {
#endif
void fsmc_init(void);
void fsmc_start(FSMCDriver *fsmcp);
void fsmc_stop(FSMCDriver *fsmcp);
void fsmcInit(void);
void fsmcStart(FSMCDriver *fsmcp);
void fsmcStop(FSMCDriver *fsmcp);
#ifdef __cplusplus
}
#endif

1
os/hal/include/hal_nand.h
View File

@ -51,6 +51,7 @@
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the NAND.
*/

244
os/hal/include/hal_sdram.h Normal file
View File

@ -0,0 +1,244 @@
/*
ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
SDRAM routines added by Nick Klimov aka progfin.
*/
/**
* @file hal_sdram.h
* @brief SDRAM Driver subsystem low level driver header.
*
* @addtogroup SDRAM
* @{
*/
#ifndef HAL_SDRAM_H_
#define HAL_SDRAM_H_
#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* FMC SDRAM Mode definition register defines
*/
#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
/*
* FMC_ReadPipe_Delay
*/
#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
/*
* FMC_Read_Burst
*/
#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
/*
* FMC_SDClock_Period
*/
#define FMC_SDClock_Disable ((uint32_t)0x00000000)
#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
/*
* FMC_ColumnBits_Number
*/
#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
/*
* FMC_RowBits_Number
*/
#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
/*
* FMC_SDMemory_Data_Width
*/
#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
/*
* FMC_InternalBank_Number
*/
#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
/*
* FMC_CAS_Latency
*/
#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
/*
* FMC_Write_Protection
*/
#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM1 is included.
*/
#if !defined(STM32_SDRAM_USE_SDRAM1) || defined(__DOXYGEN__)
#define STM32_SDRAM_USE_SDRAM1 FALSE
#else
#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE
#endif
/**
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM2 is included.
*/
#if !defined(STM32_SDRAM_USE_SDRAM2) || defined(__DOXYGEN__)
#define STM32_SDRAM_USE_SDRAM2 FALSE
#else
#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !STM32_SDRAM_USE_SDRAM1 && !STM32_SDRAM_USE_SDRAM2
#error "SDRAM driver activated but no SDRAM peripheral assigned"
#endif
#if (STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2) && !STM32_HAS_FSMC
#error "FMC not present in the selected device"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Driver state machine possible states.
*/
typedef enum {
SDRAM_UNINIT = 0, /**< Not initialized. */
SDRAM_STOP = 1, /**< Stopped. */
SDRAM_READY = 2, /**< Ready. */
} sdramstate_t;
/**
* @brief Type of a structure representing an SDRAM driver.
*/
typedef struct SDRAMDriver SDRAMDriver;
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
*/
typedef struct {
/**
* @brief SDRAM control register.
* @note Its value will be used for both banks.
*/
uint32_t sdcr;
/**
* @brief SDRAM timing register.
* @note Its value will be used for both banks.
*/
uint32_t sdtr;
/**
* @brief SDRAM command mode register.
* @note Only its MRD and NRFS bits will be used.
*/
uint32_t sdcmr;
/**
* @brief SDRAM refresh timer register.
* @note Only its COUNT bits will be used.
*/
uint32_t sdrtr;
} SDRAMConfig;
/**
* @brief Structure representing an SDRAM driver.
*/
struct SDRAMDriver {
/**
* @brief Driver state.
*/
sdramstate_t state;
/**
* @brief Pointer to the FMC SDRAM registers block.
*/
FSMC_SDRAM_TypeDef *sdram;
};
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
extern SDRAMDriver SDRAMD1;
#ifdef __cplusplus
extern "C" {
#endif
void sdramInit(void);
void sdramObjectInit(SDRAMDriver *sdramp);
void sdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp);
void sdramStop(SDRAMDriver *sdramp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_SDRAM */
#endif /* HAL_SDRAM_H_ */
/** @} */

53
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h → os/hal/include/hal_sram.h
View File

@ -22,12 +22,10 @@
* @{
*/
#ifndef HAL_FSMC_SRAM_H_
#define HAL_FSMC_SRAM_H_
#ifndef HAL_SRAM_H_
#define HAL_SRAM_H_
#include "hal_fsmc.h"
#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__)
#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@ -45,32 +43,32 @@
* @brief SRAM driver enable switch.
* @details If set to @p TRUE the support for SRAM1 is included.
*/
#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
#if !defined(STM32_SRAM_USE_SRAM1) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_SRAM1 FALSE
#endif
/**
* @brief SRAM driver enable switch.
* @details If set to @p TRUE the support for SRAM2 is included.
*/
#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
#if !defined(STM32_SRAM_USE_SRAM2) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_SRAM2 FALSE
#endif
/**
* @brief SRAM driver enable switch.
* @details If set to @p TRUE the support for SRAM3 is included.
*/
#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
#if !defined(STM32_SRAM_USE_SRAM3) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_SRAM3 FALSE
#endif
/**
* @brief SRAM driver enable switch.
* @details If set to @p TRUE the support for SRAM4 is included.
*/
#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
#if !defined(STM32_SRAM_USE_SRAM4) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_SRAM4 FALSE
#endif
/** @} */
@ -79,13 +77,13 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \
!STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4
#if !STM32_SRAM_USE_SRAM1 && !STM32_SRAM_USE_SRAM2 && \
!STM32_SRAM_USE_SRAM3 && !STM32_SRAM_USE_SRAM4
#error "SRAM driver activated but no SRAM peripheral assigned"
#endif
#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \
STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC
#if (STM32_SRAM_USE_SRAM1 || STM32_SRAM_USE_SRAM2 || \
STM32_SRAM_USE_SRAM3 || STM32_SRAM_USE_SRAM4) && !STM32_HAS_FSMC
#error "FSMC not present in the selected device"
#endif
@ -128,7 +126,7 @@ struct SRAMDriver {
/**
* @brief Pointer to the FSMC SRAM registers block.
*/
FSMC_SRAM_NOR_TypeDef *sram;
FSMC_SRAM_TypeDef *sram;
};
/*===========================================================================*/
@ -139,34 +137,35 @@ struct SRAMDriver {
/* External declarations. */
/*===========================================================================*/
#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__)
#if STM32_SRAM_USE_SRAM1 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD1;
#endif
#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__)
#if STM32_SRAM_USE_SRAM2 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD2;
#endif
#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__)
#if STM32_SRAM_USE_SRAM3 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD3;
#endif
#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__)
#if STM32_SRAM_USE_SRAM4 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD4;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void fsmcSramInit(void);
void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp);
void fsmcSramStop(SRAMDriver *sramp);
void sramInit(void);
void sramObjectInit(SRAMDriver *sdramp);
void sramStart(SRAMDriver *sramp, const SRAMConfig *cfgp);
void sramStop(SRAMDriver *sramp);
#ifdef __cplusplus
}
#endif
#endif /* STM32_USE_FSMC_SRAM */
#endif /* HAL_USE_SRAM */
#endif /* HAL_FSMC_SRAM_H_ */
#endif /* HAL_SRAM_H_ */
/** @} */

14
os/hal/ports/STM32/LLD/FSMCv1/driver.mk
View File

@ -1,16 +1,16 @@
ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
ifneq ($(findstring HAL_USE_SDRAM TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c
endif
ifneq ($(findstring HAL_USE_SRAM TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c
endif
ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
endif
else
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c \
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
endif

24
os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file hal_nand_lld.c
* @brief NAND Driver subsystem low level driver source.
* @file hal_fsmc_nand_lld.c
* @brief FSMC NAND Driver subsystem low level driver source.
*
* @addtogroup NAND
* @{
@ -26,6 +26,8 @@
#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__)
#include "hal_nand_lld.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
@ -53,14 +55,14 @@
/**
* @brief NAND1 driver identifier.
*/
#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__)
#if STM32_NAND_USE_NAND1 || defined(__DOXYGEN__)
NANDDriver NANDD1;
#endif
/**
* @brief NAND2 driver identifier.
*/
#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__)
#if STM32_NAND_USE_NAND2 || defined(__DOXYGEN__)
NANDDriver NANDD2;
#endif
@ -280,9 +282,9 @@ static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) {
*/
void nand_lld_init(void) {
fsmc_init();
fsmcInit();
#if STM32_NAND_USE_FSMC_NAND1
#if STM32_NAND_USE_NAND1
/* Driver initialization.*/
nandObjectInit(&NANDD1);
NANDD1.rxdata = NULL;
@ -294,9 +296,9 @@ void nand_lld_init(void) {
NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD;
NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR;
NANDD1.bb_map = NULL;
#endif /* STM32_NAND_USE_FSMC_NAND1 */
#endif /* STM32_NAND_USE_NAND1 */
#if STM32_NAND_USE_FSMC_NAND2
#if STM32_NAND_USE_NAND2
/* Driver initialization.*/
nandObjectInit(&NANDD2);
NANDD2.rxdata = NULL;
@ -308,7 +310,7 @@ void nand_lld_init(void) {
NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD;
NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR;
NANDD2.bb_map = NULL;
#endif /* STM32_NAND_USE_FSMC_NAND2 */
#endif /* STM32_NAND_USE_NAND2 */
}
/**
@ -325,7 +327,7 @@ void nand_lld_start(NANDDriver *nandp) {
uint32_t pcr_bus_width;
if (FSMCD1.state == FSMC_STOP)
fsmc_start(&FSMCD1);
fsmcStart(&FSMCD1);
if (nandp->state == NAND_STOP) {
b = dmaStreamAlloc(nandp->dma,
@ -345,7 +347,7 @@ void nand_lld_start(NANDDriver *nandp) {
#endif
nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) |
STM32_DMA_CR_PL(STM32_NAND_DMA_PRIORITY) |
dmasize |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE |

36
os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
View File

@ -16,7 +16,7 @@
/**
* @file hal_nand_lld.h
* @brief NAND Driver subsystem low level driver header.
* @brief FSMC NAND Driver subsystem low level driver header.
*
* @addtogroup NAND
* @{
@ -25,8 +25,8 @@
#ifndef HAL_NAND_LLD_H_
#define HAL_NAND_LLD_H_
#include "hal_fsmc.h"
#include "bitmap.h"
#include "hal_fsmc.h"
#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__)
@ -72,38 +72,38 @@
* @note The default action for DMA errors is a system halt because DMA
* error can only happen because programming errors.
*/
#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
#if !defined(STM32_FSMC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
#endif
/**
* @brief NAND interrupt enable switch.
* @details If set to @p TRUE the support for internal FSMC interrupt included.
*/
#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__)
#define STM32_NAND_USE_INT FALSE
#if !defined(STM32_FSMC_NAND_USE_INT) || defined(__DOXYGEN__)
#define STM32_FSMC_NAND_USE_INT FALSE
#endif
/**
* @brief NAND1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_NAND_NAND1_DMA_PRIORITY 0
#if !defined(STM32_FSMC_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_FSMC_NAND1_DMA_PRIORITY 0
#endif
/**
* @brief NAND2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_NAND_NAND2_DMA_PRIORITY 0
#if !defined(STM32_FSMC_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_FSMC_NAND2_DMA_PRIORITY 0
#endif
/**
* @brief DMA stream used for NAND operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#if !defined(STM32_FSMC_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#endif
/** @} */
@ -112,18 +112,14 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2
#if !STM32_NAND_USE_NAND1 && !STM32_NAND_USE_NAND2
#error "NAND driver activated but no NAND peripheral assigned"
#endif
#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC
#if (STM32_NAND_USE_NAND1 || STM32_NAND_USE_NAND2) && !STM32_HAS_FSMC
#error "FSMC not present in the selected device"
#endif
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@ -260,11 +256,11 @@ struct NANDDriver {
/* External declarations. */
/*===========================================================================*/
#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__)
#if STM32_NAND_USE_NAND1 && !defined(__DOXYGEN__)
extern NANDDriver NANDD1;
#endif
#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__)
#if STM32_NAND_USE_NAND2 && !defined(__DOXYGEN__)
extern NANDDriver NANDD2;
#endif

107
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c → os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c
View File

@ -34,9 +34,9 @@
defined(STM32F769xx) || defined(STM32F777xx) || \
defined(STM32F779xx))
#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
#include "hal_fsmc_sdram.h"
#include "hal_sdram_lld.h"
/*===========================================================================*/
/* Driver local definitions. */
@ -59,7 +59,7 @@
/**
* @brief SDRAM driver identifier.
*/
SDRAMDriver SDRAMD;
SDRAMDriver SDRAMD1;
/*===========================================================================*/
/* Driver local types. */
@ -78,9 +78,9 @@ SDRAMDriver SDRAMD;
*
* @notapi
*/
static void _sdram_wait_ready(void) {
static void sdram_lld_wait_ready(void) {
/* Wait until the SDRAM controller is ready */
while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY);
while (SDRAMD1.sdram->SDSR & FMC_SDSR_BUSY);
}
/**
@ -90,48 +90,48 @@ static void _sdram_wait_ready(void) {
*
* @notapi
*/
static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
static void sdram_lld_init_sequence(const SDRAMConfig *cfgp) {
uint32_t command_target = 0;
#if STM32_SDRAM_USE_FSMC_SDRAM1
#if STM32_SDRAM_USE_SDRAM1
command_target |= FMC_SDCMR_CTB1;
#endif
#if STM32_SDRAM_USE_FSMC_SDRAM2
#if STM32_SDRAM_USE_SDRAM2
command_target |= FMC_SDCMR_CTB2;
#endif
/* Step 3: Configure a clock configuration enable command.*/
_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
sdram_lld_wait_ready();
SDRAMD1.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
/* Step 4: Insert delay (tipically 100uS).*/
osalThreadSleepMilliseconds(1);
/* Step 5: Configure a PALL (precharge all) command.*/
_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target;
sdram_lld_wait_ready();
SDRAMD1.sdram->SDCMR = FMCCM_PALL | command_target;
/* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
sdram_lld_wait_ready();
SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
(cfgp->sdcmr & FMC_SDCMR_NRFS);
/* Step 6.2: Send the second command.*/
_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
sdram_lld_wait_ready();
SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
(cfgp->sdcmr & FMC_SDCMR_NRFS);
/* Step 7: Program the external memory mode register.*/
_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target |
sdram_lld_wait_ready();
SDRAMD1.sdram->SDCMR = FMCCM_LOAD_MODE | command_target |
(cfgp->sdcmr & FMC_SDCMR_MRD);
/* Step 8: Set clock.*/
_sdram_wait_ready();
SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT;
sdram_lld_wait_ready();
SDRAMD1.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT;
_sdram_wait_ready();
sdram_lld_wait_ready();
}
/*===========================================================================*/
@ -142,71 +142,28 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level SDRAM driver initialization.
*/
void fsmcSdramInit(void) {
void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp)
{
sdramp->sdram->SDCR1 = cfgp->sdcr;
sdramp->sdram->SDTR1 = cfgp->sdtr;
sdramp->sdram->SDCR2 = cfgp->sdcr;
sdramp->sdram->SDTR2 = cfgp->sdtr;
fsmc_init();
SDRAMD.sdram = FSMCD1.sdram;
SDRAMD.state = SDRAM_STOP;
sdram_lld_init_sequence(cfgp);
}
/**
* @brief Configures and activates the SDRAM peripheral.
*
* @param[in] sdramp pointer to the @p SDRAMDriver object
* @param[in] cfgp pointer to the @p SDRAMConfig object
*/
void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) {
if (FSMCD1.state == FSMC_STOP)
fsmc_start(&FSMCD1);
osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY),
"SDRAM. Invalid state.");
if (sdramp->state == SDRAM_STOP) {
/* Even if you need only bank2 you must properly set up SDCR and SDTR
regitsters for bank1 too. Both banks will be tuned equally assuming
connected memory ICs are equal.*/
sdramp->sdram->SDCR1 = cfgp->sdcr;
sdramp->sdram->SDTR1 = cfgp->sdtr;
sdramp->sdram->SDCR2 = cfgp->sdcr;
sdramp->sdram->SDTR2 = cfgp->sdtr;
_sdram_init_sequence(cfgp);
sdramp->state = SDRAM_READY;
}
}
/**
* @brief Deactivates the SDRAM peripheral.
*
* @param[in] sdramp pointer to the @p SDRAMDriver object
*
* @notapi
*/
void fsmcSdramStop(SDRAMDriver *sdramp) {
void sdram_lld_stop(SDRAMDriver *sdramp) {
uint32_t command_target = 0;
#if STM32_SDRAM_USE_FSMC_SDRAM1
#if STM32_SDRAM_USE_SDRAM1
command_target |= FMC_SDCMR_CTB1;
#endif
#if STM32_SDRAM_USE_FSMC_SDRAM2
#if STM32_SDRAM_USE_SDRAM2
command_target |= FMC_SDCMR_CTB2;
#endif
if (sdramp->state == SDRAM_READY) {
SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target;
sdramp->state = SDRAM_STOP;
}
sdramp->sdram->SDCMR = FMCCM_POWER_DOWN | command_target;
}
#endif /* STM32_USE_FSMC_SDRAM */
#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */

107
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h → os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h
View File

@ -18,26 +18,19 @@
*/
/**
* @file hal_fsmc_sdram.h
* @file hal_sdram.h
* @brief SDRAM Driver subsystem low level driver header.
*
* @addtogroup SDRAM
* @{
*/
#ifndef HAL_FMC_SDRAM_H_
#define HAL_FMC_SDRAM_H_
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F745xx) || defined(STM32F746xx) || \
defined(STM32F756xx) || defined(STM32F767xx) || \
defined(STM32F769xx) || defined(STM32F777xx) || \
defined(STM32F779xx))
#ifndef HAL_SDRAM_LLD_H_
#define HAL_SDRAM_LLD_H_
#include "hal_fsmc.h"
#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@ -55,8 +48,8 @@
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM1 is included.
*/
#if !defined(STM32_SDRAM_USE_FSMC_SDRAM1) || defined(__DOXYGEN__)
#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
#if !defined(STM32_SDRAM_USE_SDRAM1) || defined(__DOXYGEN__)
#define STM32_SDRAM_USE_SDRAM1 FALSE
#else
#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE
#endif
@ -65,8 +58,8 @@
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM2 is included.
*/
#if !defined(STM32_SDRAM_USE_FSMC_SDRAM2) || defined(__DOXYGEN__)
#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE
#if !defined(STM32_SDRAM_USE_SDRAM2) || defined(__DOXYGEN__)
#define STM32_SDRAM_USE_SDRAM2 FALSE
#else
#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE
#endif
@ -77,74 +70,27 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !STM32_SDRAM_USE_FSMC_SDRAM1 && !STM32_SDRAM_USE_FSMC_SDRAM2
#if !STM32_SDRAM_USE_SDRAM1 && !STM32_SDRAM_USE_SDRAM2
#error "SDRAM driver activated but no SDRAM peripheral assigned"
#endif
#if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM2) && !STM32_HAS_FSMC
#if (STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2) && !STM32_HAS_FSMC
#error "FMC not present in the selected device"
#endif
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F745xx) || defined(STM32F746xx) || \
defined(STM32F756xx) || defined(STM32F767xx) || \
defined(STM32F769xx) || defined(STM32F777xx) || \
defined(STM32F779xx))
#else
#error "Device is not compatible with SDRAM"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Driver state machine possible states.
*/
typedef enum {
SDRAM_UNINIT = 0, /**< Not initialized. */
SDRAM_STOP = 1, /**< Stopped. */
SDRAM_READY = 2, /**< Ready. */
} sdramstate_t;
/**
* @brief Type of a structure representing an SDRAM driver.
*/
typedef struct SDRAMDriver SDRAMDriver;
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
*/
typedef struct {
/**
* @brief SDRAM control register.
* @note Its value will be used for both banks.
*/
uint32_t sdcr;
/**
* @brief SDRAM timing register.
* @note Its value will be used for both banks.
*/
uint32_t sdtr;
/**
* @brief SDRAM command mode register.
* @note Only its MRD and NRFS bits will be used.
*/
uint32_t sdcmr;
/**
* @brief SDRAM refresh timer register.
* @note Only its COUNT bits will be used.
*/
uint32_t sdrtr;
} SDRAMConfig;
/**
* @brief Structure representing an SDRAM driver.
*/
struct SDRAMDriver {
/**
* @brief Driver state.
*/
sdramstate_t state;
/**
* @brief Pointer to the FMC SDRAM registers block.
*/
FSMC_SDRAM_TypeDef *sdram;
};
/*===========================================================================*/
/* Driver macros. */
@ -154,22 +100,19 @@ struct SDRAMDriver {
/* External declarations. */
/*===========================================================================*/
extern SDRAMDriver SDRAMD;
extern SDRAMDriver SDRAMD1;
#ifdef __cplusplus
extern "C" {
#endif
void fsmcSdramInit(void);
void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp);
void fsmcSdramStop(SDRAMDriver *sdramp);
void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp);
void sdram_lld_stop(SDRAMDriver *sdramp);
#ifdef __cplusplus
}
#endif
#endif /* STM32_USE_FSMC_SDRAM */
#endif /* STM32_SDRAM_USE_SDRAM */
#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */
#endif /* HAL_FMC_SDRAM_H_ */
#endif /* HAL_SDRAM_LLD_H_ */
/** @} */

61
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c → os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c
View File

@ -22,9 +22,10 @@
* @{
*/
#include "hal.h"
#include "hal_fsmc_sram.h"
#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__)
#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__)
#include "hal_sram_lld.h"
/*===========================================================================*/
/* Driver local definitions. */
@ -36,28 +37,28 @@
/**
* @brief SRAM1 driver identifier.
*/
#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__)
#if STM32_SRAM_USE_SRAM1 || defined(__DOXYGEN__)
SRAMDriver SRAMD1;
#endif
/**
* @brief SRAM2 driver identifier.
*/
#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__)
#if STM32_SRAM_USE_SRAM2 || defined(__DOXYGEN__)
SRAMDriver SRAMD2;
#endif
/**
* @brief SRAM3 driver identifier.
*/
#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__)
#if STM32_SRAM_USE_SRAM3 || defined(__DOXYGEN__)
SRAMDriver SRAMD3;
#endif
/**
* @brief SRAM4 driver identifier.
*/
#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__)
#if STM32_SRAM_USE_SRAM4 || defined(__DOXYGEN__)
SRAMDriver SRAMD4;
#endif
@ -81,36 +82,6 @@ SRAMDriver SRAMD4;
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level SRAM driver initialization.
*
* @notapi
*/
void fsmcSramInit(void) {
fsmc_init();
#if STM32_SRAM_USE_FSMC_SRAM1
SRAMD1.sram = FSMCD1.sram1;
SRAMD1.state = SRAM_STOP;
#endif /* STM32_SRAM_USE_FSMC_SRAM1 */
#if STM32_SRAM_USE_FSMC_SRAM2
SRAMD2.sram = FSMCD1.sram2;
SRAMD2.state = SRAM_STOP;
#endif /* STM32_SRAM_USE_FSMC_SRAM2 */
#if STM32_SRAM_USE_FSMC_SRAM3
SRAMD3.sram = FSMCD1.sram3;
SRAMD3.state = SRAM_STOP;
#endif /* STM32_SRAM_USE_FSMC_SRAM3 */
#if STM32_SRAM_USE_FSMC_SRAM4
SRAMD4.sram = FSMCD1.sram4;
SRAMD4.state = SRAM_STOP;
#endif /* STM32_SRAM_USE_FSMC_SRAM4 */
}
/**
* @brief Configures and activates the SRAM peripheral.
*
@ -119,20 +90,11 @@ void fsmcSramInit(void) {
*
* @notapi
*/
void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
void sram_lld_start(SRAMDriver *sramp, const SRAMConfig *cfgp) {
if (FSMCD1.state == FSMC_STOP)
fsmc_start(&FSMCD1);
osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY),
"invalid state");
if (sramp->state == SRAM_STOP) {
sramp->sram->BTR = cfgp->btr;
sramp->sram->BWTR = cfgp->bwtr;
sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN;
sramp->state = SRAM_READY;
}
}
/**
@ -142,9 +104,8 @@ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
*
* @notapi
*/
void fsmcSramStop(SRAMDriver *sramp) {
void sram_lld_stop(SRAMDriver *sramp) {
if (sramp->state == SRAM_READY) {
uint32_t mask = FSMC_BCR_MBKEN;
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
@ -155,11 +116,9 @@ void fsmcSramStop(SRAMDriver *sramp) {
mask |= FSMC_BCR_CCLKEN;
#endif
sramp->sram->BCR &= ~mask;
sramp->state = SRAM_STOP;
}
}
#endif /* STM32_USE_FSMC_SRAM */
#endif /* STM32_SRAM_USE_SRAM */
/** @} */

91
os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h Normal file
View File

@ -0,0 +1,91 @@
/*
ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_fsmc_sram.h
* @brief SRAM Driver subsystem low level driver header.
*
* @addtogroup SRAM
* @{
*/
#ifndef HAL_SRAM_LLD_H_
#define HAL_SRAM_LLD_H_
#include "hal_fsmc.h"
#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if STM32_SRAM_USE_SRAM1 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD1;
#endif
#if STM32_SRAM_USE_SRAM2 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD2;
#endif
#if STM32_SRAM_USE_SRAM3 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD3;
#endif
#if STM32_SRAM_USE_SRAM4 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD4;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void sram_lld_start(SRAMDriver *sramp, const SRAMConfig *cfgp);
void sram_lld_stop(SRAMDriver *sramp);
#ifdef __cplusplus
}
#endif
#endif /* STM32_SRAM_USE_SRAM */
#endif /* HAL_SRAM_LLD_H_ */
/** @} */

4
os/hal/src/hal_community.c
View File

@ -84,6 +84,10 @@ void halCommunityInit(void) {
#if HAL_USE_COMP || defined(__DOXYGEN__)
compInit();
#endif
#if HAL_USE_FSMC || defined(__DOXYGEN__)
fsmcInit();
#endif
}
#endif /* HAL_USE_COMMUNITY */

46
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c → os/hal/src/hal_fsmc.c
View File

@ -22,14 +22,15 @@
* @{
*/
#include "hal.h"
#include "hal_fsmc.h"
#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
#if (HAL_USE_SDRAM == TRUE) || (HAL_USE_SRAM == TRUE) || (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -66,44 +67,49 @@ FSMCDriver FSMCD1;
*
* @notapi
*/
void fsmc_init(void) {
void fsmcInit(void) {
if (FSMCD1.state == FSMC_UNINIT) {
FSMCD1.state = FSMC_STOP;
#if STM32_SRAM_USE_FSMC_SRAM1
FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE);
#if HAL_USE_SRAM
#if STM32_SRAM_USE_SRAM1
FSMCD1.sram1 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE);
#endif
#if STM32_SRAM_USE_FSMC_SRAM2
FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8);
#if STM32_SRAM_USE_SRAM2
FSMCD1.sram2 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8);
#endif
#if STM32_SRAM_USE_FSMC_SRAM3
FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2);
#if STM32_SRAM_USE_SRAM3
FSMCD1.sram3 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2);
#endif
#if STM32_SRAM_USE_FSMC_SRAM4
FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3);
#if STM32_SRAM_USE_SRAM4
FSMCD1.sram4 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3);
#endif
#endif
#if STM32_NAND_USE_FSMC_NAND1
#if HAL_USE_NAND
#if STM32_NAND_USE_NAND1
FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
#endif
#if STM32_NAND_USE_FSMC_NAND2
#if STM32_NAND_USE_NAND2
FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
#endif
#endif
#if HAL_USE_SDRAM
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F745xx) || defined(STM32F746xx) || \
defined(STM32F756xx) || defined(STM32F767xx) || \
defined(STM32F769xx) || defined(STM32F777xx) || \
defined(STM32F779xx))
#if STM32_USE_FSMC_SDRAM
#if STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2
FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE;
#endif
#endif
#endif
}
}
@ -115,7 +121,7 @@ void fsmc_init(void) {
*
* @notapi
*/
void fsmc_start(FSMCDriver *fsmcp) {
void fsmcStart(FSMCDriver *fsmcp) {
osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY),
"invalid state");
@ -145,7 +151,7 @@ void fsmc_start(FSMCDriver *fsmcp) {
*
* @notapi
*/
void fsmc_stop(FSMCDriver *fsmcp) {
void fsmcStop(FSMCDriver *fsmcp) {
if (fsmcp->state == FSMC_READY) {
/* Resets the peripheral.*/
@ -175,15 +181,17 @@ void fsmc_stop(FSMCDriver *fsmcp) {
CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
CH_IRQ_PROLOGUE();
#if STM32_NAND_USE_FSMC_NAND1
#if HAL_USE_NAND
#if STM32_NAND_USE_NAND1
if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) {
NANDD1.isr_handler(&NANDD1);
}
#endif
#if STM32_NAND_USE_FSMC_NAND2
#if STM32_NAND_USE_NAND2
if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) {
NANDD2.isr_handler(&NANDD2);
}
#endif
#endif
CH_IRQ_EPILOGUE();
}

122
os/hal/src/hal_sdram.c Normal file
View File

@ -0,0 +1,122 @@
/*
ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail)
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in sdramliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_sdram.c
* @brief SDRAM Driver code.
*
* @addtogroup SDRAM
* @{
*/
#include "hal.h"
#if HAL_USE_SDRAM || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
#include "hal_sdram_lld.h"
/**
* @brief SDRAM Driver initialization.
* @note This function is implicitly invoked by @p halInit(), there is
* no need to explicitly initialize the driver.
*
* @init
*/
void sdramInit(void) {
fsmcInit();
sdramObjectInit(&SDRAMD1);
}
/**
* @brief Initializes the standard part of a @p SDRAMDriver structure.
*
* @param[out] sdramp pointer to the @p SDRAMDriver object
*
* @init
*/
void sdramObjectInit(SDRAMDriver *sdramp) {
sdramp->sdram = FSMCD1.sdram;
sdramp->state = SDRAM_STOP;
}
/**
* @brief Configures and activates the SDRAM peripheral.
*
* @param[in] sdramp pointer to the @p SDRAMDriver object
* @param[in] config pointer to the @p SDRAMConfig object
*
* @api
*/
void sdramStart(SDRAMDriver *sdramp, const SDRAMConfig *config) {
osalDbgCheck((sdramp != NULL) && (config != NULL));
if (FSMCD1.state == FSMC_STOP)
fsmcStart(&FSMCD1);
osalSysLock();
osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY),
"invalid state");
sdram_lld_start(sdramp, config);
sdramp->state = SDRAM_READY;
osalSysUnlock();
}
/**
* @brief Deactivates the SDRAM peripheral.
*
* @param[in] sdramp pointer to the @p SDRAMDriver object
*
* @api
*/
void sdramStop(SDRAMDriver *sdramp) {
osalDbgCheck(sdramp != NULL);
osalSysLock();
osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY),
"invalid state");
sdram_lld_stop(sdramp);
sdramp->state = SDRAM_STOP;
osalSysUnlock();
}
#endif /* HAL_USE_SDRAM */
/** @} */

146
os/hal/src/hal_sram.c Normal file
View File

@ -0,0 +1,146 @@
/*
ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail)
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in sramliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_sram.c
* @brief SRAM Driver code.
*
* @addtogroup SRAM
* @{
*/
#include "hal.h"
#if HAL_USE_SRAM || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
#include "hal_sram_lld.h"
/**
* @brief SRAM Driver initialization.
* @note This function is implicitly invoked by @p halInit(), there is
* no need to explicitly initialize the driver.
*
* @init
*/
void sramInit(void) {
fsmcInit();
#if STM32_SRAM_USE_SRAM1
SRAMD1.sram = FSMCD1.sram1;
SRAMD1.state = SRAM_STOP;
sramObjectInit(&SRAMD1);
#endif /* STM32_SRAM_USE_SRAM1 */
#if STM32_SRAM_USE_SRAM2
SRAMD2.sram = FSMCD1.sram2;
SRAMD2.state = SRAM_STOP;
sramObjectInit(&SRAMD2);
#endif /* STM32_SRAM_USE_SRAM2 */
#if STM32_SRAM_USE_SRAM3
SRAMD3.sram = FSMCD1.sram3;
SRAMD3.state = SRAM_STOP;
sramObjectInit(&SRAMD3);
#endif /* STM32_SRAM_USE_SRAM3 */
#if STM32_SRAM_USE_SRAM4
SRAMD4.sram = FSMCD1.sram4;
SRAMD4.state = SRAM_STOP;
sramObjectInit(&SRAMD4);
#endif /* STM32_SRAM_USE_SRAM4 */
}
/**
* @brief Initializes the standard part of a @p SRAMDriver structure.
*
* @param[out] sramp pointer to the @p SRAMDriver object
*
* @init
*/
void sramObjectInit(SRAMDriver *sramp) {
sramp->state = SRAM_STOP;
}
/**
* @brief Configures and activates the SRAM peripheral.
*
* @param[in] sramp pointer to the @p SRAMDriver object
* @param[in] config pointer to the @p SRAMConfig object
*
* @api
*/
void sramStart(SRAMDriver *sramp, const SRAMConfig *config) {
osalDbgCheck((sramp != NULL) && (config != NULL));
if (FSMCD1.state == FSMC_STOP)
fsmcStart(&FSMCD1);
osalSysLock();
osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY),
"invalid state");
sram_lld_start(sramp, config);
sramp->state = SRAM_READY;
osalSysUnlock();
}
/**
* @brief Deactivates the SRAM peripheral.
*
* @param[in] sramp pointer to the @p SRAMDriver object
*
* @api
*/
void sramStop(SRAMDriver *sramp) {
osalDbgCheck(sramp != NULL);
osalSysLock();
osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY),
"invalid state");
sram_lld_stop(sramp);
sramp->state = SRAM_STOP;
osalSysUnlock();
}
#endif /* HAL_USE_SRAM */
/** @} */

14
testhal/STM32/STM32F0xx/COMP/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F0xx/COMP/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F0xx/crc/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F0xx/crc/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F0xx/onewire/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F0xx/onewire/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F0xx/qei/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F0xx/qei/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F1xx/onewire/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F1xx/onewire/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F1xx/qei/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F1xx/qei/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F3xx/COMP/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F3xx/COMP/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F3xx/EEProm/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F3xx/OPAMP/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F4xx/EICU/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F4xx/EICU/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC TRUE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F4xx/FSMC_NAND/main.c
View File

@ -78,9 +78,9 @@
#define NAND_TEST_KILL_BLOCK 8000
#endif
#if STM32_NAND_USE_FSMC_NAND1
#if STM32_NAND_USE_NAND1
#define NAND NANDD1
#elif STM32_NAND_USE_FSMC_NAND2
#elif STM32_NAND_USE_NAND2
#define NAND NANDD2
#else
#error "You should enable at least one NAND interface"

19
testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h
View File

@ -24,8 +24,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 TRUE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 TRUE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0
@ -34,19 +34,16 @@
/*
* FSMC SRAM driver system settings.
*/
#define STM32_USE_FSMC_SRAM FALSE
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
#define STM32_SRAM_USE_SRAM1 FALSE
#define STM32_SRAM_USE_SRAM2 FALSE
#define STM32_SRAM_USE_SRAM3 FALSE
#define STM32_SRAM_USE_SRAM4 FALSE
/*
* FSMC SDRAM driver system settings.
*/
#define STM32_USE_FSMC_SDRAM FALSE
#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE
#define STM32_SDRAM_USE_SDRAM1 FALSE
#define STM32_SDRAM_USE_SDRAM2 FALSE
/*
* TIMCAP driver system settings.
*/

14
testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC TRUE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM TRUE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

83
testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c
View File

@ -23,7 +23,6 @@
#include "string.h"
#include "hal_fsmc_sdram.h"
#include "membench.h"
#include "memtest.h"
@ -33,84 +32,6 @@
******************************************************************************
*/
/*
* FMC SDRAM Mode definition register defines
*/
#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
/*
* FMC_ReadPipe_Delay
*/
#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
/*
* FMC_Read_Burst
*/
#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
/*
* FMC_SDClock_Period
*/
#define FMC_SDClock_Disable ((uint32_t)0x00000000)
#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
/*
* FMC_ColumnBits_Number
*/
#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
/*
* FMC_RowBits_Number
*/
#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
/*
* FMC_SDMemory_Data_Width
*/
#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
/*
* FMC_InternalBank_Number
*/
#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
/*
* FMC_CAS_Latency
*/
#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
/*
* FMC_Write_Protection
*/
#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
#define SDRAM_SIZE (8 * 1024 * 1024)
#define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE)
@ -262,8 +183,8 @@ int main(void) {
halInit();
chSysInit();
fsmcSdramInit();
fsmcSdramStart(&SDRAMD, &sdram_cfg);
sdramInit();
sdramStart(&SDRAMD1, &sdram_cfg);
membench();
memtest();

18
testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h
View File

@ -26,8 +26,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0
@ -36,18 +36,16 @@
/*
* FSMC SRAM driver system settings.
*/
#define STM32_USE_FSMC_SRAM FALSE
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
#define STM32_SRAM_USE_SRAM1 FALSE
#define STM32_SRAM_USE_SRAM2 FALSE
#define STM32_SRAM_USE_SRAM3 FALSE
#define STM32_SRAM_USE_SRAM4 FALSE
/*
* FSMC SDRAM driver system settings.
*/
#define STM32_USE_FSMC_SDRAM TRUE
#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE
#define STM32_SDRAM_USE_SDRAM1 FALSE
#define STM32_SDRAM_USE_SDRAM2 TRUE
/*
* TIMCAP driver system settings.

14
testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC TRUE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM TRUE
#endif
/**
* @brief Enables the NAND subsystem.
*/

5
testhal/STM32/STM32F4xx/FSMC_SRAM/main.c
View File

@ -17,7 +17,6 @@
#include "ch.h"
#include "hal.h"
#include "hal_fsmc_sram.h"
#include "membench.h"
#include "memtest.h"
@ -173,8 +172,8 @@ int main(void) {
halInit();
chSysInit();
fsmcSramInit();
fsmcSramStart(&SRAMD4, &sram_cfg);
sramInit();
sramStart(&SRAMD4, &sram_cfg);
membench();
memtest();

18
testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h
View File

@ -26,8 +26,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0
@ -36,18 +36,16 @@
/*
* FSMC SRAM driver system settings.
*/
#define STM32_USE_FSMC_SRAM TRUE
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
#define STM32_SRAM_USE_FSMC_SRAM4 TRUE
#define STM32_SRAM_USE_SRAM1 FALSE
#define STM32_SRAM_USE_SRAM2 FALSE
#define STM32_SRAM_USE_SRAM3 FALSE
#define STM32_SRAM_USE_SRAM4 TRUE
/*
* FSMC SDRAM driver system settings.
*/
#define STM32_USE_FSMC_SDRAM FALSE
#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE
#define STM32_SDRAM_USE_SDRAM1 FALSE
#define STM32_SDRAM_USE_SDRAM2 FALSE
/*
* TIMCAP driver system settings.

14
testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F4xx/onewire/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F4xx/onewire/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

14
testhal/STM32/STM32L0xx/COMP/halconf_community.h
View File

@ -31,6 +31,20 @@
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/

4
testhal/STM32/STM32L0xx/COMP/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0

4
tools/templates/mcuconf_community.h
View File

@ -23,8 +23,8 @@
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0