Merge pull request #156 from wiml/k64_support
Kinetis K64 and PJRC Teensy3.5 support
This commit is contained in:
Fabien Poussin
GitHub
commit
dfd4708dbc
File diff suppressed because it is too large
Load Diff
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/*
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* Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
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* (C) 2017 Wim Lewis
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*
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* Permission is hereby granted, free of charge, to any person obtaining
|
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* a copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
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* SOFTWARE.
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*/
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/*
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* MK64FX512 memory setup.
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*/
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MEMORY
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{
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flash0 : org = 0x00000000, len = 0x400
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flash1 : org = 0x00000400, len = 0x10
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flash2 : org = 0x00000410, len = 512k - 0x410
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flash3 : org = 0x10000000, len = 128k /* FlexNVM */
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ram0 : org = 0x1FFF0000, len = 64k /* SRAM_L (code RAM) */
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ram1 : org = 0x20000000, len = 192k /* SRAM_U (data RAM) */
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ram2 : org = 0x14000000, len = 4k /* FlexRAM */
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ram3 : org = 0x00000000, len = 0
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ram4 : org = 0x00000000, len = 0
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ram5 : org = 0x00000000, len = 0
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ram6 : org = 0x00000000, len = 0
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ram7 : org = 0x00000000, len = 0
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}
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/* Flash region for the configuration bytes.*/
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SECTIONS
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{
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.cfmprotect : ALIGN(4) SUBALIGN(4)
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{
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KEEP(*(.cfmconfig))
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} > flash1
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}
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/* For each data/text section two region are defined, a virtual region
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and a load region (_LMA suffix).*/
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/* Flash region to be used for exception vectors.*/
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REGION_ALIAS("VECTORS_FLASH", flash0);
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REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
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/* Flash region to be used for constructors and destructors.*/
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REGION_ALIAS("XTORS_FLASH", flash2);
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REGION_ALIAS("XTORS_FLASH_LMA", flash2);
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/* Flash region to be used for code text.*/
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REGION_ALIAS("TEXT_FLASH", flash2);
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REGION_ALIAS("TEXT_FLASH_LMA", flash2);
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/* Flash region to be used for read only data.*/
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REGION_ALIAS("RODATA_FLASH", flash2);
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REGION_ALIAS("RODATA_FLASH_LMA", flash2);
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/* Flash region to be used for various.*/
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REGION_ALIAS("VARIOUS_FLASH", flash2);
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REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
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/* Flash region to be used for RAM(n) initialization data.*/
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REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
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/* RAM region to be used for Main stack. This stack accommodates the processing
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of all exceptions and interrupts.*/
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REGION_ALIAS("MAIN_STACK_RAM", ram1);
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/* RAM region to be used for the process stack. This is the stack used by
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the main() function.*/
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REGION_ALIAS("PROCESS_STACK_RAM", ram1);
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/* RAM region to be used for data segment.*/
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REGION_ALIAS("DATA_RAM", ram1);
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REGION_ALIAS("DATA_RAM_LMA", flash2);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram1);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram1);
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/* Generic rules inclusion.*/
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INCLUDE rules.ld
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@ -0,0 +1,12 @@
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# List of the ChibiOS generic K60x startup and CMSIS files.
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STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
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$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
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STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
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STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
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$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K60x \
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$(CHIBIOS)/os/common/ext/CMSIS/include \
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$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
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STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
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@ -0,0 +1,81 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
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(C) 2015 RedoX https://github.com/RedoXyde
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(C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
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(C) 2017 Wim Lewis
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
|
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file GCC/ARMCMx/K60x/cmparams.h
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* @brief ARM Cortex-M4 parameters for the Kinetis K60 family.
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*
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* @defgroup ARMCMx_K60 Kinetis K60 Specific Parameters
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* @ingroup ARMCMx_SPECIFIC
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* @details This file contains the Cortex-M4 specific parameters for the
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* Kinetis K60 family.
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* @{
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*/
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#ifndef _CMPARAMS_H_
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#define _CMPARAMS_H_
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/**
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* @brief Cortex core model.
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*/
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#define CORTEX_MODEL 4
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/**
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* @brief Systick unit presence.
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*/
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#define CORTEX_HAS_ST TRUE
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/**
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* @brief Floating Point unit presence.
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*/
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#define CORTEX_HAS_FPU TRUE
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/**
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* @brief Number of bits in priority masks.
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*/
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#define CORTEX_PRIORITY_BITS 4
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/**
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* @brief Number of interrupt vectors.
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* @note This number does not include the 16 system vectors and must be
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* rounded to a multiple of 8.
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*/
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#define CORTEX_NUM_VECTORS 88
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/* The following code is not processed when the file is included from an
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asm module.*/
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#if !defined(_FROM_ASM_)
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/* Including the device CMSIS header. Note, we are not using the definitions
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from this header because we need this file to be usable also from
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assembler source files. We verify that the info matches instead.*/
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#include "k64f.h"
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#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
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#error "CMSIS __NVIC_PRIO_BITS mismatch"
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#endif
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#endif /* !defined(_FROM_ASM_) */
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#endif /* _CMPARAMS_H_ */
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/** @} */
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@ -0,0 +1,218 @@
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/*
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ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
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Copyright (C) 2017 Wim Lewis
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Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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#define SOME_GPIO PAL_MODE_INPUT_PULLUP
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const PALConfig pal_default_config =
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{
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.ports = {
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{
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/*
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* PORTA setup.
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*
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* PTA0 -PTA3 -- bootloading coprocessor
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* PTA5 -- PIN25
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* PTA12-PTA13 -- PIN3-PIN4
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* PTA14-PTA16 -- PIN26-PIN28
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* PTA17 -- PIN39 / A20
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* PTA26 -- PIN42
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* PTA28 -- PIN40
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* PTA29 -- PIN41
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*
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* PTA18/19 crystal
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*/
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.port = IOPORT1,
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.pads = {
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/* PTA0-PTA3 -- bootloading coprocessor */
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PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_7,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_OUTPUT_PUSHPULL, /* PIN25 */
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED, /* PIN3 */
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PAL_MODE_OUTPUT_PUSHPULL, /* PIN4 */
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PAL_MODE_OUTPUT_PUSHPULL, /* PIN26 */
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PAL_MODE_UNCONNECTED, /* PIN27 */
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PAL_MODE_UNCONNECTED, /* PIN28 */
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PAL_MODE_UNCONNECTED, /* PIN39 */
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PAL_MODE_INPUT_ANALOG, /* XTAL0 */
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PAL_MODE_INPUT_ANALOG, /* XTAL0 */
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED, /* PIN42 */
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED, /* PIN40 */
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PAL_MODE_UNCONNECTED, /* PIN41 */
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PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED,
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},
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},
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{
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/*
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* PORTB setup.
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*
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* PTB0 - PIN16
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* PTB1 - PIN17
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* PTB2 - PIN19
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* PTB3 - PIN18
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* PTB10 - PIN31
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* PTB11 - PIN32
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* PTB16 - PIN0 - UART0_TX
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* PTB17 - PIN1 - UART0_RX
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* PTB18 - PIN32
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* PTB19 - PIN25
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*/
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.port = IOPORT2,
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.pads = {
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PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
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PAL_MODE_OUTPUT_PUSHPULL, SOME_GPIO, SOME_GPIO,
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PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED, SOME_GPIO, SOME_GPIO,
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PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
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PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3,
|
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PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, SOME_GPIO,
|
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SOME_GPIO, SOME_GPIO, SOME_GPIO,
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PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
},
|
||||
},
|
||||
{
|
||||
/*
|
||||
* PORTC setup.
|
||||
*
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||||
* PTC0 - PIN15
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* PTC1 - PIN22
|
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* PTC2 - PIN23
|
||||
* PTC3 - PIN9
|
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* PTC4 - PIN10
|
||||
* PTC5 - PIN13
|
||||
* PTC6 - PIN11
|
||||
* PTC7 - PIN12
|
||||
* PTC8 - PIN35
|
||||
* PTC9 - PIN36
|
||||
* PTC10 - PIN37
|
||||
* PTC11 - PIN38
|
||||
*/
|
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.port = IOPORT3,
|
||||
.pads = {
|
||||
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
|
||||
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
|
||||
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
|
||||
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
},
|
||||
},
|
||||
{
|
||||
/*
|
||||
* PORTD setup.
|
||||
*
|
||||
* PTD0 - PIN2
|
||||
* PTD1 - PIN14
|
||||
* PTD2 - PIN7
|
||||
* PTD3 - PIN8
|
||||
* PTD4 - PIN6
|
||||
* PTD5 - PIN20
|
||||
* PTD6 - PIN21
|
||||
* PTD7 - PIN5
|
||||
*/
|
||||
.port = IOPORT4,
|
||||
.pads = {
|
||||
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
|
||||
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
|
||||
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, SOME_GPIO,
|
||||
PAL_MODE_UNCONNECTED, SOME_GPIO, SOME_GPIO,
|
||||
SOME_GPIO, SOME_GPIO, SOME_GPIO,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
},
|
||||
},
|
||||
{
|
||||
/*
|
||||
* PORTE setup.
|
||||
*
|
||||
* PTE0 - PTE5 -- SDHC slot
|
||||
* PTE6 -- USB OTG power switch (Teensy3.6 only)
|
||||
* PTE10 - PIN56
|
||||
* PTE11 - PIN57
|
||||
* PTE24 - PIN33
|
||||
* PTE25 - PIN34
|
||||
* PTE26 - PIN24
|
||||
*/
|
||||
.port = IOPORT5,
|
||||
.pads = {
|
||||
PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4,
|
||||
PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4,
|
||||
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
|
||||
},
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
* @details This initialization must be performed just after stack setup
|
||||
* and before any other initialization.
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
k60x_clock_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @todo Add your board-specific code, if any.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
}
|
||||
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2017 Wim Lewis
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
/*
|
||||
* Setup for the PJRC Teensy 3.5 board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier
|
||||
*/
|
||||
#define BOARD_PJRC_TEENSY_3_5
|
||||
#define BOARD_NAME "PJRC Teensy 3.5"
|
||||
|
||||
/* External 16 MHz crystal */
|
||||
#define KINETIS_XTAL_FREQUENCY 16000000UL
|
||||
|
||||
/* Use internal capacitors for the crystal */
|
||||
#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
|
||||
|
||||
/*
|
||||
* MCU type
|
||||
*/
|
||||
#define K64FX512
|
||||
|
||||
/*
|
||||
* IO pin assignments
|
||||
*/
|
||||
#define TEENSY_PIN25 5
|
||||
#define TEENSY_PIN3 12
|
||||
#define TEENSY_PIN4 13
|
||||
#define TEENSY_PIN26 14
|
||||
#define TEENSY_PIN27 15
|
||||
#define TEENSY_PIN28 16
|
||||
#define TEENSY_PIN39 17
|
||||
#define TEENSY_PIN42 26
|
||||
#define TEENSY_PIN40 28
|
||||
#define TEENSY_PIN41 29
|
||||
|
||||
#define TEENSY_PIN25_IOPORT IOPORT1
|
||||
#define TEENSY_PIN3_IOPORT IOPORT1
|
||||
#define TEENSY_PIN4_IOPORT IOPORT1
|
||||
#define TEENSY_PIN26_IOPORT IOPORT1
|
||||
#define TEENSY_PIN27_IOPORT IOPORT1
|
||||
#define TEENSY_PIN28_IOPORT IOPORT1
|
||||
#define TEENSY_PIN39_IOPORT IOPORT1
|
||||
#define TEENSY_PIN42_IOPORT IOPORT1
|
||||
#define TEENSY_PIN40_IOPORT IOPORT1
|
||||
#define TEENSY_PIN41_IOPORT IOPORT1
|
||||
|
||||
#define TEENSY_PIN16 0
|
||||
#define TEENSY_PIN17 1
|
||||
#define TEENSY_PIN19 2
|
||||
#define TEENSY_PIN18 3
|
||||
#define TEENSY_PIN49 4
|
||||
#define TEENSY_PIN50 5
|
||||
#define TEENSY_PIN31 10
|
||||
#define TEENSY_PIN32 11
|
||||
#define TEENSY_PIN0 16
|
||||
#define TEENSY_PIN1 17
|
||||
#define TEENSY_PIN29 18
|
||||
#define TEENSY_PIN30 19
|
||||
#define TEENSY_PIN43 20
|
||||
#define TEENSY_PIN46 21
|
||||
#define TEENSY_PIN44 22
|
||||
#define TEENSY_PIN45 23
|
||||
|
||||
#define TEENSY_PIN16_IOPORT IOPORT2
|
||||
#define TEENSY_PIN17_IOPORT IOPORT2
|
||||
#define TEENSY_PIN19_IOPORT IOPORT2
|
||||
#define TEENSY_PIN18_IOPORT IOPORT2
|
||||
#define TEENSY_PIN49_IOPORT IOPORT2
|
||||
#define TEENSY_PIN50_IOPORT IOPORT2
|
||||
#define TEENSY_PIN31_IOPORT IOPORT2
|
||||
#define TEENSY_PIN32_IOPORT IOPORT2
|
||||
#define TEENSY_PIN0_IOPORT IOPORT2
|
||||
#define TEENSY_PIN1_IOPORT IOPORT2
|
||||
#define TEENSY_PIN29_IOPORT IOPORT2
|
||||
#define TEENSY_PIN30_IOPORT IOPORT2
|
||||
#define TEENSY_PIN43_IOPORT IOPORT2
|
||||
#define TEENSY_PIN46_IOPORT IOPORT2
|
||||
#define TEENSY_PIN44_IOPORT IOPORT2
|
||||
#define TEENSY_PIN45_IOPORT IOPORT2
|
||||
|
||||
#define TEENSY_PIN15 0
|
||||
#define TEENSY_PIN22 1
|
||||
#define TEENSY_PIN23 2
|
||||
#define TEENSY_PIN9 3
|
||||
#define TEENSY_PIN10 4
|
||||
#define TEENSY_PIN13 5
|
||||
#define TEENSY_PIN11 6
|
||||
#define TEENSY_PIN12 7
|
||||
#define TEENSY_PIN35 8
|
||||
#define TEENSY_PIN36 9
|
||||
#define TEENSY_PIN37 10
|
||||
#define TEENSY_PIN38 11
|
||||
|
||||
#define TEENSY_PIN15_IOPORT IOPORT3
|
||||
#define TEENSY_PIN22_IOPORT IOPORT3
|
||||
#define TEENSY_PIN23_IOPORT IOPORT3
|
||||
#define TEENSY_PIN9_IOPORT IOPORT3
|
||||
#define TEENSY_PIN10_IOPORT IOPORT3
|
||||
#define TEENSY_PIN13_IOPORT IOPORT3
|
||||
#define TEENSY_PIN11_IOPORT IOPORT3
|
||||
#define TEENSY_PIN12_IOPORT IOPORT3
|
||||
#define TEENSY_PIN35_IOPORT IOPORT3
|
||||
#define TEENSY_PIN36_IOPORT IOPORT3
|
||||
#define TEENSY_PIN37_IOPORT IOPORT3
|
||||
#define TEENSY_PIN38_IOPORT IOPORT3
|
||||
|
||||
#define TEENSY_PIN2 0
|
||||
#define TEENSY_PIN14 1
|
||||
#define TEENSY_PIN7 2
|
||||
#define TEENSY_PIN8 3
|
||||
#define TEENSY_PIN6 4
|
||||
#define TEENSY_PIN20 5
|
||||
#define TEENSY_PIN21 6
|
||||
#define TEENSY_PIN5 7
|
||||
#define TEENSY_PIN47 8
|
||||
#define TEENSY_PIN48 9
|
||||
#define TEENSY_PIN55 11
|
||||
#define TEENSY_PIN53 12
|
||||
#define TEENSY_PIN52 13
|
||||
#define TEENSY_PIN51 14
|
||||
#define TEENSY_PIN54 15
|
||||
|
||||
#define TEENSY_PIN2_IOPORT IOPORT4
|
||||
#define TEENSY_PIN14_IOPORT IOPORT4
|
||||
#define TEENSY_PIN7_IOPORT IOPORT4
|
||||
#define TEENSY_PIN8_IOPORT IOPORT4
|
||||
#define TEENSY_PIN6_IOPORT IOPORT4
|
||||
#define TEENSY_PIN20_IOPORT IOPORT4
|
||||
#define TEENSY_PIN21_IOPORT IOPORT4
|
||||
#define TEENSY_PIN5_IOPORT IOPORT4
|
||||
#define TEENSY_PIN47_IOPORT IOPORT4
|
||||
#define TEENSY_PIN48_IOPORT IOPORT4
|
||||
#define TEENSY_PIN55_IOPORT IOPORT4
|
||||
#define TEENSY_PIN53_IOPORT IOPORT4
|
||||
#define TEENSY_PIN52_IOPORT IOPORT4
|
||||
#define TEENSY_PIN51_IOPORT IOPORT4
|
||||
#define TEENSY_PIN54_IOPORT IOPORT4
|
||||
|
||||
#define TEENSY_PIN56 10
|
||||
#define TEENSY_PIN57 11
|
||||
#define TEENSY_PIN33 24
|
||||
#define TEENSY_PIN34 25
|
||||
#define TEENSY_PIN24 26
|
||||
|
||||
#define TEENSY_PIN56_IOPORT IOPORT5
|
||||
#define TEENSY_PIN57_IOPORT IOPORT5
|
||||
#define TEENSY_PIN33_IOPORT IOPORT5
|
||||
#define TEENSY_PIN34_IOPORT IOPORT5
|
||||
#define TEENSY_PIN24_IOPORT IOPORT5
|
||||
|
||||
#define LINE_PIN1 PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
|
||||
#define LINE_PIN2 PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
|
||||
#define LINE_PIN3 PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
|
||||
#define LINE_PIN4 PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
|
||||
#define LINE_PIN5 PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
|
||||
#define LINE_PIN6 PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
|
||||
#define LINE_PIN7 PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
|
||||
#define LINE_PIN8 PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
|
||||
#define LINE_PIN9 PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
|
||||
#define LINE_PIN10 PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
|
||||
#define LINE_PIN11 PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
|
||||
#define LINE_PIN12 PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
|
||||
#define LINE_PIN13 PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
|
||||
#define LINE_PIN14 PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
|
||||
#define LINE_PIN15 PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
|
||||
#define LINE_PIN16 PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
|
||||
#define LINE_PIN17 PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
|
||||
#define LINE_PIN18 PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
|
||||
#define LINE_PIN19 PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
|
||||
#define LINE_PIN20 PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
|
||||
#define LINE_PIN21 PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
|
||||
#define LINE_PIN22 PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
|
||||
#define LINE_PIN23 PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
|
||||
#define LINE_PIN24 PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
|
||||
#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
|
||||
#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
|
||||
#define LINE_PIN26 PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
|
||||
#define LINE_PIN27 PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
|
||||
#define LINE_PIN28 PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
|
||||
#define LINE_PIN29 PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
|
||||
#define LINE_PIN30 PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
|
||||
#define LINE_PIN31 PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
|
||||
#define LINE_PIN32 PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
|
||||
#define LINE_PIN33 PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
|
||||
#define LINE_PIN34 PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34)
|
||||
#define LINE_PIN35 PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35)
|
||||
#define LINE_PIN36 PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36)
|
||||
#define LINE_PIN37 PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37)
|
||||
#define LINE_PIN38 PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38)
|
||||
#define LINE_PIN39 PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39)
|
||||
#define LINE_PIN40 PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40)
|
||||
#define LINE_PIN41 PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41)
|
||||
#define LINE_PIN42 PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42)
|
||||
#define LINE_PIN43 PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43)
|
||||
#define LINE_PIN44 PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44)
|
||||
#define LINE_PIN45 PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45)
|
||||
#define LINE_PIN46 PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46)
|
||||
#define LINE_PIN47 PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47)
|
||||
#define LINE_PIN48 PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48)
|
||||
#define LINE_PIN49 PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49)
|
||||
#define LINE_PIN50 PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50)
|
||||
#define LINE_PIN51 PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN51)
|
||||
#define LINE_PIN52 PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52)
|
||||
#define LINE_PIN53 PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53)
|
||||
#define LINE_PIN54 PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54)
|
||||
#define LINE_PIN55 PAL_LINE(TEENSY_PIN55_IOPORT, TEENSY_PIN55)
|
||||
#define LINE_PIN56 PAL_LINE(TEENSY_PIN56_IOPORT, TEENSY_PIN56)
|
||||
#define LINE_PIN57 PAL_LINE(TEENSY_PIN57_IOPORT, TEENSY_PIN57)
|
||||
|
||||
#define LINE_LED LINE_PIN13
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
# List of all the board related files.
|
||||
BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
|
||||
Copyright (C) 2017 Fabio Utzig
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/hal_lld.c
|
||||
* @brief HAL Driver subsystem low level driver source template.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __CC_ARM
|
||||
__attribute__ ((section(".ARM.__at_0x400")))
|
||||
#else
|
||||
__attribute__ ((used,section(".cfmconfig")))
|
||||
#endif
|
||||
const uint8_t _cfm[0x10] = {
|
||||
0xFF, /* NV_BACKKEY3: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY2: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY1: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY0: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY7: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY6: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY5: KEY=0xFF */
|
||||
0xFF, /* NV_BACKKEY4: KEY=0xFF */
|
||||
0xFF, /* NV_FPROT3: PROT=0xFF */
|
||||
0xFF, /* NV_FPROT2: PROT=0xFF */
|
||||
0xFF, /* NV_FPROT1: PROT=0xFF */
|
||||
0xFF, /* NV_FPROT0: PROT=0xFF */
|
||||
0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
|
||||
0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
|
||||
NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
|
||||
0xFF,
|
||||
0xFF
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level HAL driver initialization.
|
||||
* @todo Use a macro to define the system clock frequency.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void hal_lld_init(void) {
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief K60x clock initialization.
|
||||
* @note All the involved constants come from the file @p board.h.
|
||||
* @note This function is meant to be invoked early during the system
|
||||
* initialization, it is usually invoked from the file
|
||||
* @p board.c.
|
||||
* @todo This function needs to be more generic.
|
||||
* @todo This function should be combined with the nearly-identical
|
||||
* functions in other Kinetis ports.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
void k60x_clock_init(void) {
|
||||
#if !KINETIS_NO_INIT
|
||||
|
||||
/* Disable the watchdog */
|
||||
WDOG->UNLOCK = 0xC520;
|
||||
WDOG->UNLOCK = 0xD928;
|
||||
__asm__("nop");
|
||||
WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
|
||||
|
||||
SIM->SCGC5 |= SIM_SCGC5_PORTA |
|
||||
SIM_SCGC5_PORTB |
|
||||
SIM_SCGC5_PORTC |
|
||||
SIM_SCGC5_PORTD |
|
||||
SIM_SCGC5_PORTE;
|
||||
|
||||
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
|
||||
/* This is the default mode at reset. */
|
||||
|
||||
/* Configure FEI mode */
|
||||
MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
|
||||
(KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
|
||||
|
||||
/* Set clock dividers */
|
||||
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
|
||||
SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
|
||||
SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
|
||||
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
|
||||
|
||||
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
|
||||
|
||||
uint32_t ratio, frdiv;
|
||||
uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
|
||||
uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
|
||||
uint8_t i;
|
||||
|
||||
/* EXTAL0 and XTAL0 */
|
||||
PORTA->PCR[18] = 0;
|
||||
PORTA->PCR[19] = 0;
|
||||
|
||||
/*
|
||||
* Start in FEI mode
|
||||
*/
|
||||
|
||||
/* Internal capacitors for crystal */
|
||||
#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
|
||||
OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
|
||||
#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
|
||||
/* Disable the internal capacitors */
|
||||
OSC0->CR = 0;
|
||||
#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
|
||||
|
||||
/* TODO: need to add more flexible calculation, specially regarding
|
||||
* divisors which may not be available depending on the XTAL
|
||||
* frequency, which would required other registers to be modified.
|
||||
*/
|
||||
/* Enable OSC, low power mode */
|
||||
if (KINETIS_XTAL_FREQUENCY > 8000000UL)
|
||||
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(2);
|
||||
else
|
||||
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(1);
|
||||
|
||||
frdiv = 7;
|
||||
ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
|
||||
for (i = 0; i < ratio_quantity; ++i) {
|
||||
if (ratio == ratios[i]) {
|
||||
frdiv = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Switch to crystal as clock source, FLL input of 31.25 KHz */
|
||||
MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
|
||||
|
||||
/* Wait for crystal oscillator to begin */
|
||||
while (!(MCG->S & MCG_S_OSCINIT0));
|
||||
|
||||
/* Wait for the FLL to use the oscillator */
|
||||
while (MCG->S & MCG_S_IREFST);
|
||||
|
||||
/* Wait for the MCGOUTCLK to use the oscillator */
|
||||
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
|
||||
|
||||
/*
|
||||
* Now in FBE mode
|
||||
*/
|
||||
#define KINETIS_PLLIN_FREQUENCY 2000000UL
|
||||
/*
|
||||
* Config PLL input for 2 MHz
|
||||
* TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
|
||||
*/
|
||||
MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
|
||||
|
||||
/*
|
||||
* Config PLL output to match KINETIS_SYSCLK_FREQUENCY
|
||||
* TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
|
||||
*/
|
||||
for(i = 24; i < 56; i++)
|
||||
{
|
||||
if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
|
||||
{
|
||||
/* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
|
||||
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(i>=56) /* Config PLL for 96 MHz output as default setting */
|
||||
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
|
||||
|
||||
/* Wait for PLL to start using crystal as its input, and to lock */
|
||||
while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
|
||||
|
||||
/*
|
||||
* Now in PBE mode
|
||||
*/
|
||||
/* Set the PLL dividers for the different clocks */
|
||||
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
|
||||
SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
|
||||
SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
|
||||
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
|
||||
SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_IRC48M; /* FIXME ? Why this? */
|
||||
|
||||
/* Switch to PLL as clock source */
|
||||
MCG->C1 = MCG_C1_CLKS(0);
|
||||
|
||||
/* Wait for PLL clock to be used */
|
||||
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
|
||||
|
||||
/*
|
||||
* Now in PEE mode
|
||||
*/
|
||||
#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
|
||||
#error Unimplemented KINETIS_MCG_MODE
|
||||
#endif /* KINETIS_MCG_MODE == ... */
|
||||
|
||||
#endif /* !KINETIS_NO_INIT */
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file K60x/hal_lld.h
|
||||
* @brief Kinetis K60x HAL subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HAL_LLD_H_
|
||||
#define HAL_LLD_H_
|
||||
|
||||
#include "kinetis_registry.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Defines the support for realtime counters in the HAL.
|
||||
*/
|
||||
#define HAL_IMPLEMENTS_COUNTERS FALSE /* FIXME check */
|
||||
|
||||
/**
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
|
||||
#define PLATFORM_NAME "Kinetis"
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Internal clock sources
|
||||
* @{
|
||||
*/
|
||||
#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
|
||||
#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
|
||||
/** @} */
|
||||
|
||||
#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
|
||||
#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
|
||||
#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
|
||||
#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
|
||||
#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
|
||||
#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
|
||||
#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
|
||||
#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Disables the MCG/system clock initialization in the HAL.
|
||||
*/
|
||||
#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
|
||||
#define KINETIS_NO_INIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCG mode selection.
|
||||
*/
|
||||
#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
|
||||
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCU PLL clock frequency.
|
||||
*/
|
||||
#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
|
||||
#define KINETIS_PLLCLK_FREQUENCY 96000000UL
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clock divider for core/system clocks (OUTDIV1).
|
||||
* @note The allowed range is 1..16
|
||||
* @note The default value is calculated for a 48 MHz system clock
|
||||
* from a 96 MHz PLL output.
|
||||
*/
|
||||
#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
|
||||
#if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
|
||||
#define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
|
||||
#else
|
||||
#define KINETIS_CLKDIV1_OUTDIV1 2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clock divider for bus clock (OUTDIV2).
|
||||
* @note The allowed range is 1..16
|
||||
* @note The default value is calculated for a 48 MHz bus clock
|
||||
* from a 96 MHz PLL output.
|
||||
*/
|
||||
#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
|
||||
#if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
|
||||
#define KINETIS_CLKDIV1_OUTDIV2 (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
|
||||
#elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
|
||||
#define KINETIS_CLKDIV1_OUTDIV2 KINETIS_CLKDIV1_OUTDIV1
|
||||
#else
|
||||
#define KINETIS_CLKDIV1_OUTDIV2 2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clock divider for flash clock (OUTDIV4).
|
||||
* @note The allowed range is 1..16
|
||||
* @note The default value is calculated for a 24 MHz flash clock
|
||||
* from a 96 MHz PLL output
|
||||
*/
|
||||
#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
|
||||
#if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
|
||||
#define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
|
||||
#elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
|
||||
#define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_CLKDIV1_OUTDIV1*2)
|
||||
#else
|
||||
#define KINETIS_CLKDIV1_OUTDIV4 4
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief FLL DCO tuning enable for 32.768 kHz reference.
|
||||
* @note Set to 1 for fine-tuning DCO for maximum frequency with
|
||||
* a 32.768 kHz reference.
|
||||
* @note The default value is for a 32.768 kHz external crystal.
|
||||
*/
|
||||
#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
|
||||
#define KINETIS_MCG_FLL_DMX32 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief FLL DCO range selection.
|
||||
* @note The allowed range is 0...3.
|
||||
* @note The default value is calculated for 48 MHz FLL output
|
||||
* from a 32.768 kHz external crystal.
|
||||
* (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
|
||||
*
|
||||
*/
|
||||
#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
|
||||
#define KINETIS_MCG_FLL_DRS 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCU system/core clock frequency.
|
||||
*/
|
||||
#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
|
||||
#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCU bus clock frequency.
|
||||
*/
|
||||
#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
|
||||
#define KINETIS_BUSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCU flash clock frequency.
|
||||
*/
|
||||
#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
|
||||
#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(KINETIS_SYSCLK_FREQUENCY)
|
||||
#error KINETIS_SYSCLK_FREQUENCY must be defined
|
||||
#endif
|
||||
|
||||
#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
|
||||
#error KINETIS_SYSCLK_FREQUENCY out of range
|
||||
#endif
|
||||
|
||||
#if !defined(KINETIS_BUSCLK_FREQUENCY)
|
||||
#error KINETIS_BUSCLK_FREQUENCY must be defined
|
||||
#endif
|
||||
|
||||
#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
|
||||
#error KINETIS_BUSCLK_FREQUENCY out of range
|
||||
#endif
|
||||
|
||||
#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
|
||||
#error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
|
||||
KINETIS_SYSCLK_FREQUENCY
|
||||
#endif
|
||||
|
||||
#if !defined(KINETIS_FLASHCLK_FREQUENCY)
|
||||
#error KINETIS_FLASHCLK_FREQUENCY must be defined
|
||||
#endif
|
||||
|
||||
#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
|
||||
#error KINETIS_FLASHCLK_FREQUENCY out of range
|
||||
#endif
|
||||
|
||||
#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
|
||||
#error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
|
||||
KINETIS_SYSCLK_FREQUENCY
|
||||
#endif
|
||||
|
||||
#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
|
||||
KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
|
||||
#error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
|
||||
#endif
|
||||
|
||||
#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
|
||||
KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
|
||||
#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
|
||||
#endif
|
||||
|
||||
#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
|
||||
KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
|
||||
#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
|
||||
#endif
|
||||
|
||||
#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
|
||||
#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
|
||||
#endif
|
||||
|
||||
#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
|
||||
#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Type representing a system clock frequency.
|
||||
*/
|
||||
typedef uint32_t halclock_t;
|
||||
|
||||
/**
|
||||
* @brief Type of the realtime free counter value.
|
||||
*/
|
||||
typedef uint32_t halrtcnt_t;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Returns the current value of the system free running counter.
|
||||
* @note This service is implemented by returning the content of the
|
||||
* DWT_CYCCNT register.
|
||||
*
|
||||
* @return The value of the system free running counter of
|
||||
* type halrtcnt_t.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define hal_lld_get_counter_value() 0
|
||||
|
||||
/**
|
||||
* @brief Realtime counter frequency.
|
||||
* @note The DWT_CYCCNT register is incremented directly by the system
|
||||
* clock so this function returns STM32_HCLK.
|
||||
*
|
||||
* @return The realtime counter frequency of type halclock_t.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define hal_lld_get_counter_frequency() 0
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#include "nvic.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void hal_lld_init(void);
|
||||
void k60x_clock_init(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2014 Derek Mulcahy
|
||||
(C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
|
||||
(C) 2017 Wim Lewis
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file K60x/kinetis_registry.h
|
||||
* @brief K60x capabilities registry.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef KINETIS_REGISTRY_H_
|
||||
#define KINETIS_REGISTRY_H_
|
||||
|
||||
#if !defined(K60x) || defined(__DOXYGEN__)
|
||||
#define K60x /* Processor family */
|
||||
#endif
|
||||
|
||||
#if defined(K64FX512) || defined(K64FN1M0) || defined(__DOXYGEN__)
|
||||
#define K64F /* Sub-family */
|
||||
#else
|
||||
#error "Unknown processor sub-family"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name K60x capabilities
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
/* K64F */
|
||||
/*===========================================================================*/
|
||||
#if defined(K64F) || defined(__DOXYGEN__)
|
||||
|
||||
/**
|
||||
* @brief Maximum system and core clock (f_SYS) frequency.
|
||||
*/
|
||||
#define KINETIS_SYSCLK_MAX 120000000L
|
||||
|
||||
/**
|
||||
* @brief Maximum bus clock (f_BUS) frequency.
|
||||
*/
|
||||
#define KINETIS_BUSCLK_MAX 60000000L
|
||||
|
||||
/**
|
||||
* @brief Maximum flash clock (f_FLASH) frequency.
|
||||
*/
|
||||
#define KINETIS_FLASHCLK_MAX 25000000L
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define KINETIS_HAS_ADC0 TRUE
|
||||
#define KINETIS_ADC0_IRQ_VECTOR VectorDC
|
||||
#define KINETIS_HAS_ADC1 TRUE
|
||||
#define KINETIS_ADC1_IRQ_VECTOR Vector164
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define KINETIS_HAS_DAC0 TRUE
|
||||
#define KINETIS_DAC0_IRQ_VECTOR Vector120
|
||||
#define KINETIS_HAS_DAC1 TRUE
|
||||
#define KINETIS_DAC1_IRQ_VECTOR Vector160
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define KINETIS_DMA0_IRQ_VECTOR Vector40
|
||||
#define KINETIS_DMA1_IRQ_VECTOR Vector44
|
||||
#define KINETIS_DMA2_IRQ_VECTOR Vector48
|
||||
#define KINETIS_DMA3_IRQ_VECTOR Vector4C
|
||||
#define KINETIS_DMA4_IRQ_VECTOR Vector50
|
||||
#define KINETIS_DMA5_IRQ_VECTOR Vector54
|
||||
#define KINETIS_DMA6_IRQ_VECTOR Vector58
|
||||
#define KINETIS_DMA7_IRQ_VECTOR Vector5C
|
||||
#define KINETIS_DMA8_IRQ_VECTOR Vector60
|
||||
#define KINETIS_DMA9_IRQ_VECTOR Vector64
|
||||
#define KINETIS_DMA10_IRQ_VECTOR Vector68
|
||||
#define KINETIS_DMA11_IRQ_VECTOR Vector6C
|
||||
#define KINETIS_DMA12_IRQ_VECTOR Vector70
|
||||
#define KINETIS_DMA13_IRQ_VECTOR Vector74
|
||||
#define KINETIS_DMA14_IRQ_VECTOR Vector78
|
||||
#define KINETIS_DMA15_IRQ_VECTOR Vector7C
|
||||
#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
|
||||
#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector80
|
||||
|
||||
/* EXT attributes.*/
|
||||
#define KINETIS_PORTA_IRQ_VECTOR Vector12C
|
||||
#define KINETIS_PORTB_IRQ_VECTOR Vector130
|
||||
#define KINETIS_PORTC_IRQ_VECTOR Vector134
|
||||
#define KINETIS_PORTD_IRQ_VECTOR Vector138
|
||||
#define KINETIS_PORTE_IRQ_VECTOR Vector13C
|
||||
#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
|
||||
#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
|
||||
#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define KINETIS_HAS_I2C0 TRUE
|
||||
#define KINETIS_I2C0_IRQ_VECTOR VectorA0
|
||||
#define KINETIS_HAS_I2C1 TRUE
|
||||
#define KINETIS_I2C1_IRQ_VECTOR VectorA4
|
||||
#define KINETIS_HAS_I2C2 TRUE
|
||||
#define KINETIS_I2C2_IRQ_VECTOR Vector168
|
||||
|
||||
/* Serial attributes.*/
|
||||
#define KINETIS_HAS_SERIAL0 TRUE
|
||||
#define KINETIS_SERIAL0_IRQ_VECTOR VectorBC
|
||||
#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorC0
|
||||
#define KINETIS_SERIAL0_IS_LPUART FALSE
|
||||
#define KINETIS_SERIAL0_IS_UARTLP FALSE
|
||||
|
||||
#define KINETIS_HAS_SERIAL1 TRUE
|
||||
#define KINETIS_SERIAL1_IRQ_VECTOR VectorC4
|
||||
#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR VectorC8
|
||||
#define KINETIS_SERIAL1_IS_LPUART FALSE
|
||||
|
||||
#define KINETIS_HAS_SERIAL2 TRUE
|
||||
#define KINETIS_SERIAL2_IRQ_VECTOR VectorCC
|
||||
#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR VectorD0
|
||||
|
||||
#define KINETIS_HAS_SERIAL3 TRUE
|
||||
#define KINETIS_SERIAL3_IRQ_VECTOR VectorD4
|
||||
#define KINETIS_SERIAL3_ERROR_IRQ_VECTOR VectorD8
|
||||
|
||||
#define KINETIS_HAS_SERIAL4 TRUE
|
||||
#define KINETIS_SERIAL4_IRQ_VECTOR Vector148
|
||||
#define KINETIS_SERIAL4_ERROR_IRQ_VECTOR Vector14C
|
||||
|
||||
#define KINETIS_HAS_SERIAL5 TRUE
|
||||
#define KINETIS_SERIAL5_IRQ_VECTOR Vector150
|
||||
#define KINETIS_SERIAL5_ERROR_IRQ_VECTOR Vector154
|
||||
|
||||
#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define KINETIS_HAS_SPI0 TRUE
|
||||
#define KINETIS_SPI0_IRQ_VECTOR VectorA8
|
||||
#define KINETIS_HAS_SPI1 TRUE
|
||||
#define KINETIS_SPI1_IRQ_VECTOR VectorAC
|
||||
#define KINETIS_HAS_SPI2 TRUE
|
||||
#define KINETIS_SPI2_IRQ_VECTOR Vector144
|
||||
|
||||
/* FlexTimer attributes.*/
|
||||
#define KINETIS_FTM0_CHANNELS 8
|
||||
#define KINETIS_FTM1_CHANNELS 2
|
||||
#define KINETIS_FTM2_CHANNELS 2
|
||||
#define KINETIS_FTM3_CHANNELS 8
|
||||
|
||||
#define KINETIS_FTM0_IRQ_VECTOR VectorE8
|
||||
#define KINETIS_FTM1_IRQ_VECTOR VectorEC
|
||||
#define KINETIS_FTM2_IRQ_VECTOR VectorF0
|
||||
#define KINETIS_HAS_FTM2 TRUE
|
||||
#define KINETIS_FTM3_IRQ_VECTOR Vector15C
|
||||
#define KINETIS_HAS_FTM3 TRUE
|
||||
|
||||
/* GPT attributes.*/
|
||||
#define KINETIS_HAS_PIT0 TRUE
|
||||
#define KINETIS_PIT0_IRQ_VECTOR Vector100
|
||||
#define KINETIS_HAS_PIT1 TRUE
|
||||
#define KINETIS_PIT1_IRQ_VECTOR Vector104
|
||||
#define KINETIS_HAS_PIT2 TRUE
|
||||
#define KINETIS_PIT2_IRQ_VECTOR Vector108
|
||||
#define KINETIS_HAS_PIT3 TRUE
|
||||
#define KINETIS_PIT3_IRQ_VECTOR Vector10C
|
||||
#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define KINETIS_HAS_USB TRUE
|
||||
#define KINETIS_USB_IRQ_VECTOR Vector114
|
||||
#define KINETIS_USB0_IS_USBOTG TRUE
|
||||
#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
|
||||
|
||||
/* SDHC (SDC, MMC, SDIO) attributes */
|
||||
#define KINETIS_HAS_SDHC TRUE
|
||||
#define KINETIS_SDHC_IRQ_VECTOR Vector184
|
||||
|
||||
/* LPTMR attributes.*/
|
||||
#define KINETIS_LPTMR0_IRQ_VECTOR Vector128
|
||||
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
#endif /* KINETIS_REGISTRY_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
# List of all platform files.
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
|
||||
# ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_spi_lld.c \
|
||||
# ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_pwm_lld.c \
|
||||
# ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
|
||||
Loading…
Reference in New Issue