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Fixed bug #1197. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14921 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-10-20 07:25:25 +00:00
parent f3ed688f1a
commit 0778b904cb
2 changed files with 42 additions and 5 deletions
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45
os/hal/ports/STM32/STM32L4xx+/hal_lld.h
View File

@ -1371,7 +1371,7 @@
#endif #endif
/** /**
* @brief PLLs input clock frequency. * @brief PLL input clock frequency.
*/ */
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) #define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
@ -1471,6 +1471,44 @@
#include "stm32_apb1.inc" #include "stm32_apb1.inc"
#include "stm32_apb2.inc" #include "stm32_apb2.inc"
/**
* @brief PLLSAI1 input clock frequency.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1CLKIN (STM32_HSECLK / STM32_PLLSAI1M_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_MSI
#define STM32_PLLSAI1CLKIN (STM32_MSICLK / STM32_PLLSAI1M_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
#define STM32_PLLSAI1CLKIN (STM32_HSI16CLK / STM32_PLLSAI1M_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
#define STM32_PLLSAI1CLKIN 0
#else
#error "invalid STM32_PLLSRC value specified"
#endif
/**
* @brief PLLSAI2 input clock frequency.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2CLKIN (STM32_HSECLK / STM32_PLLSAI2M_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_MSI
#define STM32_PLLSAI2CLKIN (STM32_MSICLK / STM32_PLLSAI2M_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
#define STM32_PLLSAI2CLKIN (STM32_HSI16CLK / STM32_PLLSAI2M_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
#define STM32_PLLSAI2CLKIN 0
#else
#error "invalid STM32_PLLSRC value specified"
#endif
/* /*
* PLLSAI1 enable check. * PLLSAI1 enable check.
*/ */
@ -1561,10 +1599,7 @@
*/ */
#define STM32_PLLSAI2REN (1 << 24) #define STM32_PLLSAI2REN (1 << 24)
/* Inclusion of PLLSAI-related checks and calculations, all PLLs share the /* Inclusion of PLLSAI-related checks and calculations.*/
same clock source so enforcing this condition.*/
#define STM32_PLLSAI1CLKIN STM32_PLLCLKIN
#define STM32_PLLSAI2CLKIN STM32_PLLCLKIN
#include <stm32_pllsai1.inc> #include <stm32_pllsai1.inc>
#include <stm32_pllsai2.inc> #include <stm32_pllsai2.inc>

2
readme.txt
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@ -84,6 +84,8 @@
- NEW: EFL driver and demo for STM32F3xx. - NEW: EFL driver and demo for STM32F3xx.
- NEW: New unit test subsystem under /os/test. Now it is officially - NEW: New unit test subsystem under /os/test. Now it is officially
ChibiOS/TEST. ChibiOS/TEST.
- FIX: Fixed PLLSA1x input frequency calculated incorrectly (bug #1197)
(TBP to 21.6.1).
- FIX: Fixed ARMCMx port, MPU not enabled when PORT_ENABLE_GUARD_PAGES is set - FIX: Fixed ARMCMx port, MPU not enabled when PORT_ENABLE_GUARD_PAGES is set
(bug #1195)(backported to 20.3.4)(TBP to 21.6.1). (bug #1195)(backported to 20.3.4)(TBP to 21.6.1).
- FIX: Fixed removed incorrect ADCv4 checks for MONEN (bug #1194) - FIX: Fixed removed incorrect ADCv4 checks for MONEN (bug #1194)