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Fixed bugs #969 and #970. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12205 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2018-07-28 09:42:11 +00:00
parent cc826010ae
commit 11db006b0f
14 changed files with 21 additions and 14 deletions
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2
demos/STM32/RT-STM32L432KC-NUCLEO32/mcuconf.h
View File

@ -89,7 +89,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

2
demos/STM32/RT-STM32L476-DISCOVERY/cfg/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

2
demos/STM32/RT-STM32L476RG-NUCLEO64/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

3
os/hal/ports/STM32/STM32L4xx/hal_lld.c
View File

@ -92,6 +92,9 @@ static void hal_lld_backup_domain_init(void) {
RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* HAL_USE_RTC */
/* Low speed output mode.*/
RCC->BDCR |= STM32_LSCOSEL;
}
/*===========================================================================*/

6
os/hal/ports/STM32/STM32L4xx/hal_lld.h
View File

@ -291,7 +291,7 @@
#define STM32_SWPMI1SEL_HSI16 (1 << 30) /**< SWPMI1 source is HSI16. */
#define STM32_DFSDMSEL_MASK (1 << 31) /**< DFSDMSEL mask. */
#define STM32_DFSDMSEL_PCLK1 (0 << 31) /**< DFSDM source is PCLK1. */
#define STM32_DFSDMSEL_PCLK2 (0 << 31) /**< DFSDM source is PCLK2. */
#define STM32_DFSDMSEL_SYSCLK (1 << 31) /**< DFSDM source is SYSCLK. */
/** @} */
@ -2130,8 +2130,8 @@
/**
* @brief DFSDM clock frequency.
*/
#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_DFSDMCLK STM32_PCLK1
#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK2) || defined(__DOXYGEN__)
#define STM32_DFSDMCLK STM32_PCLK2
#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
#define STM32_DFSDMCLK STM32_SYSCLK
#else

4
readme.txt
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@ -141,6 +141,10 @@
- EX: Updated LIS302DL to 1.1.0 (backported to 18.2.1).
- EX: Updated LPS25H to 1.1.0 (backported to 18.2.1).
- EX: Updated LSM303DLHC to 1.1.0 (backported to 18.2.1).
- HAL: Fixed option STM32_LSCOSEL not written in STM32L4 HAL (bug #970)
(backported to 18.2.2 and 17.6.5).
- HAL: Fixed invalid DFSDM1SEL option in STM32L4 HAL (bug #969)(backported
to 18.2.2 and 17.6.5).
- HAL: Fixed incorrect checks on STM32_SAI2SEL option in STM32L4 HAL
(bug #968)(backported to 18.2.2 and 17.6.5).
- HAL: Fixed incorrect handling of PDIV dividers in STM32L4 HAL (bug #967)

2
testex/STM32/STM32L4xx/QSPI-N25Q128/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

2
testhal/STM32/STM32L4xx/ADC/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

2
testhal/STM32/STM32L4xx/CAN/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

2
testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

2
testhal/STM32/STM32L4xx/IRQ_STORM/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

2
testhal/STM32/multi/PAL/cfg/stm32l476_discovery/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_MSI
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

2
testhal/STM32/multi/QSPI-MFS/cfg/stm32l476_discovery/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_MSI
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*

2
testhal/STM32/multi/USB_CDC/cfg/stm32l476_discovery/mcuconf.h
View File

@ -88,7 +88,7 @@
#define STM32_CLK48SEL STM32_CLK48SEL_MSI
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*