mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12205 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
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cc826010ae
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@ -89,7 +89,7 @@
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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@ -88,7 +88,7 @@
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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@ -88,7 +88,7 @@
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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@ -92,6 +92,9 @@ static void hal_lld_backup_domain_init(void) {
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RCC->BDCR |= RCC_BDCR_RTCEN;
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RCC->BDCR |= RCC_BDCR_RTCEN;
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}
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}
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#endif /* HAL_USE_RTC */
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#endif /* HAL_USE_RTC */
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/* Low speed output mode.*/
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RCC->BDCR |= STM32_LSCOSEL;
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}
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}
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/*===========================================================================*/
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/*===========================================================================*/
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@ -291,7 +291,7 @@
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#define STM32_SWPMI1SEL_HSI16 (1 << 30) /**< SWPMI1 source is HSI16. */
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#define STM32_SWPMI1SEL_HSI16 (1 << 30) /**< SWPMI1 source is HSI16. */
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#define STM32_DFSDMSEL_MASK (1 << 31) /**< DFSDMSEL mask. */
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#define STM32_DFSDMSEL_MASK (1 << 31) /**< DFSDMSEL mask. */
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#define STM32_DFSDMSEL_PCLK1 (0 << 31) /**< DFSDM source is PCLK1. */
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#define STM32_DFSDMSEL_PCLK2 (0 << 31) /**< DFSDM source is PCLK2. */
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#define STM32_DFSDMSEL_SYSCLK (1 << 31) /**< DFSDM source is SYSCLK. */
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#define STM32_DFSDMSEL_SYSCLK (1 << 31) /**< DFSDM source is SYSCLK. */
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/** @} */
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/** @} */
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@ -2130,8 +2130,8 @@
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/**
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/**
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* @brief DFSDM clock frequency.
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* @brief DFSDM clock frequency.
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*/
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*/
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#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK1) || defined(__DOXYGEN__)
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#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK2) || defined(__DOXYGEN__)
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#define STM32_DFSDMCLK STM32_PCLK1
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#define STM32_DFSDMCLK STM32_PCLK2
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#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
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#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
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#define STM32_DFSDMCLK STM32_SYSCLK
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#define STM32_DFSDMCLK STM32_SYSCLK
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#else
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#else
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@ -141,6 +141,10 @@
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- EX: Updated LIS302DL to 1.1.0 (backported to 18.2.1).
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- EX: Updated LIS302DL to 1.1.0 (backported to 18.2.1).
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- EX: Updated LPS25H to 1.1.0 (backported to 18.2.1).
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- EX: Updated LPS25H to 1.1.0 (backported to 18.2.1).
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- EX: Updated LSM303DLHC to 1.1.0 (backported to 18.2.1).
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- EX: Updated LSM303DLHC to 1.1.0 (backported to 18.2.1).
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- HAL: Fixed option STM32_LSCOSEL not written in STM32L4 HAL (bug #970)
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(backported to 18.2.2 and 17.6.5).
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- HAL: Fixed invalid DFSDM1SEL option in STM32L4 HAL (bug #969)(backported
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to 18.2.2 and 17.6.5).
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- HAL: Fixed incorrect checks on STM32_SAI2SEL option in STM32L4 HAL
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- HAL: Fixed incorrect checks on STM32_SAI2SEL option in STM32L4 HAL
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(bug #968)(backported to 18.2.2 and 17.6.5).
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(bug #968)(backported to 18.2.2 and 17.6.5).
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- HAL: Fixed incorrect handling of PDIV dividers in STM32L4 HAL (bug #967)
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- HAL: Fixed incorrect handling of PDIV dividers in STM32L4 HAL (bug #967)
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@ -88,7 +88,7 @@
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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@ -88,7 +88,7 @@
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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#define STM32_CLK48SEL STM32_CLK48SEL_MSI
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#define STM32_CLK48SEL STM32_CLK48SEL_MSI
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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#define STM32_CLK48SEL STM32_CLK48SEL_MSI
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#define STM32_CLK48SEL STM32_CLK48SEL_MSI
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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#define STM32_CLK48SEL STM32_CLK48SEL_MSI
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#define STM32_CLK48SEL STM32_CLK48SEL_MSI
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1
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#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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/*
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