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STM32WB: use RCCv1 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14635 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
akscram 2021-08-10 22:48:05 +00:00
parent 6ad1a238cd
commit 2918634c1a
17 changed files with 1146 additions and 791 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h
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@ -43,8 +43,9 @@
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSI1_ENABLED TRUE
#define STM32_LSI2_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -79,7 +80,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

4
os/common/startup/ARMCMx/compilers/GCC/mk/rules.mk
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@ -275,9 +275,9 @@ clean: CLEAN_RULE_HOOK
@echo Cleaning
@echo - $(DEPDIR)
@-rm -fR $(DEPDIR)/* $(BUILDDIR)/* 2>/dev/null
@-if [ -d "$(DEPDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(DEPDIR)) 2>/dev/null; fi
@-if [ -d "$(DEPDIR)" ]; then rmdir -p $(subst ./,,$(DEPDIR)) 2>/dev/null; fi
@echo - $(BUILDDIR)
@-if [ -d "$(BUILDDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi
@-if [ -d "$(BUILDDIR)" ]; then rmdir -p $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi
@echo
@echo Done

4
os/hal/boards/ST_NUCLEO48_WB55CG_USB/board.h
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@ -45,10 +45,6 @@
#define STM32_LSEDRV (3U << 3U)
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 32000000U
#endif
/*
* Board voltages.
* Required for performance limits calculation.

4
os/hal/boards/ST_NUCLEO68_WB55RG/board.h
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@ -45,10 +45,6 @@
#define STM32_LSEDRV (3U << 3U)
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 32000000U
#endif
/*
* Board voltages.
* Required for performance limits calculation.

101
os/hal/ports/STM32/LLD/RCCv1/stm32_lsi_v2.inc Normal file
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@ -0,0 +1,101 @@
/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RCCv1/stm32_lsi12.inc
* @brief Shared LSI12 clock handler.
*
* @addtogroup STM32_LSI12_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/**
* @brief LSI clock frequency.
*/
#define STM32_LSICLK 32000U
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_RCC_HAS_LSI1)
#error "STM32_RCC_HAS_LSI1 not defined in stm32_registry.h"
#endif
#if !defined(STM32_RCC_HAS_LSI2)
#error "STM32_RCC_HAS_LSI2 not defined in stm32_registry.h"
#elif !defined(STM32_RCC_LSI2_TRIM_ADDR)
#error "STM32_RCC_LSI2_TRIM_ADDR not defined in stm32_registry.h"
#endif
/* Checks on configurations.*/
#if !defined(STM32_LSI1_ENABLED)
#error "STM32_LSI1_ENABLED not defined in mcuconf.h"
#endif
#if !defined(STM32_LSI2_ENABLED)
#error "STM32_LSI2_ENABLED not defined in mcuconf.h"
#endif
#if defined(STM32_LSI_ENABLED)
#error "STM32_LSI_ENABLED should not be defined in mcuconf.h"
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
__STATIC_INLINE void lsi_init(void) {
#if STM32_LSI1_ENABLED
/* LSI1 activation.*/
RCC->CSR |= RCC_CSR_LSI1ON;
while ((RCC->CSR & RCC_CSR_LSI1RDY) == 0U) {
}
#endif
#if STM32_LSI2_ENABLED
/* Set LSI2 trimming.*/
uint32_t trim = ((*(uint32_t *)(STM32_RCC_LSI2_TRIM_ADDR)) & 0xFUL);
RCC->CSR |= (trim << RCC_CSR_LSI2TRIM_Pos);
/* LSI2 activation.*/
RCC->CSR |= RCC_CSR_LSI2ON;
while ((RCC->CSR & RCC_CSR_LSI2RDY) == 0U) {
}
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

198
os/hal/ports/STM32/LLD/RCCv1/stm32_msi_v2.inc Normal file
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@ -0,0 +1,198 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RCCv1/stm32_msi_v2.inc
* @brief Shared MSI clock handler V2.
*
* @addtogroup STM32_MSI_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/**
* @name RCC_CR register bits definitions
* @{
*/
#define STM32_MSIRANGE_MASK (15U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_100K (0U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_200K (1U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_400K (2U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_800K (3U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_1M (4U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_2M (5U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_4M (6U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_8M (7U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_16M (8U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_24M (9U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_32M (10U << RCC_CR_MSIRANGE_Pos)
#define STM32_MSIRANGE_48M (11U << RCC_CR_MSIRANGE_Pos)
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_RCC_HAS_MSI)
#error "STM32_RCC_HAS_MSI not defined in stm32_registry.h"
#endif
/* Checks on configurations.*/
#if !defined(STM32_MSIPLL_ENABLED)
#error "STM32_MSIPLL_ENABLED not defined in mcuconf.h"
#endif
#if !defined(STM32_MSIRANGE)
#error "STM32_MSIRANGE not defined in mcuconf.h"
#endif
#if !defined(STM32_LSE_ENABLED)
#error "STM32_LSE_ENABLED not defined in mcuconf.h"
#endif
#if STM32_MSIPLL_ENABLED && !STM32_LSE_ENABLED
#error "STM32_MSIPLL_ENABLED requires LSE"
#endif
/**
* @brief MSI frequency.
*/
#if STM32_MSIRANGE == STM32_MSIRANGE_100K
#define STM32_MSICLK 100000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_200K
#define STM32_MSICLK 200000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_400K
#define STM32_MSICLK 400000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_800K
#define STM32_MSICLK 800000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
#define STM32_MSICLK 1000000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
#define STM32_MSICLK 2000000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
#define STM32_MSICLK 4000000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_8M
#define STM32_MSICLK 8000000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_16M
#define STM32_MSICLK 16000000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_24M
#define STM32_MSICLK 24000000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_32M
#define STM32_MSICLK 32000000U
#elif STM32_MSIRANGE == STM32_MSIRANGE_48M
#define STM32_MSICLK 48000000U
#else
#error "invalid STM32_MSIRANGE value specified"
#endif
/* Some headers do not have this definition.*/
#if !defined(RCC_CFGR_SWS_MSI)
#define RCC_CFGR_SWS_MSI 0U
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
__STATIC_INLINE void msi_enable(void) {
RCC->CR |= RCC_CR_MSION;
while ((RCC->CR & RCC_CR_MSIRDY) == 0U) {
/* Wait until MSI is stable.*/
}
}
__STATIC_INLINE void msi_disable(void) {
RCC->CR &= ~RCC_CR_MSION;
}
__STATIC_INLINE void msi_reset(void) {
/* Resetting MSI defaults.
Note from RM0432: MSIRANGE can be modified when MSI is OFF (MSION=0)
or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when
MSI is ON and NOT ready (MSION=1 and MSIRDY=0).*/
RCC->CR = (RCC->CR & ~RCC_CR_MSIRANGE_Msk) | RCC_CR_MSIRANGE_6;
/* Making sure MSI is active and ready.*/
msi_enable();
/* Clocking from MSI, in case MSI was not the default source.*/
RCC->CFGR = RCC_CFGR_SW_MSI;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) {
/* Wait until MSI is selected.*/
}
}
__STATIC_INLINE void msi_init(void) {
uint32_t cr;
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fall back clock when PLL the fails.
Trim fields are not altered from reset values.*/
/* MSIRANGE can be set only when MSI is OFF or READY, it is ready after
reset.*/
#if STM32_MSIPLL_ENABLED
cr = STM32_MSIRANGE | RCC_CR_MSIPLLEN | RCC_CR_MSION;
#else
cr = STM32_MSIRANGE | RCC_CR_MSION;
#endif
RCC->CR = cr;
while ((RCC->CR & RCC_CR_MSIRDY) == 0U) {
/* Wait until MSI is stable.*/
}
/* Clocking from MSI, in case MSI was not the default source.*/
RCC->CFGR = 0U;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
; /* Wait until MSI is selected. */
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

337
os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1_v2.inc Normal file
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@ -0,0 +1,337 @@
/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RCCv1/stm32_pllsai1_v2.inc
* @brief Shared PLLSAI1 handler.
*
* @addtogroup STM32_PLLSAI1_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_RCC_HAS_PLLSAI1)
#define STM32_RCC_HAS_PLLSAI1 FALSE
#endif
#if STM32_RCC_HAS_PLLSAI1
/* Checks on configurations.*/
#if !defined(STM32_PLLSRC)
#error "STM32_PLLSRC not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLSAI1N_VALUE)
#error "STM32_PLLSAI1N_VALUE not defined in mcuconf.h"
#endif
#if STM32_RCC_PLLSAI1_HAS_P && !defined(STM32_PLLSAI1P_VALUE)
#error "STM32_PLLSAI1P_VALUE not defined in mcuconf.h"
#endif
#if STM32_RCC_PLLSAI1_HAS_Q && !defined(STM32_PLLSAI1Q_VALUE)
#error "STM32_PLLSAI1Q_VALUE not defined in mcuconf.h"
#endif
#if STM32_RCC_PLLSAI1_HAS_R && !defined(STM32_PLLSAI1R_VALUE)
#error "STM32_PLLSAI1R_VALUE not defined in mcuconf.h"
#endif
/* Check on limits.*/
#if !defined(STM32_PLLIN_MAX)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLIN_MIN)
#error "STM32_PLLIN_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLSAI1VCO_MAX)
#error "STM32_PLLSAI1VCO_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLSAI1VCO_MIN)
#error "STM32_PLLSAI1VCO_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLSAI1N_VALUE_MAX)
#error "STM32_PLLSAI1N_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLSAI1N_VALUE_MIN)
#error "STM32_PLLSAI1N_VALUE_MIN not defined in hal_lld.h"
#endif
#if STM32_RCC_PLLSAI1_HAS_P
#if !defined(STM32_PLLSAI1P_VALUE_MAX)
#error "STM32_PLLSAI1P_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLSAI1P_VALUE_MIN)
#error "STM32_PLLSAI1P_VALUE_MIN not defined in hal_lld.h"
#endif
#endif /* STM32_RCC_PLLSAI1_HAS_P */
#if STM32_RCC_PLLSAI1_HAS_Q
#if !defined(STM32_PLLSAI1Q_VALUE_MAX)
#error "STM32_PLLSAI1Q_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLSAI1Q_VALUE_MIN)
#error "STM32_PLLSAI1Q_VALUE_MIN not defined in hal_lld.h"
#endif
#endif /* STM32_RCC_PLLSAI1_HAS_Q */
#if STM32_RCC_PLLSAI1_HAS_R
#if !defined(STM32_PLLSAI1R_VALUE_MAX)
#error "STM32_PLLSAI1R_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLSAI1R_VALUE_MIN)
#error "STM32_PLLSAI1R_VALUE_MIN not defined in hal_lld.h"
#endif
#endif /* STM32_RCC_PLLSAI1_HAS_R */
/* Input checks.*/
#if !defined(STM32_ACTIVATE_PLLSAI1)
#error "STM32_ACTIVATE_PLLSAI1 not defined in hal_lld.h"
#endif
#if STM32_RCC_PLLSAI1_HAS_P && !defined(STM32_PLLSAI1PEN)
#error "STM32_PLLSAI1PEN not defined in hal_lld.h"
#endif
#if STM32_RCC_PLLSAI1_HAS_Q && !defined(STM32_PLLSAI1QEN)
#error "STM32_PLLSAI1QEN not defined in hal_lld.h"
#endif
#if STM32_RCC_PLLSAI1_HAS_R && !defined(STM32_PLLSAI1REN)
#error "STM32_PLLSAI1REN not defined in hal_lld.h"
#endif
#if STM32_ACTIVATE_PLLSAI1 && (STM32_PLLSAI1CLKIN == 0)
#error "PLLSAI1 activation required but no PLL clock selected"
#endif
#if ((STM32_PLLSAI1CLKIN != 0) && \
((STM32_PLLSAI1CLKIN < STM32_PLLIN_MIN) || \
(STM32_PLLSAI1CLKIN > STM32_PLLIN_MAX))) || defined(__DOXYGEN__)
#error "STM32_PLLSAI1CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif
/**
* @brief STM32_PLLSAI1N field.
*/
#if ((STM32_PLLSAI1N_VALUE >= STM32_PLLSAI1N_VALUE_MIN) && \
(STM32_PLLSAI1N_VALUE <= STM32_PLLSAI1N_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << RCC_PLLSAI1CFGR_PLLN_Pos)
#else
#error "invalid STM32_PLLSAI1N_VALUE value specified"
#endif
/**
* @brief PLLSAI1 VCO frequency.
*/
#define STM32_PLLSAI1VCO (STM32_PLLSAI1CLKIN * STM32_PLLSAI1N_VALUE)
/*
* PLLSAI1 VCO frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1VCO < STM32_PLLSAI1VCO_MIN) || \
(STM32_PLLSAI1VCO > STM32_PLLSAI1VCO_MAX)) || defined(__DOXYGEN__)
#error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif
/*---------------------------------------------------------------------------*/
/* P output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_RCC_PLLSAI1_HAS_P || defined(__DOXYGEN__)
/**
* @brief STM32_PLLSAI1P field.
*/
#if STM32_PLLSAI1P_VALUE >= STM32_PLLSAI1P_VALUE_MIN && \
STM32_PLLSAI1P_VALUE <= STM32_PLLSAI1P_VALUE_MAX || defined(__DOXYGEN__)
#define STM32_PLLSAI1P ((STM32_PLLSAI1P_VALUE - 1) << RCC_PLLSAI1CFGR_PLLP_Pos)
#else
#error "invalid STM32_PLLSAI1P_VALUE value specified"
#endif
/**
* @brief PLLSAI1 P output clock frequency.
*/
#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
/*
* PLLSAI1-P output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || \
(STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX)) || defined(__DOXYGEN__)
#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif
#else /* !STM32_RCC_PLLSAI1_HAS_P */
#define STM32_PLLSAI1P 0U
#define STM32_PLLSAI1PEN 0U
#endif /* !STM32_RCC_PLLSAI1_HAS_P */
/*---------------------------------------------------------------------------*/
/* Q output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_RCC_PLLSAI1_HAS_Q || defined(__DOXYGEN__)
/**
* @brief STM32_PLLSAI1Q field.
*/
#if (STM32_PLLSAI1Q_VALUE >= STM32_PLLSAI1Q_VALUE_MIN && \
STM32_PLLSAI1Q_VALUE <= STM32_PLLSAI1Q_VALUE_MAX) || defined(__DOXYGEN__)
#define STM32_PLLSAI1Q ((STM32_PLLSAI1Q_VALUE - 1) << RCC_PLLSAI1CFGR_PLLQ_Pos)
#else
#error "invalid STM32_PLLSAI1Q_VALUE value specified"
#endif
/**
* @brief PLLSAI1 Q output clock frequency.
*/
#define STM32_PLLSAI1_Q_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
/*
* PLLSAI1-Q output frequency range check.
*/
#if (STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || \
(STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX))) || defined(__DOXYGEN__)
#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#endif
#else /* !STM32_RCC_PLLSAI1_HAS_Q */
#define STM32_PLLSAI1Q 0U
#define STM32_PLLSAI1QEN 0U
#endif /* !STM32_RCC_PLLSAI1_HAS_Q */
/*---------------------------------------------------------------------------*/
/* R output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_RCC_PLLSAI1_HAS_R || defined(__DOXYGEN__)
/**
* @brief STM32_PLLSAI1R field.
*/
#if ((STM32_PLLSAI1R_VALUE >= STM32_PLLSAI1R_VALUE_MIN) && \
(STM32_PLLSAI1R_VALUE <= STM32_PLLSAI1R_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI1R ((STM32_PLLSAI1R_VALUE - 1) << RCC_PLLSAI1CFGR_PLLR_Pos)
#else
#error "invalid STM32_PLLSAI1R_VALUE value specified"
#endif
/**
* @brief PLLSAI1 R output clock frequency.
*/
#define STM32_PLLSAI1_R_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1R_VALUE)
/*
* PLLSAI1-R output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || \
(STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX)) || defined(__DOXYGEN__)
#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif
#else /* !STM32_RCC_PLLSAI1_HAS_R */
#define STM32_PLLSAI1R 0U
#define STM32_PLLSAI1REN 0U
#endif /* !STM32_RCC_PLLSAI1_HAS_R */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
__STATIC_INLINE bool pllsai1_not_locked(void) {
return (bool)((RCC->CR & RCC_CR_PLLSAI1RDY) == 0U);
}
__STATIC_INLINE void pllsai1_wait_lock(void) {
while (pllsai1_not_locked()) {
/* Waiting for PLLSAI1 lock.*/
}
}
#endif /* STM32_RCC_HAS_PLLSAI1 */
__STATIC_INLINE void pllsai1_init(void) {
#if STM32_RCC_HAS_PLLSAI1
#if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 activation.*/
RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN |
STM32_PLLSAI1Q | STM32_PLLSAI1QEN |
STM32_PLLSAI1P | STM32_PLLSAI1PEN |
STM32_PLLSAI1N;
RCC->CR |= RCC_CR_PLLSAI1ON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0U)
;
#endif
#endif
}
__STATIC_INLINE void pllsai1_deinit(void) {
#if STM32_RCC_HAS_PLLSAI1
#if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 de-activation.*/
RCC->PLLSAI1CFGR &= ~RCC_CR_PLLSAI1ON;
#endif
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

288
os/hal/ports/STM32/STM32WBxx/hal_lld.c
View File

@ -49,54 +49,65 @@ uint32_t SystemCoreClock = STM32_HCLK;
/*===========================================================================*/
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing RTC clock source impossible without resetting
* of the whole BKP domain.
* @brief Safe setting of flash ACR register.
*
* @param[in] acr value for the ACR register
*/
static void hal_lld_backup_domain_init(void) {
__STATIC_INLINE void flash_set_acr(uint32_t acr) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
FLASH->ACR = acr;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) {
/* Waiting for flash wait states setup.*/
}
}
#if STM32_LSE_ENABLED
/* LSE activation.*/
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Wait until LSE is stable. */
#endif
#if STM32_MSIPLL_ENABLED
/* MSI PLL activation depends on LSE. Reactivating and checking for
MSI stability.*/
RCC->CR |= RCC_CR_MSIPLLEN;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Wait until MSI is stable. */
#endif
#if HAL_USE_RTC
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
RCC->BDCR |= STM32_RTCSEL;
/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
/**
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
*/
__STATIC_INLINE void hal_lld_set_static_pwr(void) {
/* Static PWR configurations.*/
PWR->CR3 = STM32_PWR_CR3;
PWR->CR4 = STM32_PWR_CR4;
PWR->PUCRA = STM32_PWR_PUCRA;
PWR->PDCRA = STM32_PWR_PDCRA;
PWR->PUCRB = STM32_PWR_PUCRB;
PWR->PDCRB = STM32_PWR_PDCRB;
PWR->PUCRC = STM32_PWR_PUCRC;
PWR->PDCRC = STM32_PWR_PDCRC;
PWR->PUCRD = STM32_PWR_PUCRD;
PWR->PDCRD = STM32_PWR_PDCRD;
PWR->PUCRE = STM32_PWR_PUCRE;
PWR->PDCRE = STM32_PWR_PDCRE;
PWR->PUCRH = STM32_PWR_PUCRH;
PWR->PDCRH = STM32_PWR_PDCRH;
}
#endif /* HAL_USE_RTC */
/* Low speed output mode.*/
RCC->BDCR |= STM32_LSCOSEL;
/**
* @brief Initializes static muxes and dividers.
*/
__STATIC_INLINE void hal_lld_set_static_clocks(void) {
uint32_t ccipr;
/* Clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Waiting for PPRE2, PPRE1 and HPRE applied. */
while ((RCC->CFGR & (RCC_CFGR_PPRE2F_Msk | RCC_CFGR_PPRE1F_Msk |
RCC_CFGR_HPREF_Msk)) !=
(RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF))
;
/* CCIPR2 register initialization, note, must take care of the _OFF
pseudo settings.*/
ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_CLK48SEL |
STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C1SEL |
STM32_USART1SEL | STM32_LPUART1SEL;
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
ccipr |= STM32_SAI1SEL;
#endif
RCC->CCIPR = ccipr;
}
/*===========================================================================*/
@ -114,24 +125,14 @@ static void hal_lld_backup_domain_init(void) {
*/
void hal_lld_init(void) {
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~0);
rccResetAHB2(~STM32_GPIO_EN_MASK);
rccResetAHB3(~0);
rccResetAPB1R1(~0);
rccResetAPB1R2(~0);
rccResetAPB2(~0);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
/* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* NVIC initialization.*/
nvicInit();
/* IRQ subsystem initialization.*/
irqInit();
@ -157,138 +158,57 @@ void hal_lld_init(void) {
*/
void stm32_clock_init(void) {
#if 1
RCC_TypeDef *rcc = RCC; /* For inspection.*/
(void)rcc;
#endif
#if !STM32_NO_INIT
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fall back clock when PLL the fails.
Trim fields are not altered from reset values.*/
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~0);
rccResetAHB2(~STM32_GPIO_EN_MASK);
rccResetAHB3(~0);
rccResetAPB1R1(~0);
rccResetAPB1R2(~0);
rccResetAPB2(~0);
/* MSIRANGE can be set only when MSI is OFF or READY.*/
RCC->CR = RCC_CR_MSION;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Wait until MSI is stable. */
/* Flash setup for selected MSI speed setting.*/
flash_set_acr(FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
STM32_MSI_FLASHBITS);
/* Clocking from MSI, in case MSI was not the default source.*/
RCC->CFGR = 0;
while ((RCC->CFGR & STM32_SW_MASK) != STM32_SW_MSI)
; /* Wait until MSI is selected. */
/* Static PWR configurations.*/
hal_lld_set_static_pwr();
/* Core voltage setup.*/
PWR->CR1 = STM32_VOS;
/* Core voltage setup, backup domain access enabled and left open.*/
PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
/* Additional PWR configurations.*/
PWR->CR2 = STM32_PWR_CR2;
/* Wait until regulator is stable. */
while ((PWR->SR2 & PWR_SR2_VOSF) != 0)
;
#if STM32_HSI16_ENABLED
/* HSI activation.*/
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) == 0)
; /* Wait until HSI16 is stable. */
#endif
/* MSI clock reset.*/
msi_reset();
#if STM32_HSI48_ENABLED
/* HSI activation.*/
RCC->CRRCR |= RCC_CRRCR_HSI48ON;
while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
; /* Wait until HSI48 is stable. */
#endif
/* Backup domain reset.*/
bd_reset();
#if STM32_HSE_ENABLED
/* HSE activation.*/
RCC->CR |= RCC_CR_HSEON;
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Wait until HSE is stable. */
/* Clocks setup.*/
lse_init();
lsi_init();
msi_init();
hsi16_init();
hsi48_init();
hse32_init();
/* HSE PRE setting.*/
RCC->CR |= STM32_HSEPRE;
#endif
/* Backup domain initializations.*/
bd_init();
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSI1ON;
while ((RCC->CSR & RCC_CSR_LSI1RDY) == 0)
; /* Wait until LSI is stable. */
#endif
/* Static clocks setup.*/
hal_lld_set_static_clocks();
/* Backup domain access enabled and left open.*/
PWR->CR1 |= PWR_CR1_DBP;
#if STM32_LSE_ENABLED
/* LSE activation.*/
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Wait until LSE is stable. */
#endif
/* Flash setup for selected MSI speed setting.*/
FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
STM32_MSI_FLASHBITS;
/* Changing MSIRANGE to configured value.*/
RCC->CR |= STM32_MSIRANGE;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
;
/* MSI is configured SYSCLK source so wait for it to be stable as well.*/
while ((RCC->CFGR & STM32_SW_MASK) != STM32_SW_MSI)
;
#if STM32_MSIPLL_ENABLED
/* MSI PLL (to LSE) activation */
RCC->CR |= RCC_CR_MSIPLLEN;
#endif
#if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1
/* PLLM and PLLSRC are common to all PLLs.*/
RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
STM32_PLLQ | STM32_PLLQEN |
STM32_PLLP | STM32_PLLPEN |
STM32_PLLN | STM32_PLLM |
STM32_PLLSRC;
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CR |= RCC_CR_PLLON;
/* Waiting for PLL clock.*/
while ((RCC->CR & RCC_CR_PLLRDY) == 0)
;
#endif
#if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 activation.*/
RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN |
STM32_PLLSAI1Q | STM32_PLLSAI1QEN |
STM32_PLLSAI1P | STM32_PLLSAI1PEN |
STM32_PLLSAI1N;
RCC->CR |= RCC_CR_PLLSAI1ON;
/* Waiting for PLL clock.*/
while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0)
;
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Waiting for PPRE2, PPRE1 and HPRE applied. */
while ((RCC->CFGR & (RCC_CFGR_PPRE2F_Msk | RCC_CFGR_PPRE1F_Msk |
RCC_CFGR_HPREF_Msk)) !=
(RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF))
;
/* PLLs activation, if required.*/
pll_init();
pllsai1_init();
/* Extended clock recovery register (HCLK2, HCLK4, HCLK5). */
RCC->EXTCFGR = STM32_RFCSSSEL | STM32_C2HPRE | STM32_SHDHPRE;
@ -299,24 +219,9 @@ void stm32_clock_init(void) {
(RCC_EXTCFGR_C2HPREF | RCC_EXTCFGR_SHDHPREF))
;
/* CCIPR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_CLK48SEL |
STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C1SEL |
STM32_USART1SEL | STM32_LPUART1SEL;
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
ccipr |= STM32_SAI1SEL;
#endif
RCC->CCIPR = ccipr;
}
/* Set flash WS's for SYSCLK source */
if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
}
flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS);
}
/* Switching to the configured SYSCLK source if it is different from MSI.*/
@ -329,10 +234,7 @@ void stm32_clock_init(void) {
/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
}
flash_set_acr((FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS);
}
#endif /* STM32_NO_INIT */

821
os/hal/ports/STM32/STM32WBxx/hal_lld.h
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File diff suppressed because it is too large Load Diff

3
os/hal/ports/STM32/STM32WBxx/platform.mk
View File

@ -32,14 +32,15 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
# Shared variables
ALLCSRC += $(PLATFORMSRC)

22
os/hal/ports/STM32/STM32WBxx/stm32_registry.h
View File

@ -74,6 +74,28 @@
#if defined(STM32WB55xx) || defined(__DOXYGEN__)
/* RCC attributes.*/
#define STM32_RCC_HAS_HSI16 TRUE
#define STM32_RCC_HAS_HSI48 TRUE
#define STM32_RCC_HAS_MSI TRUE
#define STM32_RCC_HAS_LSI FALSE
#define STM32_RCC_HAS_LSI1 TRUE
#define STM32_RCC_HAS_LSI2 TRUE
#define STM32_RCC_LSI2_TRIM_ADDR 0x1FFF7548U
#define STM32_RCC_HAS_LSE TRUE
#define STM32_RCC_HAS_HSE FALSE
#define STM32_RCC_HAS_HSE32 TRUE
#define STM32_RCC_HAS_PLL TRUE
#define STM32_RCC_PLL_HAS_P TRUE
#define STM32_RCC_PLL_HAS_Q TRUE
#define STM32_RCC_PLL_HAS_R TRUE
#define STM32_RCC_HAS_PLLSAI1 TRUE
#define STM32_RCC_PLLSAI1_HAS_P TRUE
#define STM32_RCC_PLLSAI1_HAS_Q TRUE
#define STM32_RCC_PLLSAI1_HAS_R TRUE
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE

7
testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h
View File

@ -43,8 +43,9 @@
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSI1_ENABLED TRUE
#define STM32_LSI2_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -79,7 +80,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

7
testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h
View File

@ -43,8 +43,9 @@
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSI1_ENABLED TRUE
#define STM32_LSI2_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -79,7 +80,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

7
testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h
View File

@ -43,8 +43,9 @@
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSI1_ENABLED TRUE
#define STM32_LSI2_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
@ -79,7 +80,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1QCLK
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

5
testhal/STM32/multi/USB_CDC/cfg/stm32wb55cg_nucleo48/mcuconf.h
View File

@ -43,8 +43,9 @@
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSI1_ENABLED FALSE
#define STM32_LSI2_ENABLED FALSE
#define STM32_HSE32_ENABLED FALSE
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M

5
testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h
View File

@ -43,8 +43,9 @@
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSI1_ENABLED FALSE
#define STM32_LSI2_ENABLED FALSE
#define STM32_HSE32_ENABLED FALSE
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M

7
tools/ftl/processors/conf/mcuconf_stm32wb55xx/mcuconf.h.ftl
View File

@ -54,8 +54,9 @@
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"}
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
#define STM32_LSI1_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
#define STM32_LSI2_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
#define STM32_HSE32_ENABLED ${doc.STM32_HSE32_ENABLED!"FALSE"}
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
#define STM32_MSIPLL_ENABLED ${doc.STM32_MSIPLL_ENABLED!"FALSE"}
#define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"}
@ -90,7 +91,7 @@
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLLSAI1"}
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLLSAI1QCLK"}
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}